^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * dm9000 Ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DM9000X_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DM9000X_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DM9000_ID 0x90000A46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* although the registers are 16 bit, they are 32-bit aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DM9000_NCR 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DM9000_NSR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DM9000_TCR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DM9000_TSR1 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DM9000_TSR2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DM9000_RCR 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DM9000_RSR 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DM9000_ROCR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DM9000_BPTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DM9000_FCTR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DM9000_FCR 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DM9000_EPCR 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DM9000_EPAR 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DM9000_EPDRL 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DM9000_EPDRH 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DM9000_WCR 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DM9000_PAR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DM9000_MAR 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DM9000_GPCR 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DM9000_GPR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DM9000_TRPAL 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DM9000_TRPAH 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DM9000_RWPAL 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DM9000_RWPAH 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DM9000_VIDL 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DM9000_VIDH 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DM9000_PIDL 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DM9000_PIDH 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define DM9000_CHIPR 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DM9000_SMCR 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DM9000_ETXCSR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define DM9000_TCCR 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define DM9000_RCSR 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CHIPR_DM9000A 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CHIPR_DM9000B 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DM9000_MRCMDX 0xF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DM9000_MRCMD 0xF2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DM9000_MRRL 0xF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DM9000_MRRH 0xF5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DM9000_MWCMDX 0xF6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DM9000_MWCMD 0xF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DM9000_MWRL 0xFA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DM9000_MWRH 0xFB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DM9000_TXPLL 0xFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DM9000_TXPLH 0xFD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DM9000_ISR 0xFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DM9000_IMR 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define NCR_EXT_PHY (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define NCR_WAKEEN (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define NCR_FCOL (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NCR_FDX (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NCR_RESERVED (3<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define NCR_MAC_LBK (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define NCR_RST (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define NSR_SPEED (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NSR_LINKST (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define NSR_WAKEST (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define NSR_TX2END (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define NSR_TX1END (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define NSR_RXOV (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TCR_TJDIS (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TCR_EXCECM (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TCR_PAD_DIS2 (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TCR_CRC_DIS2 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TCR_PAD_DIS1 (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TCR_CRC_DIS1 (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TCR_TXREQ (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TSR_TJTO (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TSR_LC (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TSR_NC (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TSR_LCOL (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TSR_COL (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TSR_EC (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RCR_WTDIS (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define RCR_DIS_LONG (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RCR_DIS_CRC (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RCR_ALL (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RCR_RUNT (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define RCR_PRMSC (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RCR_RXEN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RSR_RF (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RSR_MF (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RSR_LCS (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RSR_RWTO (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RSR_PLE (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define RSR_AE (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define RSR_CE (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define RSR_FOE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define WCR_LINKEN (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define WCR_SAMPLEEN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define WCR_MAGICEN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define WCR_LINKST (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define WCR_SAMPLEST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define WCR_MAGICST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FCTR_HWOT(ot) (( ot & 0xf ) << 4 )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FCTR_LWOT(ot) ( ot & 0xf )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMR_PAR (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMR_ROOM (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMR_ROM (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMR_PTM (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMR_PRM (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ISR_ROOS (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ISR_ROS (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ISR_PTS (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ISR_PRS (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ISR_CLR_STATUS (ISR_ROOS | ISR_ROS | ISR_PTS | ISR_PRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EPCR_REEP (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EPCR_WEP (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EPCR_EPOS (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EPCR_ERPRR (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EPCR_ERPRW (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define EPCR_ERRE (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GPCR_GEP_CNTL (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TCCR_IP (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TCCR_TCP (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TCCR_UDP (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RCSR_UDP_BAD (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define RCSR_TCP_BAD (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define RCSR_IP_BAD (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define RCSR_UDP (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define RCSR_TCP (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define RCSR_IP (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define RCSR_CSUM (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RCSR_DISCARD (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DM9000_PKT_RDY 0x01 /* Packet ready to receive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DM9000_PKT_ERR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DM9000_PKT_MAX 1536 /* Received packet max size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* DM9000A / DM9000B definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMR_LNKCHNG (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMR_UNDERRUN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ISR_LNKCHNG (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ISR_UNDERRUN (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Davicom MII registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MII_DM_DSPCR 0x1b /* DSP Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define DSPCR_INIT_PARAM 0xE100 /* DSP init parameter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* _DM9000X_H_ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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