^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Copyright, 1988-1992, Russell Nelson, Crynwr Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) the Free Software Foundation, version 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) You should have received a copy of the GNU General Public License
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) along with this program; if not, write to the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PP_ChipID 0x0000 /* offset 0h -> Corp -ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* offset 2h -> Model/Product Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* offset 3h -> Chip Revision Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PP_ISAIOB 0x0020 /* IO base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PP_CS8900_ISAINT 0x0022 /* ISA interrupt select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PP_CS8920_ISAINT 0x0370 /* ISA interrupt select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PP_CS8900_ISADMA 0x0024 /* ISA Rec DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PP_CS8920_ISADMA 0x0374 /* ISA Rec DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PP_ISASOF 0x0026 /* ISA DMA offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PP_DmaFrameCnt 0x0028 /* ISA DMA Frame count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PP_DmaByteCnt 0x002A /* ISA DMA Byte count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PP_CS8900_ISAMemB 0x002C /* Memory base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PP_CS8920_ISAMemB 0x0348 /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PP_ISABootBase 0x0030 /* Boot Prom base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PP_ISABootMask 0x0034 /* Boot Prom Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* EEPROM data and command registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PP_EECMD 0x0040 /* NVR Interface Command register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PP_EEData 0x0042 /* NVR Interface Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PP_DebugReg 0x0044 /* Debug Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PP_RxCFG 0x0102 /* Rx Bus config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PP_RxCTL 0x0104 /* Receive Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PP_TxCFG 0x0106 /* Transmit Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PP_TxCMD 0x0108 /* Transmit Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PP_BufCFG 0x010A /* Bus configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PP_LineCTL 0x0112 /* Line Config Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PP_SelfCTL 0x0114 /* Self Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PP_BusCTL 0x0116 /* ISA bus control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PP_TestCTL 0x0118 /* Test Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PP_AutoNegCTL 0x011C /* Auto Negotiation Ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PP_ISQ 0x0120 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PP_RxEvent 0x0124 /* Rx Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PP_TxEvent 0x0128 /* Tx Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PP_BufEvent 0x012C /* Bus Event Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PP_RxMiss 0x0130 /* Receive Miss Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PP_TxCol 0x0132 /* Transmit Collision Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PP_LineST 0x0134 /* Line State Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PP_SelfST 0x0136 /* Self State register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PP_BusST 0x0138 /* Bus Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PP_TDR 0x013C /* Time Domain Reflectometry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PP_AutoNegST 0x013E /* Auto Neg Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PP_TxCommand 0x0144 /* Tx Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PP_TxLength 0x0146 /* Tx Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PP_LAF 0x0150 /* Hash Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PP_IA 0x0158 /* Physical Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PP_RxStatus 0x0400 /* Receive start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PP_RxLength 0x0402 /* Receive Length of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PP_RxFrame 0x0404 /* Receive frame pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PP_TxFrame 0x0A00 /* Transmit frame pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Primary I/O Base Address. If no I/O base is supplied by the user, then this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* can be used as the default I/O base to access the PacketPage Area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DEFAULTIOBASE 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FIRST_IO 0x020C /* First I/O port to check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define LAST_IO 0x037C /* Last I/O port to check (+10h) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ADD_MASK 0x3000 /* Mask it use of the ADD_PORT register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ADD_SIG 0x3000 /* Expected ID signature */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* On Macs, we only need use the ISA I/O stuff until we do MEMORY_ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifdef CONFIG_MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define LCSLOTBASE 0xfee00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MMIOBASE 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CHIP_EISA_ID_SIG 0x630E /* Product ID Code for Crystal Chip (CS8900 spec 4.3) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CHIP_EISA_ID_SIG_STR "0x630E"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #ifdef IBMEIPKT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EISA_ID_SIG 0x4D24 /* IBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define PART_NO_SIG 0x1010 /* IBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MONGOOSE_BIT 0x0000 /* IBM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EISA_ID_SIG 0x630E /* PnP Vendor ID (same as chip id for Crystal board) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PART_NO_SIG 0x4000 /* ID code CS8920 board (PnP Vendor Product code) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MONGOOSE_BIT 0x2000 /* PART_NO_SIG + MONGOOSE_BUT => ID of mongoose */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define PRODUCT_ID_ADD 0x0002 /* Address of product ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* Mask to find out the types of registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_TYPE_MASK 0x001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Eeprom Commands */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ERSE_WR_ENBL 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ERSE_WR_DISABLE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Defines Control/Config register quintuplet numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RX_BUF_CFG 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RX_CONTROL 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TX_CFG 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TX_COMMAND 0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BUF_CFG 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LINE_CONTROL 0x0013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SELF_CONTROL 0x0015
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BUS_CONTROL 0x0017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEST_CONTROL 0x0019
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Defines Status/Count registers quintuplet numbers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RX_EVENT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TX_EVENT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BUF_EVENT 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RX_MISS_COUNT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TX_COL_COUNT 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LINE_STATUS 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SELF_STATUS 0x0016
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BUS_STATUS 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TDR 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* PP_RxCFG - Receive Configuration and Interrupt Mask bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define SKIP_1 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RX_STREAM_ENBL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RX_OK_ENBL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RX_DMA_ONLY 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AUTO_RX_DMA 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BUFFER_CRC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RX_CRC_ERROR_ENBL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define RX_RUNT_ENBL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define RX_EXTRA_DATA_ENBL 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* PP_RxCTL - Receive Control bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define RX_IA_HASH_ACCEPT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define RX_PROM_ACCEPT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define RX_OK_ACCEPT 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RX_MULTCAST_ACCEPT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RX_IA_ACCEPT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define RX_BROADCAST_ACCEPT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define RX_BAD_CRC_ACCEPT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define RX_RUNT_ACCEPT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define RX_EXTRA_DATA_ACCEPT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RX_ALL_ACCEPT (RX_PROM_ACCEPT|RX_BAD_CRC_ACCEPT|RX_RUNT_ACCEPT|RX_EXTRA_DATA_ACCEPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Default receive mode - individually addressed, broadcast, and error free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DEF_RX_ACCEPT (RX_IA_ACCEPT | RX_BROADCAST_ACCEPT | RX_OK_ACCEPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* PP_TxCFG - Transmit Configuration Interrupt Mask bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TX_LOST_CRS_ENBL 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TX_SQE_ERROR_ENBL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TX_OK_ENBL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TX_LATE_COL_ENBL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TX_JBR_ENBL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TX_ANY_COL_ENBL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TX_16_COL_ENBL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* PP_TxCMD - Transmit Command bit definition - Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TX_START_4_BYTES 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TX_START_64_BYTES 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TX_START_128_BYTES 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TX_START_ALL_BYTES 0x00C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TX_FORCE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TX_ONE_COL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TX_TWO_PART_DEFF_DISABLE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TX_NO_CRC 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TX_RUNT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* PP_BufCFG - Buffer Configuration Interrupt Mask bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GENERATE_SW_INTERRUPT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RX_DMA_ENBL 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define READY_FOR_TX_ENBL 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TX_UNDERRUN_ENBL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define RX_MISS_ENBL 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define RX_128_BYTE_ENBL 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TX_COL_COUNT_OVRFLOW_ENBL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RX_MISS_COUNT_OVRFLOW_ENBL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define RX_DEST_MATCH_ENBL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* PP_LineCTL - Line Control bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SERIAL_RX_ON 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SERIAL_TX_ON 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define AUI_ONLY 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AUTO_AUI_10BASET 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MODIFIED_BACKOFF 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define NO_AUTO_POLARITY 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TWO_PART_DEFDIS 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define LOW_RX_SQUELCH 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* PP_SelfCTL - Software Self Control bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define POWER_ON_RESET 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SW_STOP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SLEEP_ON 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AUTO_WAKEUP 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HCB0_ENBL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HCB1_ENBL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HCB0 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HCB1 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* PP_BusCTL - ISA Bus Control bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define RESET_RX_DMA 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MEMORY_ON 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define DMA_BURST_MODE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IO_CHANNEL_READY_ON 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define RX_DMA_SIZE_64K 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ENABLE_IRQ 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* PP_TestCTL - Test Control bit definition - Read/write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LINK_OFF 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ENDEC_LOOPBACK 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AUI_LOOPBACK 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define BACKOFF_OFF 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define FDX_8900 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FAST_TEST 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* PP_RxEvent - Receive Event Bit definition - Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define RX_IA_HASHED 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define RX_DRIBBLE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define RX_OK 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RX_HASHED 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RX_IA 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define RX_BROADCAST 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define RX_CRC_ERROR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define RX_RUNT 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define RX_EXTRA_DATA 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HASH_INDEX_MASK 0x0FC00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* PP_TxEvent - Transmit Event Bit definition - Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TX_LOST_CRS 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TX_SQE_ERROR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TX_OK 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TX_LATE_COL 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TX_JBR 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TX_16_COL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TX_SEND_OK_BITS (TX_OK|TX_LOST_CRS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TX_COL_COUNT_MASK 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* PP_BufEvent - Buffer Event Bit definition - Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define SW_INTERRUPT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define RX_DMA 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define READY_FOR_TX 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TX_UNDERRUN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define RX_MISS 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define RX_128_BYTE 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TX_COL_OVRFLW 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define RX_MISS_OVRFLW 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define RX_DEST_MATCH 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* PP_LineST - Ethernet Line Status bit definition - Read-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define LINK_OK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define AUI_ON 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TENBASET_ON 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define POLARITY_OK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CRS_OK 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* PP_SelfST - Chip Software Status bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ACTIVE_33V 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define INIT_DONE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SI_BUSY 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EEPROM_PRESENT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define EEPROM_OK 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define EL_PRESENT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define EE_SIZE_64 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* PP_BusST - ISA Bus Status bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TX_BID_ERROR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define READY_FOR_TX_NOW 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* PP_AutoNegCTL - Auto Negotiation Control bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RE_NEG_NOW 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ALLOW_FDX 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define AUTO_NEG_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define NLP_ENABLE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define FORCE_FDX 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define AUTO_NEG_BITS (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define AUTO_NEG_MASK (FORCE_FDX|NLP_ENABLE|AUTO_NEG_ENABLE|ALLOW_FDX|RE_NEG_NOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* PP_AutoNegST - Auto Negotiation Status bit definition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define AUTO_NEG_BUSY 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define FLP_LINK 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define FLP_LINK_GOOD 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define LINK_FAULT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HDX_ACTIVE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define FDX_ACTIVE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* The following block defines the ISQ event types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ISQ_RECEIVER_EVENT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ISQ_TRANSMITTER_EVENT 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ISQ_BUFFER_EVENT 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ISQ_RX_MISS_EVENT 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ISQ_TX_COL_EVENT 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define ISQ_EVENT_MASK 0x003F /* ISQ mask to find out type of event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define ISQ_HIST 16 /* small history buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define AUTOINCREMENT 0x8000 /* Bit mask to set bit-15 for autoincrement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TXRXBUFSIZE 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define RXDMABUFSIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define RXDMASIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TXRX_LENGTH_MASK 0x07FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* rx options bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RCV_WITH_RXON 1 /* Set SerRx ON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RCV_COUNTS 2 /* Use Framecnt1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RCV_PONG 4 /* Pong respondent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RCV_DONG 8 /* Dong operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RCV_POLLING 0x10 /* Poll RxEvent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RCV_ISQ 0x20 /* Use ISQ, int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RCV_AUTO_DMA 0x100 /* Set AutoRxDMAE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RCV_DMA 0x200 /* Set RxDMA only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define RCV_DMA_ALL 0x400 /* Copy all DMA'ed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define RCV_FIXED_DATA 0x800 /* Every frame same */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define RCV_IO 0x1000 /* Use ISA IO only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define RCV_MEMORY 0x2000 /* Use ISA Memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define RAM_SIZE 0x1000 /* The card has 4k bytes or RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PKT_START PP_TxFrame /* Start of packet RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define RX_FRAME_PORT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TX_FRAME_PORT RX_FRAME_PORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TX_CMD_PORT 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TX_NOW 0x0000 /* Tx packet after 5 bytes copied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TX_AFTER_381 0x0040 /* Tx packet after 381 bytes copied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TX_AFTER_ALL 0x00c0 /* Tx packet after all bytes copied */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TX_LEN_PORT 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ISQ_PORT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define ADD_PORT 0x000A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DATA_PORT 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define EEPROM_WRITE_EN 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EEPROM_WRITE_DIS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EEPROM_WRITE_CMD 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EEPROM_READ_CMD 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* Receive Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Description of header of each packet in receive area of memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define RBUF_EVENT_LOW 0 /* Low byte of RxEvent - status of received frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define RBUF_EVENT_HIGH 1 /* High byte of RxEvent - status of received frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define RBUF_LEN_LOW 2 /* Length of received data - low byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define RBUF_LEN_HI 3 /* Length of received data - high byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define RBUF_HEAD_LEN 4 /* Length of this header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define CHIP_READ 0x1 /* Used to mark state of the repins code (chip or dma) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DMA_READ 0x2 /* Used to mark state of the repins code (chip or dma) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* for bios scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #ifdef CSDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* use these values for debugging bios scan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define BIOS_START_SEG 0x00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BIOS_OFFSET_INC 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define BIOS_START_SEG 0x0c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define BIOS_OFFSET_INC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define BIOS_LAST_OFFSET 0x0fc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Byte offsets into the EEPROM configuration buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define ISA_CNF_OFFSET 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TX_CTL_OFFSET (ISA_CNF_OFFSET + 8) /* 8900 eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define AUTO_NEG_CNF_OFFSET (ISA_CNF_OFFSET + 8) /* 8920 eeprom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* the assumption here is that the bits in the eeprom are generally */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* in the same position as those in the autonegctl register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Of course the IMM bit is not in that register so it must be */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* masked out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define EE_FORCE_FDX 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define EE_NLP_ENABLE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define EE_AUTO_NEG_ENABLE 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define EE_ALLOW_FDX 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define EE_AUTO_NEG_CNF_MASK (EE_FORCE_FDX|EE_NLP_ENABLE|EE_AUTO_NEG_ENABLE|EE_ALLOW_FDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMM_BIT 0x0040 /* ignore missing media */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define ADAPTER_CNF_OFFSET (AUTO_NEG_CNF_OFFSET + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define A_CNF_10B_T 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define A_CNF_AUI 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define A_CNF_10B_2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define A_CNF_MEDIA_TYPE 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define A_CNF_MEDIA_AUTO 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define A_CNF_MEDIA_10B_T 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define A_CNF_MEDIA_AUI 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define A_CNF_MEDIA_10B_2 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define A_CNF_DC_DC_POLARITY 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define A_CNF_NO_AUTO_POLARITY 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define A_CNF_LOW_RX_SQUELCH 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define A_CNF_EXTND_10B_2 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define PACKET_PAGE_OFFSET 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /* Bit definitions for the ISA configuration word from the EEPROM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define INT_NO_MASK 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define DMA_NO_MASK 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define ISA_DMA_SIZE 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define ISA_AUTO_RxDMA 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define ISA_RxDMA 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DMA_BURST 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define STREAM_TRANSFER 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ANY_ISA_DMA (ISA_AUTO_RxDMA | ISA_RxDMA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /* DMA controller registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define DMA_BASE 0x00 /* DMA controller base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DMA_BASE_2 0x0C0 /* DMA controller base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DMA_STAT 0x0D0 /* DMA controller status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define DMA_MASK 0x0D4 /* DMA controller mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define DMA_MODE 0x0D6 /* DMA controller mode register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define DMA_RESETFF 0x0D8 /* DMA controller first/last flip flop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) /* DMA data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define DMA_DISABLE 0x04 /* Disable channel n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define DMA_ENABLE 0x00 /* Enable channel n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Demand transfers, incr. address, auto init, writes, ch. n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define DMA_RX_MODE 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* Demand transfers, incr. address, auto init, reads, ch. n */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define DMA_TX_MODE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define DMA_SIZE (16*1024) /* Size of dma buffer - 16k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CS8900 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CS8920 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CS8920M 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define REVISON_BITS 0x1F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define EEVER_NUMBER 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CHKSUM_LEN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CHKSUM_VAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define START_EEPROM_DATA 0x001c /* Offset into eeprom for start of data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define IRQ_MAP_EEPROM_DATA 0x0046 /* Offset into eeprom for the IRQ map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define IRQ_MAP_LEN 0x0004 /* No of bytes to read for the IRQ map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define PNP_IRQ_FRMT 0x0022 /* PNP small item IRQ format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CS8900_IRQ_MAP 0x1c20 /* This IRQ map is fixed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CS8920_NO_INTS 0x0F /* Max CS8920 interrupt select # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define PNP_ADD_PORT 0x0279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define PNP_WRITE_PORT 0x0A79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define GET_PNP_ISA_STRUCT 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define PNP_ISA_STRUCT_LEN 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define PNP_CSN_CNT_OFF 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define PNP_RD_PORT_OFF 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define PNP_FUNCTION_OK 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define PNP_WAKE 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PNP_RSRC_DATA 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PNP_RSRC_READY 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define PNP_STATUS 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define PNP_ACTIVATE 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define PNP_CNF_IO_H 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define PNP_CNF_IO_L 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define PNP_CNF_INT 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define PNP_CNF_DMA 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define PNP_CNF_MEM 0x48
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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