^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Atmel MACB Ethernet Controller driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004-2006 Atmel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _MACB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _MACB_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phylink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/net_tstamp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) || defined(CONFIG_MACB_USE_HWSTAMP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MACB_EXT_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MACB_GREGS_NBR 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MACB_GREGS_VERSION 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MACB_MAX_QUEUES 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* MACB register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MACB_NCR 0x0000 /* Network Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MACB_NCFGR 0x0004 /* Network Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MACB_NSR 0x0008 /* Network Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MACB_TAR 0x000c /* AT91RM9200 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MACB_TCR 0x0010 /* AT91RM9200 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MACB_TSR 0x0014 /* Transmit Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MACB_RBQP 0x0018 /* RX Q Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MACB_TBQP 0x001c /* TX Q Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MACB_RSR 0x0020 /* Receive Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MACB_ISR 0x0024 /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MACB_IER 0x0028 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MACB_IDR 0x002c /* Interrupt Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MACB_IMR 0x0030 /* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MACB_MAN 0x0034 /* PHY Maintenance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MACB_PTR 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MACB_PFR 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MACB_FTO 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MACB_SCF 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MACB_MCF 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MACB_FRO 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MACB_FCSE 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MACB_ALE 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MACB_DTF 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MACB_LCOL 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MACB_EXCOL 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MACB_TUND 0x0064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MACB_CSE 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MACB_RRE 0x006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MACB_ROVR 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MACB_RSE 0x0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MACB_ELE 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MACB_RJA 0x007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MACB_USF 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MACB_STE 0x0084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MACB_RLE 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MACB_TPF 0x008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MACB_HRB 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MACB_HRT 0x0094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MACB_SA1B 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MACB_SA1T 0x009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MACB_SA2B 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MACB_SA2T 0x00a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MACB_SA3B 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MACB_SA3T 0x00ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MACB_SA4B 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MACB_SA4T 0x00b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MACB_TID 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MACB_TPQ 0x00bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MACB_USRIO 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MACB_WOL 0x00c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MACB_MID 0x00fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MACB_TBQPH 0x04C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MACB_RBQPH 0x04D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* GEM register offsets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GEM_NCFGR 0x0004 /* Network Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GEM_USRIO 0x000c /* User IO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GEM_DMACFG 0x0010 /* DMA Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GEM_JML 0x0048 /* Jumbo Max Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GEM_HRB 0x0080 /* Hash Bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GEM_HRT 0x0084 /* Hash Top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GEM_SA1B 0x0088 /* Specific1 Bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GEM_SA1T 0x008C /* Specific1 Top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GEM_SA2B 0x0090 /* Specific2 Bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GEM_SA2T 0x0094 /* Specific2 Top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GEM_SA3B 0x0098 /* Specific3 Bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GEM_SA3T 0x009C /* Specific3 Top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GEM_SA4B 0x00A0 /* Specific4 Bottom */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GEM_SA4T 0x00A4 /* Specific4 Top */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GEM_WOL 0x00b8 /* Wake on LAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GEM_EFTSH 0x00e8 /* PTP Event Frame Transmitted Seconds Register 47:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GEM_EFRSH 0x00ec /* PTP Event Frame Received Seconds Register 47:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GEM_PEFTSH 0x00f0 /* PTP Peer Event Frame Transmitted Seconds Register 47:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GEM_PEFRSH 0x00f4 /* PTP Peer Event Frame Received Seconds Register 47:32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GEM_OTX 0x0100 /* Octets transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GEM_OCTTXL 0x0100 /* Octets transmitted [31:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GEM_OCTTXH 0x0104 /* Octets transmitted [47:32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GEM_TXCNT 0x0108 /* Frames Transmitted counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GEM_TXBCCNT 0x010c /* Broadcast Frames counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GEM_TXMCCNT 0x0110 /* Multicast Frames counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GEM_TXPAUSECNT 0x0114 /* Pause Frames Transmitted Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GEM_TX64CNT 0x0118 /* 64 byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GEM_TX65CNT 0x011c /* 65-127 byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GEM_TX128CNT 0x0120 /* 128-255 byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define GEM_TX256CNT 0x0124 /* 256-511 byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define GEM_TX512CNT 0x0128 /* 512-1023 byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define GEM_TX1024CNT 0x012c /* 1024-1518 byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define GEM_TX1519CNT 0x0130 /* 1519+ byte Frames TX counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define GEM_TXURUNCNT 0x0134 /* TX under run error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GEM_SNGLCOLLCNT 0x0138 /* Single Collision Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define GEM_MULTICOLLCNT 0x013c /* Multiple Collision Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GEM_EXCESSCOLLCNT 0x0140 /* Excessive Collision Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GEM_LATECOLLCNT 0x0144 /* Late Collision Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GEM_TXDEFERCNT 0x0148 /* Deferred Transmission Frame Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GEM_TXCSENSECNT 0x014c /* Carrier Sense Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GEM_ORX 0x0150 /* Octets received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GEM_OCTRXL 0x0150 /* Octets received [31:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GEM_OCTRXH 0x0154 /* Octets received [47:32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GEM_RXCNT 0x0158 /* Frames Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define GEM_RXBROADCNT 0x015c /* Broadcast Frames Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define GEM_RXMULTICNT 0x0160 /* Multicast Frames Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define GEM_RXPAUSECNT 0x0164 /* Pause Frames Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define GEM_RX64CNT 0x0168 /* 64 byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define GEM_RX65CNT 0x016c /* 65-127 byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define GEM_RX128CNT 0x0170 /* 128-255 byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define GEM_RX256CNT 0x0174 /* 256-511 byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define GEM_RX512CNT 0x0178 /* 512-1023 byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define GEM_RX1024CNT 0x017c /* 1024-1518 byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define GEM_RX1519CNT 0x0180 /* 1519+ byte Frames RX Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define GEM_RXUNDRCNT 0x0184 /* Undersize Frames Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define GEM_RXOVRCNT 0x0188 /* Oversize Frames Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define GEM_RXJABCNT 0x018c /* Jabbers Received Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GEM_RXFCSCNT 0x0190 /* Frame Check Sequence Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define GEM_RXLENGTHCNT 0x0194 /* Length Field Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define GEM_RXSYMBCNT 0x0198 /* Symbol Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define GEM_RXALIGNCNT 0x019c /* Alignment Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define GEM_RXRESERRCNT 0x01a0 /* Receive Resource Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define GEM_RXORCNT 0x01a4 /* Receive Overrun Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define GEM_RXIPCCNT 0x01a8 /* IP header Checksum Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define GEM_RXTCPCCNT 0x01ac /* TCP Checksum Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define GEM_RXUDPCCNT 0x01b0 /* UDP Checksum Error Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define GEM_TISUBN 0x01bc /* 1588 Timer Increment Sub-ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define GEM_TSH 0x01c0 /* 1588 Timer Seconds High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define GEM_TSL 0x01d0 /* 1588 Timer Seconds Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define GEM_TN 0x01d4 /* 1588 Timer Nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define GEM_TA 0x01d8 /* 1588 Timer Adjust */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define GEM_TI 0x01dc /* 1588 Timer Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define GEM_EFTSL 0x01e0 /* PTP Event Frame Tx Seconds Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define GEM_EFTN 0x01e4 /* PTP Event Frame Tx Nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define GEM_EFRSL 0x01e8 /* PTP Event Frame Rx Seconds Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define GEM_EFRN 0x01ec /* PTP Event Frame Rx Nanoseconds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define GEM_PEFTSL 0x01f0 /* PTP Peer Event Frame Tx Secs Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define GEM_PEFTN 0x01f4 /* PTP Peer Event Frame Tx Ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define GEM_PEFRSL 0x01f8 /* PTP Peer Event Frame Rx Sec Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define GEM_PEFRN 0x01fc /* PTP Peer Event Frame Rx Ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define GEM_DCFG1 0x0280 /* Design Config 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define GEM_DCFG2 0x0284 /* Design Config 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define GEM_DCFG3 0x0288 /* Design Config 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define GEM_DCFG4 0x028c /* Design Config 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define GEM_DCFG5 0x0290 /* Design Config 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define GEM_DCFG6 0x0294 /* Design Config 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define GEM_DCFG7 0x0298 /* Design Config 7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define GEM_DCFG8 0x029C /* Design Config 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define GEM_DCFG10 0x02A4 /* Design Config 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define GEM_TXBDCTRL 0x04cc /* TX Buffer Descriptor control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define GEM_RXBDCTRL 0x04d0 /* RX Buffer Descriptor control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Screener Type 2 match registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define GEM_SCRT2 0x540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* EtherType registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define GEM_ETHT 0x06E0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Type 2 compare registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define GEM_T2CMPW0 0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define GEM_T2CMPW1 0x0704
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define T2CMP_OFST(t2idx) (t2idx * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* type 2 compare registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * each location requires 3 compare regs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define GEM_IP4SRC_CMP(idx) (idx * 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define GEM_IP4DST_CMP(idx) (idx * 3 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define GEM_PORT_CMP(idx) (idx * 3 + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Which screening type 2 EtherType register will be used (0 - 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SCRT2_ETHT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define GEM_ISR(hw_q) (0x0400 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define GEM_TBQP(hw_q) (0x0440 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define GEM_TBQPH(hw_q) (0x04C8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define GEM_RBQP(hw_q) (0x0480 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define GEM_RBQS(hw_q) (0x04A0 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define GEM_RBQPH(hw_q) (0x04D4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define GEM_IER(hw_q) (0x0600 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define GEM_IDR(hw_q) (0x0620 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define GEM_IMR(hw_q) (0x0640 + ((hw_q) << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Bitfields in NCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MACB_LB_OFFSET 0 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MACB_LB_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MACB_LLB_OFFSET 1 /* Loop back local */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MACB_LLB_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MACB_RE_OFFSET 2 /* Receive enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MACB_RE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MACB_TE_OFFSET 3 /* Transmit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MACB_TE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MACB_MPE_OFFSET 4 /* Management port enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MACB_MPE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MACB_CLRSTAT_OFFSET 5 /* Clear stats regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MACB_CLRSTAT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MACB_INCSTAT_OFFSET 6 /* Incremental stats regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MACB_INCSTAT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MACB_WESTAT_OFFSET 7 /* Write enable stats regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MACB_WESTAT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MACB_BP_OFFSET 8 /* Back pressure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MACB_BP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MACB_TSTART_OFFSET 9 /* Start transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MACB_TSTART_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MACB_THALT_OFFSET 10 /* Transmit halt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MACB_THALT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MACB_NCR_TPF_OFFSET 11 /* Transmit pause frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MACB_NCR_TPF_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MACB_TZQ_OFFSET 12 /* Transmit zero quantum pause frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MACB_TZQ_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MACB_SRTSM_OFFSET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MACB_OSSMODE_OFFSET 24 /* Enable One Step Synchro Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MACB_OSSMODE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* Bitfields in NCFGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MACB_SPD_OFFSET 0 /* Speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MACB_SPD_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MACB_FD_OFFSET 1 /* Full duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MACB_FD_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MACB_BIT_RATE_OFFSET 2 /* Discard non-VLAN frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MACB_BIT_RATE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MACB_JFRAME_OFFSET 3 /* reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MACB_JFRAME_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MACB_CAF_OFFSET 4 /* Copy all frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MACB_CAF_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MACB_NBC_OFFSET 5 /* No broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MACB_NBC_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MACB_NCFGR_MTI_OFFSET 6 /* Multicast hash enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MACB_NCFGR_MTI_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MACB_UNI_OFFSET 7 /* Unicast hash enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MACB_UNI_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MACB_BIG_OFFSET 8 /* Receive 1536 byte frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MACB_BIG_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MACB_EAE_OFFSET 9 /* External address match enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MACB_EAE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MACB_CLK_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MACB_CLK_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MACB_RTY_OFFSET 12 /* Retry test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MACB_RTY_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MACB_PAE_OFFSET 13 /* Pause enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MACB_PAE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MACB_RM9200_RMII_OFFSET 13 /* AT91RM9200 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define MACB_RM9200_RMII_SIZE 1 /* AT91RM9200 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define MACB_RBOF_OFFSET 14 /* Receive buffer offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define MACB_RBOF_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MACB_RLCE_OFFSET 16 /* Length field error frame discard */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MACB_RLCE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define MACB_DRFCS_OFFSET 17 /* FCS remove */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MACB_DRFCS_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MACB_EFRHD_OFFSET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define MACB_EFRHD_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MACB_IRXFCS_OFFSET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MACB_IRXFCS_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* GEM specific NCFGR bitfields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define GEM_GBE_OFFSET 10 /* Gigabit mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define GEM_GBE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define GEM_PCSSEL_OFFSET 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define GEM_PCSSEL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define GEM_CLK_OFFSET 18 /* MDC clock division */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define GEM_CLK_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define GEM_DBW_OFFSET 21 /* Data bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define GEM_DBW_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define GEM_RXCOEN_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define GEM_RXCOEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define GEM_SGMIIEN_OFFSET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define GEM_SGMIIEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* Constants for data bus width. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define GEM_DBW128 2 /* 128 bit AMBA AHB data bus width */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Bitfields in DMACFG. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define GEM_FBLDO_OFFSET 0 /* fixed burst length for DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define GEM_FBLDO_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define GEM_ENDIA_DESC_OFFSET 6 /* endian swap mode for management descriptor access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define GEM_ENDIA_DESC_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define GEM_ENDIA_PKT_OFFSET 7 /* endian swap mode for packet data access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define GEM_ENDIA_PKT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GEM_RXBMS_OFFSET 8 /* RX packet buffer memory size select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define GEM_RXBMS_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define GEM_TXPBMS_OFFSET 10 /* TX packet buffer memory size select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define GEM_TXPBMS_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define GEM_TXCOEN_OFFSET 11 /* TX IP/TCP/UDP checksum gen offload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define GEM_TXCOEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define GEM_RXBS_OFFSET 16 /* DMA receive buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define GEM_RXBS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define GEM_DDRP_OFFSET 24 /* disc_when_no_ahb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define GEM_DDRP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define GEM_RXEXT_OFFSET 28 /* RX extended Buffer Descriptor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define GEM_RXEXT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define GEM_TXEXT_OFFSET 29 /* TX extended Buffer Descriptor mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define GEM_TXEXT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define GEM_ADDR64_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Bitfields in NSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MACB_NSR_LINK_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MACB_MDIO_OFFSET 1 /* status of the mdio_in pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MACB_MDIO_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define MACB_IDLE_OFFSET 2 /* The PHY management logic is idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define MACB_IDLE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Bitfields in TSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MACB_UBR_OFFSET 0 /* Used bit read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MACB_UBR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MACB_COL_OFFSET 1 /* Collision occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MACB_COL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MACB_TSR_RLE_OFFSET 2 /* Retry limit exceeded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MACB_TSR_RLE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MACB_TGO_OFFSET 3 /* Transmit go */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define MACB_TGO_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define MACB_BEX_OFFSET 4 /* TX frame corruption due to AHB error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define MACB_BEX_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define MACB_RM9200_BNQ_OFFSET 4 /* AT91RM9200 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define MACB_RM9200_BNQ_SIZE 1 /* AT91RM9200 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define MACB_COMP_OFFSET 5 /* Trnasmit complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define MACB_COMP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MACB_UND_OFFSET 6 /* Trnasmit under run */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MACB_UND_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Bitfields in RSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MACB_BNA_OFFSET 0 /* Buffer not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MACB_BNA_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MACB_REC_OFFSET 1 /* Frame received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MACB_REC_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define MACB_OVR_OFFSET 2 /* Receive overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define MACB_OVR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* Bitfields in ISR/IER/IDR/IMR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define MACB_MFD_OFFSET 0 /* Management frame sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define MACB_MFD_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define MACB_RCOMP_OFFSET 1 /* Receive complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define MACB_RCOMP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MACB_RXUBR_OFFSET 2 /* RX used bit read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MACB_RXUBR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MACB_TXUBR_OFFSET 3 /* TX used bit read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MACB_TXUBR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MACB_ISR_TUND_OFFSET 4 /* Enable TX buffer under run interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MACB_ISR_TUND_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MACB_ISR_RLE_OFFSET 5 /* EN retry exceeded/late coll interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MACB_ISR_RLE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MACB_TXERR_OFFSET 6 /* EN TX frame corrupt from error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MACB_TXERR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MACB_RM9200_TBRE_OFFSET 6 /* EN may send new frame interrupt (RM9200) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MACB_RM9200_TBRE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define MACB_TCOMP_OFFSET 7 /* Enable transmit complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define MACB_TCOMP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define MACB_ISR_LINK_OFFSET 9 /* Enable link change interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define MACB_ISR_LINK_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define MACB_ISR_ROVR_OFFSET 10 /* Enable receive overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define MACB_ISR_ROVR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define MACB_HRESP_OFFSET 11 /* Enable hrsep not OK interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define MACB_HRESP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define MACB_PFR_OFFSET 12 /* Enable pause frame w/ quantum interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define MACB_PFR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define MACB_PTZ_OFFSET 13 /* Enable pause time zero interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define MACB_PTZ_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define MACB_WOL_OFFSET 14 /* Enable wake-on-lan interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define MACB_WOL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MACB_DRQFR_OFFSET 18 /* PTP Delay Request Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define MACB_DRQFR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MACB_SFR_OFFSET 19 /* PTP Sync Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MACB_SFR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MACB_DRQFT_OFFSET 20 /* PTP Delay Request Frame Transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MACB_DRQFT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MACB_SFT_OFFSET 21 /* PTP Sync Frame Transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define MACB_SFT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MACB_PDRQFR_OFFSET 22 /* PDelay Request Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define MACB_PDRQFR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define MACB_PDRSFR_OFFSET 23 /* PDelay Response Frame Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define MACB_PDRSFR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MACB_PDRQFT_OFFSET 24 /* PDelay Request Frame Transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define MACB_PDRQFT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define MACB_PDRSFT_OFFSET 25 /* PDelay Response Frame Transmitted */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define MACB_PDRSFT_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define MACB_SRI_OFFSET 26 /* TSU Seconds Register Increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define MACB_SRI_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define GEM_WOL_OFFSET 28 /* Enable wake-on-lan interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define GEM_WOL_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* Timer increment fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define MACB_TI_CNS_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define MACB_TI_CNS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define MACB_TI_ACNS_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define MACB_TI_ACNS_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define MACB_TI_NIT_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define MACB_TI_NIT_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Bitfields in MAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MACB_DATA_OFFSET 0 /* data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define MACB_DATA_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define MACB_CODE_OFFSET 16 /* Must be written to 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define MACB_CODE_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define MACB_REGA_OFFSET 18 /* Register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define MACB_REGA_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define MACB_PHYA_OFFSET 23 /* PHY address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MACB_PHYA_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define MACB_RW_OFFSET 28 /* Operation. 10 is read. 01 is write. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define MACB_RW_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define MACB_SOF_OFFSET 30 /* Must be written to 1 for Clause 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define MACB_SOF_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* Bitfields in USRIO (AVR32) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define MACB_MII_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define MACB_MII_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define MACB_EAM_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define MACB_EAM_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define MACB_TX_PAUSE_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define MACB_TX_PAUSE_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define MACB_TX_PAUSE_ZERO_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define MACB_TX_PAUSE_ZERO_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Bitfields in USRIO (AT91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MACB_RMII_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MACB_RMII_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define GEM_RGMII_OFFSET 0 /* GEM gigabit mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define GEM_RGMII_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MACB_CLKEN_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MACB_CLKEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) /* Bitfields in WOL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MACB_IP_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define MACB_IP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MACB_MAG_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define MACB_MAG_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define MACB_ARP_OFFSET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MACB_ARP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define MACB_SA1_OFFSET 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define MACB_SA1_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define MACB_WOL_MTI_OFFSET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MACB_WOL_MTI_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Bitfields in MID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define MACB_IDNUM_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MACB_IDNUM_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define MACB_REV_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MACB_REV_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Bitfields in DCFG1. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define GEM_IRQCOR_OFFSET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define GEM_IRQCOR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define GEM_DBWDEF_OFFSET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define GEM_DBWDEF_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Bitfields in DCFG2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define GEM_RX_PKT_BUFF_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define GEM_RX_PKT_BUFF_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define GEM_TX_PKT_BUFF_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define GEM_TX_PKT_BUFF_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Bitfields in DCFG5. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define GEM_TSU_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define GEM_TSU_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Bitfields in DCFG6. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define GEM_PBUF_LSO_OFFSET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define GEM_PBUF_LSO_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define GEM_DAW64_OFFSET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define GEM_DAW64_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* Bitfields in DCFG8. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define GEM_T1SCR_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define GEM_T1SCR_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define GEM_T2SCR_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define GEM_T2SCR_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define GEM_SCR2ETH_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define GEM_SCR2ETH_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define GEM_SCR2CMP_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define GEM_SCR2CMP_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /* Bitfields in DCFG10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define GEM_TXBD_RDBUFF_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define GEM_TXBD_RDBUFF_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define GEM_RXBD_RDBUFF_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define GEM_RXBD_RDBUFF_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Bitfields in TISUBN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define GEM_SUBNSINCR_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define GEM_SUBNSINCRL_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define GEM_SUBNSINCRL_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define GEM_SUBNSINCRH_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define GEM_SUBNSINCRH_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define GEM_SUBNSINCR_SIZE 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Bitfields in TI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define GEM_NSINCR_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define GEM_NSINCR_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Bitfields in TSH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define GEM_TSH_OFFSET 0 /* TSU timer value (s). MSB [47:32] of seconds timer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define GEM_TSH_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /* Bitfields in TSL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define GEM_TSL_OFFSET 0 /* TSU timer value (s). LSB [31:0] of seconds timer count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define GEM_TSL_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Bitfields in TN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define GEM_TN_OFFSET 0 /* TSU timer value (ns) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define GEM_TN_SIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* Bitfields in TXBDCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define GEM_TXTSMODE_OFFSET 4 /* TX Descriptor Timestamp Insertion mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define GEM_TXTSMODE_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* Bitfields in RXBDCTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define GEM_RXTSMODE_OFFSET 4 /* RX Descriptor Timestamp Insertion mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define GEM_RXTSMODE_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Bitfields in SCRT2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define GEM_QUEUE_OFFSET 0 /* Queue Number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define GEM_QUEUE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define GEM_VLANPR_OFFSET 4 /* VLAN Priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define GEM_VLANPR_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define GEM_VLANEN_OFFSET 8 /* VLAN Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define GEM_VLANEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define GEM_ETHT2IDX_OFFSET 9 /* Index to screener type 2 EtherType register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define GEM_ETHT2IDX_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define GEM_ETHTEN_OFFSET 12 /* EtherType Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define GEM_ETHTEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define GEM_CMPA_OFFSET 13 /* Compare A - Index to screener type 2 Compare register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define GEM_CMPA_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define GEM_CMPAEN_OFFSET 18 /* Compare A Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define GEM_CMPAEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define GEM_CMPB_OFFSET 19 /* Compare B - Index to screener type 2 Compare register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define GEM_CMPB_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define GEM_CMPBEN_OFFSET 24 /* Compare B Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define GEM_CMPBEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define GEM_CMPC_OFFSET 25 /* Compare C - Index to screener type 2 Compare register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define GEM_CMPC_SIZE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define GEM_CMPCEN_OFFSET 30 /* Compare C Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define GEM_CMPCEN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Bitfields in ETHT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define GEM_ETHTCMP_OFFSET 0 /* EtherType compare value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define GEM_ETHTCMP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Bitfields in T2CMPW0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define GEM_T2CMP_OFFSET 16 /* 0xFFFF0000 compare value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define GEM_T2CMP_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define GEM_T2MASK_OFFSET 0 /* 0x0000FFFF compare value or mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define GEM_T2MASK_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Bitfields in T2CMPW1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define GEM_T2DISMSK_OFFSET 9 /* disable mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define GEM_T2DISMSK_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define GEM_T2CMPOFST_OFFSET 7 /* compare offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define GEM_T2CMPOFST_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define GEM_T2OFST_OFFSET 0 /* offset value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define GEM_T2OFST_SIZE 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Offset for screener type 2 compare values (T2CMPOFST).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * Note the offset is applied after the specified point,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * e.g. GEM_T2COMPOFST_ETYPE denotes the EtherType field, so an offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * of 12 bytes from this would be the source IP address in an IP header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define GEM_T2COMPOFST_SOF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define GEM_T2COMPOFST_ETYPE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define GEM_T2COMPOFST_IPHDR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define GEM_T2COMPOFST_TCPUDP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* offset from EtherType to IP address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define ETYPE_SRCIP_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define ETYPE_DSTIP_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* offset from IP header to port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define IPHDR_SRCPORT_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define IPHDR_DSTPORT_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Transmit DMA buffer descriptor Word 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define GEM_DMA_TXVALID_OFFSET 23 /* timestamp has been captured in the Buffer Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define GEM_DMA_TXVALID_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /* Receive DMA buffer descriptor Word 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define GEM_DMA_RXVALID_OFFSET 2 /* indicates a valid timestamp in the Buffer Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define GEM_DMA_RXVALID_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* DMA buffer descriptor Word 2 (32 bit addressing) or Word 4 (64 bit addressing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define GEM_DMA_SECL_OFFSET 30 /* Timestamp seconds[1:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define GEM_DMA_SECL_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define GEM_DMA_NSEC_OFFSET 0 /* Timestamp nanosecs [29:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define GEM_DMA_NSEC_SIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* DMA buffer descriptor Word 3 (32 bit addressing) or Word 5 (64 bit addressing) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* New hardware supports 12 bit precision of timestamp in DMA buffer descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * Old hardware supports only 6 bit precision but it is enough for PTP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * Less accuracy is used always instead of checking hardware version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define GEM_DMA_SECH_OFFSET 0 /* Timestamp seconds[5:2] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define GEM_DMA_SECH_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define GEM_DMA_SEC_WIDTH (GEM_DMA_SECH_SIZE + GEM_DMA_SECL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define GEM_DMA_SEC_TOP (1 << GEM_DMA_SEC_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define GEM_DMA_SEC_MASK (GEM_DMA_SEC_TOP - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* Bitfields in ADJ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define GEM_ADDSUB_OFFSET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define GEM_ADDSUB_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Constants for CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define MACB_CLK_DIV8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define MACB_CLK_DIV16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define MACB_CLK_DIV32 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define MACB_CLK_DIV64 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* GEM specific constants for CLK. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define GEM_CLK_DIV8 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define GEM_CLK_DIV16 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define GEM_CLK_DIV32 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define GEM_CLK_DIV48 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define GEM_CLK_DIV64 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define GEM_CLK_DIV96 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Constants for MAN register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define MACB_MAN_C22_SOF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define MACB_MAN_C22_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define MACB_MAN_C22_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define MACB_MAN_C22_CODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define MACB_MAN_C45_SOF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define MACB_MAN_C45_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define MACB_MAN_C45_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define MACB_MAN_C45_POST_READ_INCR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define MACB_MAN_C45_READ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define MACB_MAN_C45_CODE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /* Capability mask bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define MACB_CAPS_ISR_CLEAR_ON_WRITE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define MACB_CAPS_USRIO_HAS_CLKEN 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define MACB_CAPS_NO_GIGABIT_HALF 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define MACB_CAPS_USRIO_DISABLED 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define MACB_CAPS_JUMBO 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define MACB_CAPS_GEM_HAS_PTP 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define MACB_CAPS_BD_RD_PREFETCH 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define MACB_CAPS_NEEDS_RSTONUBR 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define MACB_CAPS_MACB_IS_EMAC 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define MACB_CAPS_FIFO_MODE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define MACB_CAPS_GIGABIT_MODE_AVAILABLE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define MACB_CAPS_SG_DISABLED 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define MACB_CAPS_MACB_IS_GEM 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /* LSO settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define MACB_LSO_UFO_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #define MACB_LSO_TSO_ENABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /* Bit manipulation macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define MACB_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) (1 << MACB_##name##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define MACB_BF(name,value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) (((value) & ((1 << MACB_##name##_SIZE) - 1)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) << MACB_##name##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define MACB_BFEXT(name,value)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) (((value) >> MACB_##name##_OFFSET) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) & ((1 << MACB_##name##_SIZE) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define MACB_BFINS(name,value,old) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) (((old) & ~(((1 << MACB_##name##_SIZE) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) << MACB_##name##_OFFSET)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) | MACB_BF(name,value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) #define GEM_BIT(name) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) (1 << GEM_##name##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define GEM_BF(name, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) (((value) & ((1 << GEM_##name##_SIZE) - 1)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) << GEM_##name##_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define GEM_BFEXT(name, value)\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) (((value) >> GEM_##name##_OFFSET) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) & ((1 << GEM_##name##_SIZE) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) #define GEM_BFINS(name, value, old) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) (((old) & ~(((1 << GEM_##name##_SIZE) - 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) << GEM_##name##_OFFSET)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) | GEM_BF(name, value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Register access macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define macb_readl(port, reg) (port)->macb_reg_readl((port), MACB_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define macb_writel(port, reg, value) (port)->macb_reg_writel((port), MACB_##reg, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define gem_readl(port, reg) (port)->macb_reg_readl((port), GEM_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define gem_writel(port, reg, value) (port)->macb_reg_writel((port), GEM_##reg, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define queue_readl(queue, reg) (queue)->bp->macb_reg_readl((queue)->bp, (queue)->reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define queue_writel(queue, reg, value) (queue)->bp->macb_reg_writel((queue)->bp, (queue)->reg, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #define gem_readl_n(port, reg, idx) (port)->macb_reg_readl((port), GEM_##reg + idx * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define gem_writel_n(port, reg, idx, value) (port)->macb_reg_writel((port), GEM_##reg + idx * 4, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define PTP_TS_BUFFER_SIZE 128 /* must be power of 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Conditional GEM/MACB macros. These perform the operation to the correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * register dependent on whether the device is a GEM or a MACB. For registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * and bitfields that are common across both devices, use macb_{read,write}l
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * to avoid the cost of the conditional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define macb_or_gem_writel(__bp, __reg, __value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (macb_is_gem((__bp))) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) gem_writel((__bp), __reg, __value); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) macb_writel((__bp), __reg, __value); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define macb_or_gem_readl(__bp, __reg) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) u32 __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) if (macb_is_gem((__bp))) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) __v = gem_readl((__bp), __reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) else \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) __v = macb_readl((__bp), __reg); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __v; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) #define MACB_READ_NSR(bp) macb_readl(bp, NSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* struct macb_dma_desc - Hardware DMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * @addr: DMA address of data buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * @ctrl: Control and status bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct macb_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) #ifdef MACB_EXT_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define HW_DMA_CAP_32B 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define HW_DMA_CAP_64B (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) #define HW_DMA_CAP_PTP (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define HW_DMA_CAP_64B_PTP (HW_DMA_CAP_64B | HW_DMA_CAP_PTP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) struct macb_dma_desc_64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u32 addrh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 resvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct macb_dma_desc_ptp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 ts_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) u32 ts_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct gem_tx_ts {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) struct macb_dma_desc_ptp desc_ptp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) /* DMA descriptor bitfields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define MACB_RX_USED_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define MACB_RX_USED_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define MACB_RX_WRAP_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define MACB_RX_WRAP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define MACB_RX_WADDR_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define MACB_RX_WADDR_SIZE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define MACB_RX_FRMLEN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #define MACB_RX_FRMLEN_SIZE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define MACB_RX_OFFSET_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define MACB_RX_OFFSET_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define MACB_RX_SOF_OFFSET 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define MACB_RX_SOF_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define MACB_RX_EOF_OFFSET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define MACB_RX_EOF_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define MACB_RX_CFI_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define MACB_RX_CFI_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define MACB_RX_VLAN_PRI_OFFSET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define MACB_RX_VLAN_PRI_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MACB_RX_PRI_TAG_OFFSET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define MACB_RX_PRI_TAG_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define MACB_RX_VLAN_TAG_OFFSET 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define MACB_RX_VLAN_TAG_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define MACB_RX_TYPEID_MATCH_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define MACB_RX_TYPEID_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define MACB_RX_SA4_MATCH_OFFSET 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define MACB_RX_SA4_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define MACB_RX_SA3_MATCH_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define MACB_RX_SA3_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define MACB_RX_SA2_MATCH_OFFSET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define MACB_RX_SA2_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define MACB_RX_SA1_MATCH_OFFSET 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define MACB_RX_SA1_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define MACB_RX_EXT_MATCH_OFFSET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define MACB_RX_EXT_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define MACB_RX_UHASH_MATCH_OFFSET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define MACB_RX_UHASH_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define MACB_RX_MHASH_MATCH_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define MACB_RX_MHASH_MATCH_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define MACB_RX_BROADCAST_OFFSET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define MACB_RX_BROADCAST_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define MACB_RX_FRMLEN_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define MACB_RX_JFRMLEN_MASK 0x3FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) /* RX checksum offload disabled: bit 24 clear in NCFGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define GEM_RX_TYPEID_MATCH_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define GEM_RX_TYPEID_MATCH_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) /* RX checksum offload enabled: bit 24 set in NCFGR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define GEM_RX_CSUM_OFFSET 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) #define GEM_RX_CSUM_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define MACB_TX_FRMLEN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define MACB_TX_FRMLEN_SIZE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define MACB_TX_LAST_OFFSET 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define MACB_TX_LAST_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define MACB_TX_NOCRC_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define MACB_TX_NOCRC_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define MACB_MSS_MFS_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) #define MACB_MSS_MFS_SIZE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define MACB_TX_LSO_OFFSET 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define MACB_TX_LSO_SIZE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define MACB_TX_TCP_SEQ_SRC_OFFSET 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define MACB_TX_TCP_SEQ_SRC_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define MACB_TX_BUF_EXHAUSTED_OFFSET 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define MACB_TX_BUF_EXHAUSTED_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define MACB_TX_UNDERRUN_OFFSET 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define MACB_TX_UNDERRUN_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define MACB_TX_ERROR_OFFSET 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define MACB_TX_ERROR_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define MACB_TX_WRAP_OFFSET 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define MACB_TX_WRAP_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define MACB_TX_USED_OFFSET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define MACB_TX_USED_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define GEM_TX_FRMLEN_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define GEM_TX_FRMLEN_SIZE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /* Buffer descriptor constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define GEM_RX_CSUM_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define GEM_RX_CSUM_IP_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define GEM_RX_CSUM_IP_TCP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define GEM_RX_CSUM_IP_UDP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /* limit RX checksum offload to TCP and UDP packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define GEM_RX_CSUM_CHECKED_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) /* Scaled PPM fraction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define PPM_FRACTION 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /* struct macb_tx_skb - data about an skb which is being transmitted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) * @skb: skb currently being transmitted, only set for the last buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) * of the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) * @mapping: DMA address of the skb's fragment buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) * @size: size of the DMA mapped buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) * @mapped_as_page: true when buffer was mapped with skb_frag_dma_map(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) * false when buffer was mapped with dma_map_single()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct macb_tx_skb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) bool mapped_as_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* Hardware-collected statistics. Used when updating the network
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * device stats by a periodic timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct macb_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u32 rx_pause_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) u32 tx_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 tx_single_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u32 tx_multiple_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 rx_ok;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) u32 rx_fcs_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 rx_align_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) u32 tx_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) u32 tx_late_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) u32 tx_excessive_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) u32 tx_underruns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) u32 tx_carrier_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 rx_resource_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) u32 rx_overruns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 rx_symbol_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) u32 rx_oversize_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) u32 rx_jabbers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) u32 rx_undersize_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) u32 sqe_test_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) u32 rx_length_mismatch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) u32 tx_pause_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct gem_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) u32 tx_octets_31_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) u32 tx_octets_47_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) u32 tx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) u32 tx_broadcast_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u32 tx_multicast_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) u32 tx_pause_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) u32 tx_64_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u32 tx_65_127_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) u32 tx_128_255_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) u32 tx_256_511_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 tx_512_1023_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) u32 tx_1024_1518_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 tx_greater_than_1518_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) u32 tx_underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) u32 tx_single_collision_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u32 tx_multiple_collision_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) u32 tx_excessive_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) u32 tx_late_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) u32 tx_deferred_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) u32 tx_carrier_sense_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) u32 rx_octets_31_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) u32 rx_octets_47_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) u32 rx_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u32 rx_broadcast_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) u32 rx_multicast_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) u32 rx_pause_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) u32 rx_64_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) u32 rx_65_127_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) u32 rx_128_255_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) u32 rx_256_511_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) u32 rx_512_1023_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) u32 rx_1024_1518_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) u32 rx_greater_than_1518_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) u32 rx_undersized_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) u32 rx_oversize_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) u32 rx_jabbers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) u32 rx_frame_check_sequence_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) u32 rx_length_field_frame_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 rx_symbol_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) u32 rx_alignment_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u32 rx_resource_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) u32 rx_overruns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u32 rx_ip_header_checksum_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u32 rx_tcp_checksum_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) u32 rx_udp_checksum_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) /* Describes the name and offset of an individual statistic register, as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) * returned by `ethtool -S`. Also describes which net_device_stats statistics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) * this register should contribute to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct gem_statistic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) char stat_string[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 stat_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Bitfield defs for net_device_stat statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define GEM_NDS_RXERR_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define GEM_NDS_RXLENERR_OFFSET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #define GEM_NDS_RXOVERERR_OFFSET 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define GEM_NDS_RXCRCERR_OFFSET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define GEM_NDS_RXFRAMEERR_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define GEM_NDS_RXFIFOERR_OFFSET 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define GEM_NDS_TXERR_OFFSET 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define GEM_NDS_TXABORTEDERR_OFFSET 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) #define GEM_NDS_TXCARRIERERR_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define GEM_NDS_TXFIFOERR_OFFSET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define GEM_NDS_COLLISIONS_OFFSET 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define GEM_STAT_TITLE(name, title) GEM_STAT_TITLE_BITS(name, title, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define GEM_STAT_TITLE_BITS(name, title, bits) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) .stat_string = title, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) .offset = GEM_##name, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .stat_bits = bits \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* list of gem statistic registers. The names MUST match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * corresponding GEM_* definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) static const struct gem_statistic gem_statistics[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) GEM_STAT_TITLE(OCTTXL, "tx_octets"), /* OCTTXH combined with OCTTXL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) GEM_STAT_TITLE(TXCNT, "tx_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) GEM_STAT_TITLE(TXBCCNT, "tx_broadcast_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) GEM_STAT_TITLE(TXMCCNT, "tx_multicast_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) GEM_STAT_TITLE(TXPAUSECNT, "tx_pause_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) GEM_STAT_TITLE(TX64CNT, "tx_64_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) GEM_STAT_TITLE(TX65CNT, "tx_65_127_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) GEM_STAT_TITLE(TX128CNT, "tx_128_255_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) GEM_STAT_TITLE(TX256CNT, "tx_256_511_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) GEM_STAT_TITLE(TX512CNT, "tx_512_1023_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) GEM_STAT_TITLE(TX1024CNT, "tx_1024_1518_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) GEM_STAT_TITLE(TX1519CNT, "tx_greater_than_1518_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) GEM_STAT_TITLE_BITS(TXURUNCNT, "tx_underrun",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_TXFIFOERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) GEM_STAT_TITLE_BITS(SNGLCOLLCNT, "tx_single_collision_frames",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) GEM_STAT_TITLE_BITS(MULTICOLLCNT, "tx_multiple_collision_frames",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) GEM_STAT_TITLE_BITS(EXCESSCOLLCNT, "tx_excessive_collisions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) GEM_BIT(NDS_TXERR)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) GEM_BIT(NDS_TXABORTEDERR)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) GEM_BIT(NDS_COLLISIONS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) GEM_STAT_TITLE_BITS(LATECOLLCNT, "tx_late_collisions",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) GEM_STAT_TITLE(TXDEFERCNT, "tx_deferred_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) GEM_STAT_TITLE_BITS(TXCSENSECNT, "tx_carrier_sense_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) GEM_BIT(NDS_TXERR)|GEM_BIT(NDS_COLLISIONS)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) GEM_STAT_TITLE(OCTRXL, "rx_octets"), /* OCTRXH combined with OCTRXL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) GEM_STAT_TITLE(RXCNT, "rx_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) GEM_STAT_TITLE(RXBROADCNT, "rx_broadcast_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) GEM_STAT_TITLE(RXMULTICNT, "rx_multicast_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) GEM_STAT_TITLE(RXPAUSECNT, "rx_pause_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) GEM_STAT_TITLE(RX64CNT, "rx_64_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) GEM_STAT_TITLE(RX65CNT, "rx_65_127_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) GEM_STAT_TITLE(RX128CNT, "rx_128_255_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) GEM_STAT_TITLE(RX256CNT, "rx_256_511_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) GEM_STAT_TITLE(RX512CNT, "rx_512_1023_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) GEM_STAT_TITLE(RX1024CNT, "rx_1024_1518_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) GEM_STAT_TITLE(RX1519CNT, "rx_greater_than_1518_byte_frames"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) GEM_STAT_TITLE_BITS(RXUNDRCNT, "rx_undersized_frames",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) GEM_STAT_TITLE_BITS(RXOVRCNT, "rx_oversize_frames",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) GEM_STAT_TITLE_BITS(RXJABCNT, "rx_jabbers",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXLENERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) GEM_STAT_TITLE_BITS(RXFCSCNT, "rx_frame_check_sequence_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXCRCERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) GEM_STAT_TITLE_BITS(RXLENGTHCNT, "rx_length_field_frame_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) GEM_BIT(NDS_RXERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) GEM_STAT_TITLE_BITS(RXSYMBCNT, "rx_symbol_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFRAMEERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) GEM_STAT_TITLE_BITS(RXALIGNCNT, "rx_alignment_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) GEM_STAT_TITLE_BITS(RXRESERRCNT, "rx_resource_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXOVERERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) GEM_STAT_TITLE_BITS(RXORCNT, "rx_overruns",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) GEM_BIT(NDS_RXERR)|GEM_BIT(NDS_RXFIFOERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) GEM_STAT_TITLE_BITS(RXIPCCNT, "rx_ip_header_checksum_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) GEM_BIT(NDS_RXERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) GEM_STAT_TITLE_BITS(RXTCPCCNT, "rx_tcp_checksum_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) GEM_BIT(NDS_RXERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) GEM_STAT_TITLE_BITS(RXUDPCCNT, "rx_udp_checksum_errors",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) GEM_BIT(NDS_RXERR)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #define GEM_STATS_LEN ARRAY_SIZE(gem_statistics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define QUEUE_STAT_TITLE(title) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .stat_string = title, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* per queue statistics, each should be unsigned long type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) struct queue_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) unsigned long first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) unsigned long rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) unsigned long rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) unsigned long rx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned long tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) unsigned long tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) unsigned long tx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static const struct gem_statistic queue_statistics[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) QUEUE_STAT_TITLE("rx_packets"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) QUEUE_STAT_TITLE("rx_bytes"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) QUEUE_STAT_TITLE("rx_dropped"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) QUEUE_STAT_TITLE("tx_packets"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) QUEUE_STAT_TITLE("tx_bytes"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) QUEUE_STAT_TITLE("tx_dropped"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define QUEUE_STATS_LEN ARRAY_SIZE(queue_statistics)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) struct macb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) struct macb_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct macb_or_gem_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) int (*mog_alloc_rx_buffers)(struct macb *bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) void (*mog_free_rx_buffers)(struct macb *bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) void (*mog_init_rings)(struct macb *bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) int (*mog_rx)(struct macb_queue *queue, struct napi_struct *napi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) int budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) /* MACB-PTP interface: adapt to platform needs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct macb_ptp_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) void (*ptp_init)(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) void (*ptp_remove)(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) s32 (*get_ptp_max_adj)(void);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) unsigned int (*get_tsu_rate)(struct macb *bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int (*get_ts_info)(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct ethtool_ts_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) int (*get_hwtst)(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct ifreq *ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int (*set_hwtst)(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) struct ifreq *ifr, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct macb_pm_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) u32 scrt2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) u32 usrio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct macb_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) unsigned int dma_burst_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) int (*clk_init)(struct platform_device *pdev, struct clk **pclk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) struct clk **hclk, struct clk **tx_clk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) struct clk **rx_clk, struct clk **tsu_clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) int (*init)(struct platform_device *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) int jumbo_max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct tsu_incr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u32 sub_ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u32 ns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) struct macb_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) struct macb *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) unsigned int ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) unsigned int IER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) unsigned int IDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) unsigned int IMR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) unsigned int TBQP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) unsigned int TBQPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) unsigned int RBQS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) unsigned int RBQP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) unsigned int RBQPH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) unsigned int tx_head, tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) struct macb_dma_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) struct macb_tx_skb *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct work_struct tx_error_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dma_addr_t rx_buffers_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned int rx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) unsigned int rx_prepared_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) struct macb_dma_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct sk_buff **rx_skbuff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) void *rx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct queue_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #ifdef CONFIG_MACB_USE_HWSTAMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct work_struct tx_ts_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) unsigned int tx_ts_head, tx_ts_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct gem_tx_ts tx_timestamps[PTP_TS_BUFFER_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) struct ethtool_rx_fs_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) struct ethtool_rx_flow_spec fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) struct ethtool_rx_fs_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct macb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) bool native_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* hardware IO accessors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) u32 (*macb_reg_readl)(struct macb *bp, int offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) void (*macb_reg_writel)(struct macb *bp, int offset, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) size_t rx_buffer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) unsigned int rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) unsigned int tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) unsigned int num_queues;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) unsigned int queue_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct macb_queue queues[MACB_MAX_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) struct clk *tx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) struct clk *rx_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) struct clk *tsu_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct macb_stats macb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) struct gem_stats gem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) struct macb_or_gem_ops macbgem_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct phylink *phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct phylink_config phylink_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) u32 caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) unsigned int dma_burst_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) phy_interface_t phy_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* AT91RM9200 transmit queue (1 on wire + 1 queued) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) struct macb_tx_skb rm9200_txq[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) unsigned int rm9200_tx_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) unsigned int rm9200_tx_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) unsigned int max_tx_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u64 ethtool_stats[GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) unsigned int rx_frm_len_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) unsigned int jumbo_max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) u32 wol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct macb_ptp_info *ptp_info; /* macb-ptp interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #ifdef MACB_EXT_DESC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) uint8_t hw_dma_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) spinlock_t tsu_clk_lock; /* gem tsu clock locking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) unsigned int tsu_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct ptp_clock_info ptp_clock_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) struct tsu_incr tsu_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) struct hwtstamp_config tstamp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* RX queue filer rule set*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct ethtool_rx_fs_list rx_fs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) spinlock_t rx_fs_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) unsigned int max_tuples;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct tasklet_struct hresp_err_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int rx_bd_rd_prefetch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int tx_bd_rd_prefetch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u32 rx_intr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct macb_pm_data pm_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #ifdef CONFIG_MACB_USE_HWSTAMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define GEM_TSEC_SIZE (GEM_TSH_SIZE + GEM_TSL_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define TSU_SEC_MAX_VAL (((u64)1 << GEM_TSEC_SIZE) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define TSU_NSEC_MAX_VAL ((1 << GEM_TN_SIZE) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) enum macb_bd_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) TSTAMP_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) TSTAMP_FRAME_PTP_EVENT_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) TSTAMP_ALL_PTP_FRAMES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) TSTAMP_ALL_FRAMES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) void gem_ptp_init(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) void gem_ptp_remove(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) int gem_ptp_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) void gem_ptp_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) if (queue->bp->tstamp_config.tx_type == TSTAMP_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) return gem_ptp_txstamp(queue, skb, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) if (bp->tstamp_config.rx_filter == TSTAMP_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) gem_ptp_rxstamp(bp, skb, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) int gem_get_hwtst(struct net_device *dev, struct ifreq *rq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) int gem_set_hwtst(struct net_device *dev, struct ifreq *ifr, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) static inline void gem_ptp_init(struct net_device *ndev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) static inline void gem_ptp_remove(struct net_device *ndev) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) static inline int gem_ptp_do_txstamp(struct macb_queue *queue, struct sk_buff *skb, struct macb_dma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) static inline void gem_ptp_do_rxstamp(struct macb *bp, struct sk_buff *skb, struct macb_dma_desc *desc) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static inline bool macb_is_gem(struct macb *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return !!(bp->caps & MACB_CAPS_MACB_IS_GEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static inline bool gem_has_ptp(struct macb *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) return !!(bp->caps & MACB_CAPS_GEM_HAS_PTP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * struct macb_platform_data - platform data for MACB Ethernet used for PCI registration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * @pclk: platform clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * @hclk: AHB clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct macb_platform_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) struct clk *pclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct clk *hclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #endif /* _MACB_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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