^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* cnic.h: QLogic CNIC core network driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2006-2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef CNIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CNIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define HC_INDEX_ISCSI_EQ_CONS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HC_INDEX_FCOE_EQ_CONS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define KWQ_PAGE_CNT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define KCQ_PAGE_CNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define KWQ_CID 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define KCQ_CID 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * krnlq_context definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define L5_KRNLQ_FLAGS 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define L5_KRNLQ_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define L5_KRNLQ_TYPE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define KRNLQ_FLAGS_PG_SZ (0xf<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define KRNLQ_FLAGS_PG_SZ_256 (0<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define KRNLQ_FLAGS_PG_SZ_512 (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define KRNLQ_FLAGS_PG_SZ_1K (2<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define KRNLQ_FLAGS_PG_SZ_2K (3<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define KRNLQ_FLAGS_PG_SZ_4K (4<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define KRNLQ_FLAGS_PG_SZ_8K (5<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define KRNLQ_FLAGS_PG_SZ_16K (6<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define KRNLQ_FLAGS_PG_SZ_32K (7<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define KRNLQ_FLAGS_PG_SZ_64K (8<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define KRNLQ_FLAGS_PG_SZ_128K (9<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define KRNLQ_FLAGS_PG_SZ_256K (10<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define KRNLQ_FLAGS_PG_SZ_512K (11<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define KRNLQ_FLAGS_PG_SZ_1M (12<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define KRNLQ_FLAGS_PG_SZ_2M (13<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define KRNLQ_FLAGS_QE_SELF_SEQ (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define KRNLQ_SIZE_TYPE_SIZE ((((0x28 + 0x1f) & ~0x1f) / 0x20) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define KRNLQ_TYPE_TYPE (0xf<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define KRNLQ_TYPE_TYPE_EMPTY (0<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define KRNLQ_TYPE_TYPE_KRNLQ (6<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define L5_KRNLQ_HOST_QIDX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define L5_KRNLQ_HOST_FW_QIDX 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define L5_KRNLQ_NX_QE_SELF_SEQ 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define L5_KRNLQ_QE_SELF_SEQ_MAX 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define L5_KRNLQ_NX_QE_HADDR_HI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define L5_KRNLQ_NX_QE_HADDR_LO 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define L5_KRNLQ_PGTBL_PGIDX 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define L5_KRNLQ_NX_PG_QIDX 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define L5_KRNLQ_PGTBL_NPAGES 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define L5_KRNLQ_QIDX_INCR 0x0000001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define L5_KRNLQ_PGTBL_HADDR_HI 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define L5_KRNLQ_PGTBL_HADDR_LO 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BNX2_PG_CTX_MAP 0x1a0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BNX2_ISCSI_CTX_MAP 0x1a0074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAX_COMPLETED_KCQE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAX_CNIC_L5_CONTEXT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAX_CM_SK_TBL_SZ MAX_CNIC_L5_CONTEXT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MAX_ISCSI_TBL_SZ 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CNIC_LOCAL_PORT_MIN 60000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CNIC_LOCAL_PORT_MAX 61024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CNIC_LOCAL_PORT_RANGE (CNIC_LOCAL_PORT_MAX - CNIC_LOCAL_PORT_MIN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define KWQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kwqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define KCQE_CNT (BNX2_PAGE_SIZE / sizeof(struct kcqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MAX_KWQE_CNT (KWQE_CNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MAX_KCQE_CNT (KCQE_CNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MAX_KWQ_IDX ((KWQ_PAGE_CNT * KWQE_CNT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX_KCQ_IDX ((KCQ_PAGE_CNT * KCQE_CNT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define KWQ_PG(x) (((x) & ~MAX_KWQE_CNT) >> (BNX2_PAGE_BITS - 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define KWQ_IDX(x) ((x) & MAX_KWQE_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define KCQ_PG(x) (((x) & ~MAX_KCQE_CNT) >> (BNX2_PAGE_BITS - 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define KCQ_IDX(x) ((x) & MAX_KCQE_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BNX2X_NEXT_KCQE(x) (((x) & (MAX_KCQE_CNT - 1)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) (MAX_KCQE_CNT - 1)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) (x) + 2 : (x) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BNX2X_KWQ_DATA_PG(cp, x) ((x) / (cp)->kwq_16_data_pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BNX2X_KWQ_DATA_IDX(cp, x) ((x) % (cp)->kwq_16_data_pp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BNX2X_KWQ_DATA(cp, x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) &(cp)->kwq_16_data[BNX2X_KWQ_DATA_PG(cp, x)][BNX2X_KWQ_DATA_IDX(cp, x)]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DEF_IPID_START 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DEF_KA_TIMEOUT 10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DEF_KA_INTERVAL 300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DEF_KA_MAX_PROBE_COUNT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DEF_TOS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define DEF_TTL 0xfe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DEF_SND_SEQ_SCALE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DEF_RCV_BUF 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DEF_SND_BUF 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DEF_SEED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DEF_MAX_RT_TIME 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DEF_MAX_DA_COUNT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DEF_SWS_TIMER 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DEF_MAX_CWND 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct cnic_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) void *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BNX2_MAX_CID 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct cnic_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int num_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void **pg_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dma_addr_t *pg_map_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) int pgtbl_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 *pgtbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dma_addr_t pgtbl_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct cnic_id_tbl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CNIC_KWQ16_DATA_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct kwqe_16_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u8 data[CNIC_KWQ16_DATA_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct cnic_iscsi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct cnic_dma task_array_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct cnic_dma r2tq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct cnic_dma hq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct cnic_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct kwqe_16_data *kwqe_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dma_addr_t kwqe_data_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) wait_queue_head_t waitq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int wait_cond;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) unsigned long timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) unsigned long ctx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CTX_FL_OFFLD_START 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CTX_FL_DELETE_WAIT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CTX_FL_CID_ERROR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) u8 ulp_proto_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct cnic_iscsi *iscsi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) } proto;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct kcq_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct cnic_dma dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct kcqe **kcq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u16 *hw_prod_idx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u16 sw_prod_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u16 *status_idx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u16 (*next_idx)(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u16 (*hw_idx)(u16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define UIO_USE_TX_DOORBELL 0x017855DB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct cnic_uio_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct uio_info cnic_uinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 uio_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int l2_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void *l2_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) dma_addr_t l2_ring_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) int l2_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) void *l2_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) dma_addr_t l2_buf_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct cnic_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct cnic_local {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) spinlock_t cnic_ulp_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) void *ulp_handle[MAX_CNIC_ULP_TYPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) unsigned long ulp_flags[MAX_CNIC_ULP_TYPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define ULP_F_INIT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ULP_F_START 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ULP_F_CALL_PENDING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct cnic_ulp_ops __rcu *ulp_ops[MAX_CNIC_ULP_TYPE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long cnic_local_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CNIC_LCL_FL_KWQ_INIT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CNIC_LCL_FL_L2_WAIT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CNIC_LCL_FL_RINGS_INITED 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CNIC_LCL_FL_STOP_ISCSI 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct cnic_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct cnic_eth_dev *ethdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct cnic_uio_dev *udev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int l2_rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int l2_single_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u16 *rx_cons_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u16 *tx_cons_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u16 rx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 tx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct cnic_dma kwq_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct kwqe **kwq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct cnic_dma kwq_16_data_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u16 max_kwq_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u16 kwq_prod_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 kwq_io_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u16 *kwq_con_idx_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u16 kwq_con_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct kcq_info kcq1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct kcq_info kcq2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) void *gen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct status_block_msix *bnx2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct host_hc_status_block_e1x *bnx2x_e1x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* index values - which counter to update */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SM_RX_ID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define SM_TX_ID 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) } status_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct host_sp_status_block *bnx2x_def_status_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 status_blk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 bnx2x_igu_sb_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 int_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 last_status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct tasklet_struct cnic_irq_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct kcqe *completed_kcq[MAX_COMPLETED_KCQE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct cnic_sock *csk_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct cnic_id_tbl csk_port_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct cnic_dma gbl_buf_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct cnic_iscsi *iscsi_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct cnic_context *ctx_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct cnic_id_tbl cid_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) atomic_t iscsi_conn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 iscsi_start_cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 fcoe_init_cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 fcoe_start_cid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct cnic_id_tbl fcoe_cid_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 max_cid_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* per connection parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int num_iscsi_tasks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int num_ccells;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int task_array_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int r2tq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) int hq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int num_cqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct delayed_work delete_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct cnic_ctx *ctx_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int ctx_blks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int ctx_blk_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned long ctx_align;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int cids_per_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u32 shmem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) struct cnic_ops *cnic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int (*start_hw)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) void (*stop_hw)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) void (*setup_pgtbl)(struct cnic_dev *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct cnic_dma *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int (*alloc_resc)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) void (*free_resc)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int (*start_cm)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) void (*stop_cm)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) void (*enable_int)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) void (*disable_int_sync)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) void (*ack_int)(struct cnic_dev *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) void (*arm_int)(struct cnic_dev *, u32 index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void (*close_conn)(struct cnic_sock *, u32 opcode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct bnx2x_bd_chain_next {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u8 reserved[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define ISCSI_DEFAULT_MAX_OUTSTANDING_R2T (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define ISCSI_RAMROD_CMD_ID_UPDATE_CONN (ISCSI_KCQE_OPCODE_UPDATE_CONN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define ISCSI_RAMROD_CMD_ID_INIT (ISCSI_KCQE_OPCODE_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define CDU_REGION_NUMBER_XCM_AG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define CDU_REGION_NUMBER_UCM_AG 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define CDU_VALID_DATA(_cid, _region, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) (((_cid) << 8) | (((_region)&0xf)<<4) | (((_type)&0xf)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define CDU_CRC8(_cid, _region, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) (calc_crc8(CDU_VALID_DATA(_cid, _region, _type), 0xff))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define CDU_RSRVD_VALUE_TYPE_A(_cid, _region, _type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) (0x80 | ((CDU_CRC8(_cid, _region, _type)) & 0x7f))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define BNX2X_CONTEXT_MEM_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define BNX2X_FCOE_CID 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BNX2X_ISCSI_START_CID 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define BNX2X_ISCSI_NUM_CONNECTIONS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define BNX2X_ISCSI_TASK_CONTEXT_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BNX2X_ISCSI_MAX_PENDING_R2TS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define BNX2X_ISCSI_R2TQE_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BNX2X_ISCSI_HQ_BD_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BNX2X_ISCSI_GLB_BUF_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define BNX2X_ISCSI_PBL_NOT_CACHED 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define BNX2X_ISCSI_PDU_HEADER_NOT_CACHED 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define BNX2X_FCOE_NUM_CONNECTIONS 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define BNX2X_FCOE_L5_CID_BASE MAX_ISCSI_TBL_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define BNX2X_CHIP_IS_E2_PLUS(bp) (CHIP_IS_E2(bp) || CHIP_IS_E3(bp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BNX2X_RX_DESC_CNT (BNX2_PAGE_SIZE / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) sizeof(struct eth_rx_bd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BNX2X_MAX_RX_DESC_CNT (BNX2X_RX_DESC_CNT - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define BNX2X_RCQ_DESC_CNT (BNX2_PAGE_SIZE / \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) sizeof(union eth_rx_cqe))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define BNX2X_MAX_RCQ_DESC_CNT (BNX2X_RCQ_DESC_CNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BNX2X_NEXT_RCQE(x) (((x) & BNX2X_MAX_RCQ_DESC_CNT) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) (BNX2X_MAX_RCQ_DESC_CNT - 1)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) ((x) + 2) : ((x) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define BNX2X_DEF_SB_ID HC_SP_SB_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define BNX2X_SHMEM_MF_BLK_OFFSET 0x7e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define BNX2X_SHMEM_ADDR(base, field) (base + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) offsetof(struct shmem_region, field))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define BNX2X_SHMEM2_ADDR(base, field) (base + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) offsetof(struct shmem2_region, field))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define BNX2X_SHMEM2_HAS(base, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) ((base) && \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) (CNIC_RD(dev, BNX2X_SHMEM2_ADDR(base, size)) > \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) offsetof(struct shmem2_region, field)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define BNX2X_MF_CFG_ADDR(base, field) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ((base) + offsetof(struct mf_cfg, field))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #ifndef ETH_MAX_RX_CLIENTS_E2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define ETH_MAX_RX_CLIENTS_E2 ETH_MAX_RX_CLIENTS_E1H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CNIC_FUNC(cp) ((cp)->func)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BNX2X_HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) (BP_VN(bp) << 17) | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BNX2X_SW_CID(x) (x & 0x1ffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BNX2X_CL_QZONE_ID(bp, cli) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) (BNX2X_CHIP_IS_E2_PLUS(bp) ? cli : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) cli + (BP_PORT(bp) * ETH_MAX_RX_CLIENTS_E1H))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #ifndef MAX_STAT_COUNTER_ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define MAX_STAT_COUNTER_ID \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) (CHIP_IS_E1H(bp) ? MAX_STAT_COUNTER_ID_E1H : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) ((BNX2X_CHIP_IS_E2_PLUS(bp)) ? MAX_STAT_COUNTER_ID_E2 : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MAX_STAT_COUNTER_ID_E1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CNIC_SUPPORTS_FCOE(cp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) (BNX2X_CHIP_IS_E2_PLUS(bp) && !NO_FCOE(bp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CNIC_RAMROD_TMO (HZ / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags