^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* bnx2.h: QLogic bnx2 network driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2004-2014 Broadcom Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2014-2015 QLogic Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * it under the terms of the GNU General Public License as published by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Written by: Michael Chan (mchan@broadcom.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef BNX2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BNX2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Hardware data structures and register definitions automatically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * generated from RTL code. Do not modify.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * tx_bd definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct bnx2_tx_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 tx_bd_haddr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u32 tx_bd_haddr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u32 tx_bd_mss_nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TX_BD_TCP6_OFF2_SHL (14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 tx_bd_vlan_tag_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TX_BD_FLAGS_CONN_FAULT (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TX_BD_FLAGS_TCP6_OFF0_MSK (3<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TX_BD_FLAGS_TCP6_OFF0_SHL (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TX_BD_FLAGS_TCP_UDP_CKSUM (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TX_BD_FLAGS_IP_CKSUM (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TX_BD_FLAGS_VLAN_TAG (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TX_BD_FLAGS_COAL_NOW (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TX_BD_FLAGS_DONT_GEN_CRC (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TX_BD_FLAGS_END (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TX_BD_FLAGS_START (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TX_BD_FLAGS_SW_OPTION_WORD (0x1f<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TX_BD_FLAGS_TCP6_OFF4_SHL (12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TX_BD_FLAGS_SW_FLAGS (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TX_BD_FLAGS_SW_SNAP (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TX_BD_FLAGS_SW_LSO (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * rx_bd definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct bnx2_rx_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 rx_bd_haddr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 rx_bd_haddr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 rx_bd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 rx_bd_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RX_BD_FLAGS_NOPUSH (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RX_BD_FLAGS_DUMMY (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RX_BD_FLAGS_END (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RX_BD_FLAGS_START (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BNX2_RX_ALIGN 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * status_block definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct status_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 status_attn_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define STATUS_ATTN_BITS_LINK_STATE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define STATUS_ATTN_BITS_TX_SCHEDULER_ABORT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define STATUS_ATTN_BITS_TX_BD_READ_ABORT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STATUS_ATTN_BITS_TX_BD_CACHE_ABORT (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STATUS_ATTN_BITS_TX_PROCESSOR_ABORT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define STATUS_ATTN_BITS_TX_DMA_ABORT (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define STATUS_ATTN_BITS_TX_PATCHUP_ABORT (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define STATUS_ATTN_BITS_TX_ASSEMBLER_ABORT (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define STATUS_ATTN_BITS_RX_PARSER_MAC_ABORT (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define STATUS_ATTN_BITS_RX_PARSER_CATCHUP_ABORT (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define STATUS_ATTN_BITS_RX_MBUF_ABORT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define STATUS_ATTN_BITS_RX_LOOKUP_ABORT (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define STATUS_ATTN_BITS_RX_PROCESSOR_ABORT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define STATUS_ATTN_BITS_RX_V2P_ABORT (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define STATUS_ATTN_BITS_RX_BD_CACHE_ABORT (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define STATUS_ATTN_BITS_RX_DMA_ABORT (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define STATUS_ATTN_BITS_COMPLETION_ABORT (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define STATUS_ATTN_BITS_HOST_COALESCE_ABORT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define STATUS_ATTN_BITS_MAILBOX_QUEUE_ABORT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define STATUS_ATTN_BITS_CONTEXT_ABORT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define STATUS_ATTN_BITS_CMD_SCHEDULER_ABORT (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define STATUS_ATTN_BITS_CMD_PROCESSOR_ABORT (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define STATUS_ATTN_BITS_MGMT_PROCESSOR_ABORT (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define STATUS_ATTN_BITS_MAC_ABORT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define STATUS_ATTN_BITS_TIMER_ABORT (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define STATUS_ATTN_BITS_DMAE_ABORT (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define STATUS_ATTN_BITS_FLSH_ABORT (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define STATUS_ATTN_BITS_GRC_ABORT (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define STATUS_ATTN_BITS_EPB_ERROR (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define STATUS_ATTN_BITS_PARITY_ERROR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 status_attn_bits_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u16 status_tx_quick_consumer_index0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u16 status_tx_quick_consumer_index1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u16 status_tx_quick_consumer_index2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 status_tx_quick_consumer_index3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u16 status_rx_quick_consumer_index0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 status_rx_quick_consumer_index1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 status_rx_quick_consumer_index2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 status_rx_quick_consumer_index3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 status_rx_quick_consumer_index4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u16 status_rx_quick_consumer_index5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 status_rx_quick_consumer_index6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 status_rx_quick_consumer_index7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u16 status_rx_quick_consumer_index8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u16 status_rx_quick_consumer_index9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u16 status_rx_quick_consumer_index10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u16 status_rx_quick_consumer_index11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u16 status_rx_quick_consumer_index12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 status_rx_quick_consumer_index13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u16 status_rx_quick_consumer_index14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u16 status_rx_quick_consumer_index15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u16 status_completion_producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u16 status_cmd_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u16 status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u8 status_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u8 status_blk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #elif defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u16 status_tx_quick_consumer_index1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u16 status_tx_quick_consumer_index0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u16 status_tx_quick_consumer_index3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u16 status_tx_quick_consumer_index2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 status_rx_quick_consumer_index1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 status_rx_quick_consumer_index0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u16 status_rx_quick_consumer_index3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u16 status_rx_quick_consumer_index2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u16 status_rx_quick_consumer_index5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u16 status_rx_quick_consumer_index4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u16 status_rx_quick_consumer_index7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u16 status_rx_quick_consumer_index6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u16 status_rx_quick_consumer_index9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u16 status_rx_quick_consumer_index8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u16 status_rx_quick_consumer_index11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u16 status_rx_quick_consumer_index10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u16 status_rx_quick_consumer_index13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u16 status_rx_quick_consumer_index12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 status_rx_quick_consumer_index15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u16 status_rx_quick_consumer_index14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u16 status_cmd_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u16 status_completion_producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u8 status_blk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u8 status_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * status_block definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct status_block_msix {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u16 status_tx_quick_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u16 status_rx_quick_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u16 status_completion_producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u16 status_cmd_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 status_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u16 status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u8 status_unused2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u8 status_blk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #elif defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) u16 status_rx_quick_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u16 status_tx_quick_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) u16 status_cmd_consumer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) u16 status_completion_producer_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 status_unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 status_blk_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 status_unused2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) u16 status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BNX2_SBLK_MSIX_ALIGN_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * statistics_block definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct statistics_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 stat_IfHCInOctets_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 stat_IfHCInOctets_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 stat_IfHCInBadOctets_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 stat_IfHCInBadOctets_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 stat_IfHCOutOctets_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 stat_IfHCOutOctets_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) u32 stat_IfHCOutBadOctets_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 stat_IfHCOutBadOctets_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 stat_IfHCInUcastPkts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 stat_IfHCInUcastPkts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 stat_IfHCInMulticastPkts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 stat_IfHCInMulticastPkts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 stat_IfHCInBroadcastPkts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 stat_IfHCInBroadcastPkts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 stat_IfHCOutUcastPkts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 stat_IfHCOutUcastPkts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 stat_IfHCOutMulticastPkts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 stat_IfHCOutMulticastPkts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 stat_IfHCOutBroadcastPkts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 stat_IfHCOutBroadcastPkts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) u32 stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 stat_Dot3StatsCarrierSenseErrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 stat_Dot3StatsFCSErrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 stat_Dot3StatsAlignmentErrors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 stat_Dot3StatsSingleCollisionFrames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u32 stat_Dot3StatsMultipleCollisionFrames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) u32 stat_Dot3StatsDeferredTransmissions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 stat_Dot3StatsExcessiveCollisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) u32 stat_Dot3StatsLateCollisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) u32 stat_EtherStatsCollisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) u32 stat_EtherStatsFragments;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) u32 stat_EtherStatsJabbers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u32 stat_EtherStatsUndersizePkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 stat_EtherStatsOverrsizePkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u32 stat_EtherStatsPktsRx64Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) u32 stat_EtherStatsPktsRx65Octetsto127Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u32 stat_EtherStatsPktsRx128Octetsto255Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 stat_EtherStatsPktsRx256Octetsto511Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) u32 stat_EtherStatsPktsRx512Octetsto1023Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 stat_EtherStatsPktsRx1024Octetsto1522Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 stat_EtherStatsPktsRx1523Octetsto9022Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 stat_EtherStatsPktsTx64Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u32 stat_EtherStatsPktsTx65Octetsto127Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 stat_EtherStatsPktsTx128Octetsto255Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 stat_EtherStatsPktsTx256Octetsto511Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 stat_EtherStatsPktsTx512Octetsto1023Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 stat_EtherStatsPktsTx1024Octetsto1522Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 stat_EtherStatsPktsTx1523Octetsto9022Octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 stat_XonPauseFramesReceived;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 stat_XoffPauseFramesReceived;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 stat_OutXonSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 stat_OutXoffSent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 stat_FlowControlDone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 stat_MacControlFramesReceived;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 stat_XoffStateEntered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 stat_IfInFramesL2FilterDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 stat_IfInRuleCheckerDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 stat_IfInFTQDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 stat_IfInMBUFDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 stat_IfInRuleCheckerP4Hit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 stat_CatchupInRuleCheckerDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 stat_CatchupInFTQDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 stat_CatchupInMBUFDiscards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 stat_CatchupInRuleCheckerP4Hit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 stat_GenStat00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 stat_GenStat01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 stat_GenStat02;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 stat_GenStat03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 stat_GenStat04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 stat_GenStat05;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 stat_GenStat06;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 stat_GenStat07;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 stat_GenStat08;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 stat_GenStat09;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 stat_GenStat10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 stat_GenStat11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 stat_GenStat12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) u32 stat_GenStat13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 stat_GenStat14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 stat_GenStat15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 stat_FwRxDrop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * l2_fhdr definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) struct l2_fhdr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 l2_fhdr_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define L2_FHDR_STATUS_RULE_CLASS (0x7<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define L2_FHDR_STATUS_RULE_P2 (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define L2_FHDR_STATUS_RULE_P3 (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define L2_FHDR_STATUS_RULE_P4 (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define L2_FHDR_STATUS_L2_VLAN_TAG (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define L2_FHDR_STATUS_L2_LLC_SNAP (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define L2_FHDR_STATUS_RSS_HASH (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define L2_FHDR_STATUS_IP_DATAGRAM (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define L2_FHDR_STATUS_TCP_SEGMENT (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define L2_FHDR_STATUS_UDP_DATAGRAM (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define L2_FHDR_STATUS_SPLIT (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define L2_FHDR_ERRORS_BAD_CRC (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define L2_FHDR_ERRORS_PHY_DECODE (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define L2_FHDR_ERRORS_ALIGNMENT (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define L2_FHDR_ERRORS_TOO_SHORT (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define L2_FHDR_ERRORS_GIANT_FRAME (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define L2_FHDR_ERRORS_TCP_XSUM (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define L2_FHDR_ERRORS_UDP_XSUM (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define L2_FHDR_STATUS_USE_RXHASH \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) (L2_FHDR_STATUS_TCP_SEGMENT | L2_FHDR_STATUS_RSS_HASH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 l2_fhdr_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #if defined(__BIG_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u16 l2_fhdr_pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u16 l2_fhdr_vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u16 l2_fhdr_ip_xsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u16 l2_fhdr_tcp_udp_xsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #elif defined(__LITTLE_ENDIAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u16 l2_fhdr_vlan_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) u16 l2_fhdr_pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u16 l2_fhdr_tcp_udp_xsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u16 l2_fhdr_ip_xsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BNX2_RX_OFFSET (sizeof(struct l2_fhdr) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * l2_context definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define BNX2_L2CTX_TYPE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define BNX2_L2CTX_TYPE_SIZE_L2 ((0xc0/0x20)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define BNX2_L2CTX_TYPE_TYPE (0xf<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define BNX2_L2CTX_TYPE_TYPE_EMPTY (0<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define BNX2_L2CTX_TYPE_TYPE_L2 (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define BNX2_L2CTX_TX_HOST_BIDX 0x00000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define BNX2_L2CTX_EST_NBD 0x00000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define BNX2_L2CTX_CMD_TYPE 0x00000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define BNX2_L2CTX_CMD_TYPE_TYPE (0xf<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define BNX2_L2CTX_CMD_TYPE_TYPE_L2 (0<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define BNX2_L2CTX_CMD_TYPE_TYPE_TCP (1<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define BNX2_L2CTX_TX_HOST_BSEQ 0x00000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BNX2_L2CTX_TSCH_BSEQ 0x00000094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define BNX2_L2CTX_TBDR_BSEQ 0x00000098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define BNX2_L2CTX_TBDR_BOFF 0x0000009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define BNX2_L2CTX_TBDR_BIDX 0x0000009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define BNX2_L2CTX_TBDR_BHADDR_HI 0x000000a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define BNX2_L2CTX_TBDR_BHADDR_LO 0x000000a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define BNX2_L2CTX_TXP_BOFF 0x000000a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define BNX2_L2CTX_TXP_BIDX 0x000000a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define BNX2_L2CTX_TXP_BSEQ 0x000000ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define BNX2_L2CTX_TYPE_XI 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define BNX2_L2CTX_CMD_TYPE_XI 0x00000240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define BNX2_L2CTX_TBDR_BHADDR_HI_XI 0x00000258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BNX2_L2CTX_TBDR_BHADDR_LO_XI 0x0000025c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * l2_bd_chain_context definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BNX2_L2CTX_BD_PRE_READ 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BNX2_L2CTX_CTX_SIZE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define BNX2_L2CTX_CTX_TYPE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define BNX2_L2CTX_FLOW_CTRL_ENABLE 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BNX2_L2CTX_CTX_TYPE_SIZE_L2 ((0x20/20)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE (0xf<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_UNDEFINED (0<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE (1<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define BNX2_L2CTX_HOST_BDIDX 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define BNX2_L2CTX_L5_STATUSB_NUM_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define BNX2_L2CTX_L2_STATUSB_NUM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define BNX2_L2CTX_L5_STATUSB_NUM(sb_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L5_STATUSB_NUM_SHIFT) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define BNX2_L2CTX_L2_STATUSB_NUM(sb_id) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) (((sb_id) > 0) ? (((sb_id) + 7) << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT) : 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define BNX2_L2CTX_HOST_BSEQ 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BNX2_L2CTX_NX_BSEQ 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define BNX2_L2CTX_NX_BDHADDR_HI 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BNX2_L2CTX_NX_BDHADDR_LO 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define BNX2_L2CTX_NX_BDIDX 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define BNX2_L2CTX_HOST_PG_BDIDX 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define BNX2_L2CTX_PG_BUF_SIZE 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BNX2_L2CTX_RBDC_KEY 0x0000004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define BNX2_L2CTX_RBDC_JUMBO_KEY 0x3ffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define BNX2_L2CTX_NX_PG_BDHADDR_HI 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define BNX2_L2CTX_NX_PG_BDHADDR_LO 0x00000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * pci_config_l definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * offset: 0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define BNX2_PCICFG_MSI_CONTROL 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define BNX2_PCICFG_MSI_CONTROL_ENABLE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define BNX2_PCICFG_MISC_CONFIG 0x00000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define BNX2_PCICFG_MISC_CONFIG_TARGET_BYTE_SWAP (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define BNX2_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define BNX2_PCICFG_MISC_CONFIG_RESERVED1 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define BNX2_PCICFG_MISC_CONFIG_CLOCK_CTL_ENA (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define BNX2_PCICFG_MISC_CONFIG_TARGET_GRC_WORD_SWAP (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define BNX2_PCICFG_MISC_CONFIG_REG_WINDOW_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_REQ (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define BNX2_PCICFG_MISC_CONFIG_CORE_RST_BSY (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN1_SWAP_EN (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN2_SWAP_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define BNX2_PCICFG_MISC_CONFIG_GRC_WIN3_SWAP_EN (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define BNX2_PCICFG_MISC_CONFIG_ASIC_METAL_REV (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define BNX2_PCICFG_MISC_CONFIG_ASIC_BASE_REV (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define BNX2_PCICFG_MISC_CONFIG_ASIC_ID (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BNX2_PCICFG_MISC_STATUS 0x0000006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define BNX2_PCICFG_MISC_STATUS_INTA_VALUE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define BNX2_PCICFG_MISC_STATUS_32BIT_DET (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define BNX2_PCICFG_MISC_STATUS_M66EN (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define BNX2_PCICFG_MISC_STATUS_PCIX_DET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_66 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_100 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_133 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define BNX2_PCICFG_MISC_STATUS_PCIX_SPEED_PCI_MODE (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define BNX2_PCICFG_MISC_STATUS_BAD_MEM_WRITE_BE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_17 (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_18 (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED_19 (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define BNX2_PCICFG_PCI_CLOCK_CONTROL_BITS_RESERVED (0xfffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define BNX2_PCICFG_REG_WINDOW_ADDRESS 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define BNX2_PCICFG_REG_WINDOW_ADDRESS_VAL (0xfffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define BNX2_PCICFG_REG_WINDOW 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define BNX2_PCICFG_INT_ACK_CMD 0x00000084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define BNX2_PCICFG_INT_ACK_CMD_INDEX (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define BNX2_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define BNX2_PCICFG_INT_ACK_CMD_MASK_INT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define BNX2_PCICFG_INT_ACK_CMD_INTERRUPT_NUM (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define BNX2_PCICFG_STATUS_BIT_SET_CMD 0x00000088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define BNX2_PCICFG_STATUS_BIT_CLEAR_CMD 0x0000008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define BNX2_PCICFG_MAILBOX_QUEUE_ADDR 0x00000090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define BNX2_PCICFG_MAILBOX_QUEUE_DATA 0x00000094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define BNX2_PCICFG_DEVICE_CONTROL 0x000000b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define BNX2_PCICFG_DEVICE_STATUS_NO_PEND ((1L<<5)<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * pci_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * offset: 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define BNX2_PCI_GRC_WINDOW_ADDR 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define BNX2_PCI_GRC_WINDOW_ADDR_VALUE (0x1ffL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define BNX2_PCI_GRC_WINDOW_ADDR_SEP_WIN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define BNX2_PCI_GRC_WINDOW2_BASE 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define BNX2_PCI_GRC_WINDOW3_BASE 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define BNX2_PCI_CONFIG_1 0x00000404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define BNX2_PCI_CONFIG_1_RESERVED0 (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_OFF (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_16 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_32 (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_64 (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_128 (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_256 (5L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_512 (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define BNX2_PCI_CONFIG_1_READ_BOUNDARY_1024 (7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY (0x7L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_OFF (0L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_16 (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_32 (2L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_64 (3L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_128 (4L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_256 (5L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_512 (6L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define BNX2_PCI_CONFIG_1_WRITE_BOUNDARY_1024 (7L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define BNX2_PCI_CONFIG_1_RESERVED1 (0x3ffffL<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define BNX2_PCI_CONFIG_2 0x00000408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define BNX2_PCI_CONFIG_2_BAR1_SIZE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_DISABLED (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64K (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128K (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256K (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512K (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1M (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_2M (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_4M (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_8M (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_16M (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_32M (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_64M (11L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_128M (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_256M (13L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_512M (14L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define BNX2_PCI_CONFIG_2_BAR1_SIZE_1G (15L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define BNX2_PCI_CONFIG_2_BAR1_64ENA (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define BNX2_PCI_CONFIG_2_EXP_ROM_RETRY (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define BNX2_PCI_CONFIG_2_CFG_CYCLE_RETRY (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define BNX2_PCI_CONFIG_2_FIRST_CFG_DONE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_DISABLED (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1K (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2K (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4K (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8K (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16K (5L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_32K (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_64K (7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_128K (8L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_256K (9L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_512K (10L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_1M (11L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_2M (12L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_4M (13L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_8M (14L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define BNX2_PCI_CONFIG_2_EXP_ROM_SIZE_16M (15L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define BNX2_PCI_CONFIG_2_MAX_SPLIT_LIMIT (0x1fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT (0x3L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_512 (0L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_1K (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_2K (2L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define BNX2_PCI_CONFIG_2_MAX_READ_LIMIT_4K (3L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_MSTR (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define BNX2_PCI_CONFIG_2_FORCE_32_BIT_TGT (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define BNX2_PCI_CONFIG_2_KEEP_REQ_ASSERT (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define BNX2_PCI_CONFIG_2_RESERVED0 (0x3fL<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define BNX2_PCI_CONFIG_2_BAR_PREFETCH_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define BNX2_PCI_CONFIG_2_RESERVED0_XI (0x7fffL<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define BNX2_PCI_CONFIG_3 0x0000040c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define BNX2_PCI_CONFIG_3_STICKY_BYTE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define BNX2_PCI_CONFIG_3_REG_STICKY_BYTE (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define BNX2_PCI_CONFIG_3_FORCE_PME (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define BNX2_PCI_CONFIG_3_PME_STATUS (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define BNX2_PCI_CONFIG_3_PME_ENABLE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define BNX2_PCI_CONFIG_3_PM_STATE (0x3L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define BNX2_PCI_CONFIG_3_VAUX_PRESET (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define BNX2_PCI_CONFIG_3_PCI_POWER (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define BNX2_PCI_PM_DATA_A 0x00000410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define BNX2_PCI_PM_DATA_A_PM_DATA_0_PRG (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define BNX2_PCI_PM_DATA_A_PM_DATA_1_PRG (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define BNX2_PCI_PM_DATA_A_PM_DATA_2_PRG (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define BNX2_PCI_PM_DATA_A_PM_DATA_3_PRG (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define BNX2_PCI_PM_DATA_B 0x00000414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define BNX2_PCI_PM_DATA_B_PM_DATA_4_PRG (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define BNX2_PCI_PM_DATA_B_PM_DATA_5_PRG (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define BNX2_PCI_PM_DATA_B_PM_DATA_6_PRG (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define BNX2_PCI_PM_DATA_B_PM_DATA_7_PRG (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define BNX2_PCI_SWAP_DIAG0 0x00000418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define BNX2_PCI_SWAP_DIAG1 0x0000041c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define BNX2_PCI_EXP_ROM_ADDR 0x00000420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define BNX2_PCI_EXP_ROM_ADDR_ADDRESS (0x3fffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define BNX2_PCI_EXP_ROM_ADDR_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define BNX2_PCI_EXP_ROM_DATA 0x00000424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define BNX2_PCI_VPD_INTF 0x00000428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define BNX2_PCI_VPD_INTF_INTF_REQ (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define BNX2_PCI_VPD_ADDR_FLAG 0x0000042c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define BNX2_PCI_VPD_ADDR_FLAG_MSK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define BNX2_PCI_VPD_ADDR_FLAG_SL 0L
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define BNX2_PCI_VPD_ADDR_FLAG_ADDRESS (0x1fffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define BNX2_PCI_VPD_ADDR_FLAG_WR (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define BNX2_PCI_VPD_DATA 0x00000430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define BNX2_PCI_ID_VAL1 0x00000434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define BNX2_PCI_ID_VAL1_DEVICE_ID (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define BNX2_PCI_ID_VAL1_VENDOR_ID (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define BNX2_PCI_ID_VAL2 0x00000438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define BNX2_PCI_ID_VAL2_SUBSYSTEM_VENDOR_ID (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define BNX2_PCI_ID_VAL2_SUBSYSTEM_ID (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define BNX2_PCI_ID_VAL3 0x0000043c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define BNX2_PCI_ID_VAL3_CLASS_CODE (0xffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define BNX2_PCI_ID_VAL3_REVISION_ID (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define BNX2_PCI_ID_VAL4 0x00000440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define BNX2_PCI_ID_VAL4_CAP_ENA (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define BNX2_PCI_ID_VAL4_CAP_ENA_0 (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define BNX2_PCI_ID_VAL4_CAP_ENA_1 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define BNX2_PCI_ID_VAL4_CAP_ENA_2 (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define BNX2_PCI_ID_VAL4_CAP_ENA_3 (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define BNX2_PCI_ID_VAL4_CAP_ENA_4 (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define BNX2_PCI_ID_VAL4_CAP_ENA_5 (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define BNX2_PCI_ID_VAL4_CAP_ENA_6 (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define BNX2_PCI_ID_VAL4_CAP_ENA_7 (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define BNX2_PCI_ID_VAL4_CAP_ENA_8 (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define BNX2_PCI_ID_VAL4_CAP_ENA_9 (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define BNX2_PCI_ID_VAL4_CAP_ENA_10 (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define BNX2_PCI_ID_VAL4_CAP_ENA_11 (11L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define BNX2_PCI_ID_VAL4_CAP_ENA_12 (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define BNX2_PCI_ID_VAL4_CAP_ENA_13 (13L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define BNX2_PCI_ID_VAL4_CAP_ENA_14 (14L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define BNX2_PCI_ID_VAL4_CAP_ENA_15 (15L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define BNX2_PCI_ID_VAL4_RESERVED0 (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG (0x3L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_0 (0L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_2 (2L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define BNX2_PCI_ID_VAL4_PM_SCALE_PRG_3 (3L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define BNX2_PCI_ID_VAL4_MSI_PV_MASK_CAP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define BNX2_PCI_ID_VAL4_MSI_LIMIT (0x7L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define BNX2_PCI_ID_VAL4_MULTI_MSG_CAP (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define BNX2_PCI_ID_VAL4_MSI_ENABLE (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define BNX2_PCI_ID_VAL4_MAX_64_ADVERTIZE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define BNX2_PCI_ID_VAL4_MAX_133_ADVERTIZE (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define BNX2_PCI_ID_VAL4_RESERVED2 (0x7L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B21 (0x3L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B21 (0x3L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) #define BNX2_PCI_ID_VAL4_MAX_CUMULATIVE_SIZE_B0 (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define BNX2_PCI_ID_VAL4_MAX_MEM_READ_SIZE_B10 (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define BNX2_PCI_ID_VAL4_MAX_SPLIT_SIZE_B0 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define BNX2_PCI_ID_VAL4_RESERVED3 (0x7L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define BNX2_PCI_ID_VAL4_RESERVED3_XI (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) #define BNX2_PCI_ID_VAL5 0x00000444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define BNX2_PCI_ID_VAL5_D1_SUPPORT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define BNX2_PCI_ID_VAL5_D2_SUPPORT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define BNX2_PCI_ID_VAL5_PME_IN_D0 (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define BNX2_PCI_ID_VAL5_PME_IN_D1 (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define BNX2_PCI_ID_VAL5_PME_IN_D2 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) #define BNX2_PCI_ID_VAL5_PME_IN_D3_HOT (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define BNX2_PCI_ID_VAL5_RESERVED0_TE (0x3ffffffL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) #define BNX2_PCI_ID_VAL5_PM_VERSION_XI (0x7L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define BNX2_PCI_ID_VAL5_NO_SOFT_RESET_XI (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) #define BNX2_PCI_ID_VAL5_RESERVED0_XI (0x3fffffL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) #define BNX2_PCI_PCIX_EXTENDED_STATUS 0x00000448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define BNX2_PCI_PCIX_EXTENDED_STATUS_NO_SNOOP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define BNX2_PCI_PCIX_EXTENDED_STATUS_LONG_BURST (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_CLASS (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #define BNX2_PCI_PCIX_EXTENDED_STATUS_SPLIT_COMP_MSG_IDX (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) #define BNX2_PCI_ID_VAL6 0x0000044c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define BNX2_PCI_ID_VAL6_MAX_LAT (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) #define BNX2_PCI_ID_VAL6_MIN_GNT (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define BNX2_PCI_ID_VAL6_BIST (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) #define BNX2_PCI_ID_VAL6_RESERVED0 (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define BNX2_PCI_MSI_DATA 0x00000450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define BNX2_PCI_MSI_DATA_MSI_DATA (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define BNX2_PCI_MSI_ADDR_H 0x00000454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) #define BNX2_PCI_MSI_ADDR_L 0x00000458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define BNX2_PCI_MSI_ADDR_L_VAL (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define BNX2_PCI_CFG_ACCESS_CMD 0x0000045c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define BNX2_PCI_CFG_ACCESS_CMD_ADR (0x3fL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define BNX2_PCI_CFG_ACCESS_CMD_RD_REQ (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) #define BNX2_PCI_CFG_ACCESS_CMD_WR_REQ (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) #define BNX2_PCI_CFG_ACCESS_DATA 0x00000460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define BNX2_PCI_MSI_MASK 0x00000464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #define BNX2_PCI_MSI_MASK_MSI_MASK (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define BNX2_PCI_MSI_PEND 0x00000468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define BNX2_PCI_MSI_PEND_MSI_PEND (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define BNX2_PCI_PM_DATA_C 0x0000046c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) #define BNX2_PCI_PM_DATA_C_PM_DATA_8_PRG (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define BNX2_PCI_PM_DATA_C_RESERVED0 (0xffffffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define BNX2_PCI_MSIX_CONTROL 0x000004c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) #define BNX2_PCI_MSIX_CONTROL_MSIX_TBL_SIZ (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define BNX2_PCI_MSIX_CONTROL_RESERVED0 (0x1fffffL<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define BNX2_PCI_MSIX_TBL_OFF_BIR 0x000004c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_BIR (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define BNX2_PCI_MSIX_TBL_OFF_BIR_MSIX_TBL_OFF (0x1fffffffL<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define BNX2_PCI_MSIX_PBA_OFF_BIT 0x000004c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_BIR (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define BNX2_PCI_MSIX_PBA_OFF_BIT_MSIX_PBA_OFF (0x1fffffffL<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define BNX2_PCI_PCIE_CAPABILITY 0x000004d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define BNX2_PCI_PCIE_CAPABILITY_INTERRUPT_MSG_NUM (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define BNX2_PCI_PCIE_CAPABILITY_COMPLY_PCIE_1_1 (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define BNX2_PCI_DEVICE_CAPABILITY 0x000004d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define BNX2_PCI_DEVICE_CAPABILITY_MAX_PL_SIZ_SUPPORTED (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define BNX2_PCI_DEVICE_CAPABILITY_EXTENDED_TAG_SUPPORT (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define BNX2_PCI_DEVICE_CAPABILITY_L0S_ACCEPTABLE_LATENCY (0x7L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define BNX2_PCI_DEVICE_CAPABILITY_L1_ACCEPTABLE_LATENCY (0x7L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define BNX2_PCI_DEVICE_CAPABILITY_ROLE_BASED_ERR_RPT (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) #define BNX2_PCI_LINK_CAPABILITY 0x000004dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0001 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_SPEED_0010 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) #define BNX2_PCI_LINK_CAPABILITY_MAX_LINK_WIDTH (0x1fL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define BNX2_PCI_LINK_CAPABILITY_CLK_POWER_MGMT (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) #define BNX2_PCI_LINK_CAPABILITY_ASPM_SUPPORT (0x3L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_101 (5L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_LAT_110 (6L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT (0x7L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_001 (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_LAT_010 (2L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT (0x7L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_101 (5L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define BNX2_PCI_LINK_CAPABILITY_L0S_EXIT_COMM_LAT_110 (6L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT (0x7L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_001 (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) #define BNX2_PCI_LINK_CAPABILITY_L1_EXIT_COMM_LAT_010 (2L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define BNX2_PCI_LINK_CAPABILITY_PORT_NUM (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2 0x000004e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_RANGE_SUPP (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_CMPL_TO_DISABL_SUPP (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) #define BNX2_PCI_PCIE_DEVICE_CAPABILITY_2_RESERVED (0x7ffffffL<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define BNX2_PCI_PCIE_LINK_CAPABILITY_2 0x000004e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define BNX2_PCI_PCIE_LINK_CAPABILITY_2_RESERVED (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define BNX2_PCI_GRC_WINDOW1_ADDR 0x00000610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) #define BNX2_PCI_GRC_WINDOW1_ADDR_VALUE (0x1ffL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define BNX2_PCI_GRC_WINDOW2_ADDR 0x00000614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define BNX2_PCI_GRC_WINDOW2_ADDR_VALUE (0x1ffL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define BNX2_PCI_GRC_WINDOW3_ADDR 0x00000618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #define BNX2_PCI_GRC_WINDOW3_ADDR_VALUE (0x1ffL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define BNX2_MSIX_TABLE_ADDR 0x318000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define BNX2_MSIX_PBA_ADDR 0x31c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * misc_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * offset: 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define BNX2_MISC_COMMAND 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) #define BNX2_MISC_COMMAND_ENABLE_ALL (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define BNX2_MISC_COMMAND_DISABLE_ALL (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) #define BNX2_MISC_COMMAND_SW_RESET (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define BNX2_MISC_COMMAND_POR_RESET (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) #define BNX2_MISC_COMMAND_HD_RESET (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define BNX2_MISC_COMMAND_CMN_SW_RESET (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) #define BNX2_MISC_COMMAND_PAR_ERROR (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define BNX2_MISC_COMMAND_CS16_ERR (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) #define BNX2_MISC_COMMAND_CS16_ERR_LOC (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define BNX2_MISC_COMMAND_PAR_ERR_RAM (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) #define BNX2_MISC_COMMAND_POWERDOWN_EVENT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define BNX2_MISC_COMMAND_SW_SHUTDOWN (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) #define BNX2_MISC_COMMAND_SHUTDOWN_EN (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define BNX2_MISC_COMMAND_DINTEG_ATTN_EN (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) #define BNX2_MISC_COMMAND_PCIE_LINK_IN_L23 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define BNX2_MISC_COMMAND_PCIE_DIS (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define BNX2_MISC_CFG 0x00000804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) #define BNX2_MISC_CFG_GRC_TMOUT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define BNX2_MISC_CFG_NVM_WR_EN (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) #define BNX2_MISC_CFG_NVM_WR_EN_PROTECT (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define BNX2_MISC_CFG_NVM_WR_EN_PCI (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW (2L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define BNX2_MISC_CFG_NVM_WR_EN_ALLOW2 (3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) #define BNX2_MISC_CFG_BIST_EN (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) #define BNX2_MISC_CFG_CK25_OUT_ALT_SRC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) #define BNX2_MISC_CFG_RESERVED5_TE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define BNX2_MISC_CFG_RESERVED6_TE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) #define BNX2_MISC_CFG_CLK_CTL_OVERRIDE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) #define BNX2_MISC_CFG_LEDMODE (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) #define BNX2_MISC_CFG_LEDMODE_MAC (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define BNX2_MISC_CFG_LEDMODE_PHY1_TE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #define BNX2_MISC_CFG_LEDMODE_PHY2_TE (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define BNX2_MISC_CFG_LEDMODE_PHY3_TE (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) #define BNX2_MISC_CFG_LEDMODE_PHY4_TE (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define BNX2_MISC_CFG_LEDMODE_PHY5_TE (5L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define BNX2_MISC_CFG_LEDMODE_PHY6_TE (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define BNX2_MISC_CFG_LEDMODE_PHY7_TE (7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #define BNX2_MISC_CFG_MCP_GRC_TMOUT_TE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define BNX2_MISC_CFG_DBU_GRC_TMOUT_TE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) #define BNX2_MISC_CFG_LEDMODE_XI (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define BNX2_MISC_CFG_LEDMODE_MAC_XI (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #define BNX2_MISC_CFG_LEDMODE_PHY1_XI (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define BNX2_MISC_CFG_LEDMODE_PHY2_XI (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) #define BNX2_MISC_CFG_LEDMODE_PHY3_XI (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define BNX2_MISC_CFG_LEDMODE_MAC2_XI (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) #define BNX2_MISC_CFG_LEDMODE_PHY4_XI (5L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define BNX2_MISC_CFG_LEDMODE_PHY5_XI (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #define BNX2_MISC_CFG_LEDMODE_PHY6_XI (7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define BNX2_MISC_CFG_LEDMODE_MAC3_XI (8L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #define BNX2_MISC_CFG_LEDMODE_PHY7_XI (9L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define BNX2_MISC_CFG_LEDMODE_PHY8_XI (10L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) #define BNX2_MISC_CFG_LEDMODE_PHY9_XI (11L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define BNX2_MISC_CFG_LEDMODE_MAC4_XI (12L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) #define BNX2_MISC_CFG_LEDMODE_PHY10_XI (13L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define BNX2_MISC_CFG_LEDMODE_PHY11_XI (14L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #define BNX2_MISC_CFG_LEDMODE_UNUSED_XI (15L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define BNX2_MISC_CFG_PORT_SELECT_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) #define BNX2_MISC_CFG_PARITY_MODE_XI (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #define BNX2_MISC_ID 0x00000808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) #define BNX2_MISC_ID_BOND_ID (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) #define BNX2_MISC_ID_BOND_ID_X (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define BNX2_MISC_ID_BOND_ID_C (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) #define BNX2_MISC_ID_BOND_ID_S (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define BNX2_MISC_ID_CHIP_METAL (0xffL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) #define BNX2_MISC_ID_CHIP_REV (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define BNX2_MISC_ID_CHIP_NUM (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define BNX2_MISC_ENABLE_STATUS_BITS 0x0000080c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_SCHEDULER_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_READ_ENABLE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_BD_CACHE_ENABLE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PROCESSOR_ENABLE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_DMA_ENABLE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PATCHUP_ENABLE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_HEADER_Q_ENABLE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #define BNX2_MISC_ENABLE_STATUS_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define BNX2_MISC_ENABLE_STATUS_BITS_EMAC_ENABLE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_MBUF_ENABLE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_LOOKUP_ENABLE (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_PROCESSOR_ENABLE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_BD_CACHE_ENABLE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #define BNX2_MISC_ENABLE_STATUS_BITS_RX_DMA_ENABLE (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define BNX2_MISC_ENABLE_STATUS_BITS_COMPLETION_ENABLE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) #define BNX2_MISC_ENABLE_STATUS_BITS_HOST_COALESCE_ENABLE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define BNX2_MISC_ENABLE_STATUS_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) #define BNX2_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define BNX2_MISC_ENABLE_STATUS_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define BNX2_MISC_ENABLE_STATUS_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) #define BNX2_MISC_ENABLE_STATUS_BITS_TIMER_ENABLE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define BNX2_MISC_ENABLE_STATUS_BITS_DMA_ENGINE_ENABLE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) #define BNX2_MISC_ENABLE_STATUS_BITS_UMP_ENABLE (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define BNX2_MISC_ENABLE_STATUS_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define BNX2_MISC_ENABLE_STATUS_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define BNX2_MISC_ENABLE_SET_BITS 0x00000810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define BNX2_MISC_ENABLE_SET_BITS_TX_SCHEDULER_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_READ_ENABLE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define BNX2_MISC_ENABLE_SET_BITS_TX_BD_CACHE_ENABLE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define BNX2_MISC_ENABLE_SET_BITS_TX_PROCESSOR_ENABLE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define BNX2_MISC_ENABLE_SET_BITS_TX_DMA_ENABLE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define BNX2_MISC_ENABLE_SET_BITS_TX_PATCHUP_ENABLE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define BNX2_MISC_ENABLE_SET_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define BNX2_MISC_ENABLE_SET_BITS_TX_HEADER_Q_ENABLE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define BNX2_MISC_ENABLE_SET_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) #define BNX2_MISC_ENABLE_SET_BITS_EMAC_ENABLE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) #define BNX2_MISC_ENABLE_SET_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define BNX2_MISC_ENABLE_SET_BITS_RX_MBUF_ENABLE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) #define BNX2_MISC_ENABLE_SET_BITS_RX_LOOKUP_ENABLE (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define BNX2_MISC_ENABLE_SET_BITS_RX_PROCESSOR_ENABLE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) #define BNX2_MISC_ENABLE_SET_BITS_RX_V2P_ENABLE (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define BNX2_MISC_ENABLE_SET_BITS_RX_BD_CACHE_ENABLE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) #define BNX2_MISC_ENABLE_SET_BITS_RX_DMA_ENABLE (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define BNX2_MISC_ENABLE_SET_BITS_COMPLETION_ENABLE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) #define BNX2_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define BNX2_MISC_ENABLE_SET_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) #define BNX2_MISC_ENABLE_SET_BITS_CONTEXT_ENABLE (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define BNX2_MISC_ENABLE_SET_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) #define BNX2_MISC_ENABLE_SET_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define BNX2_MISC_ENABLE_SET_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define BNX2_MISC_ENABLE_SET_BITS_TIMER_ENABLE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define BNX2_MISC_ENABLE_SET_BITS_DMA_ENGINE_ENABLE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define BNX2_MISC_ENABLE_SET_BITS_UMP_ENABLE (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define BNX2_MISC_ENABLE_SET_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define BNX2_MISC_ENABLE_SET_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define BNX2_MISC_ENABLE_CLR_BITS 0x00000814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define BNX2_MISC_ENABLE_CLR_BITS_TX_SCHEDULER_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_READ_ENABLE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define BNX2_MISC_ENABLE_CLR_BITS_TX_BD_CACHE_ENABLE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) #define BNX2_MISC_ENABLE_CLR_BITS_TX_PROCESSOR_ENABLE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define BNX2_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) #define BNX2_MISC_ENABLE_CLR_BITS_TX_PATCHUP_ENABLE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define BNX2_MISC_ENABLE_CLR_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) #define BNX2_MISC_ENABLE_CLR_BITS_TX_HEADER_Q_ENABLE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define BNX2_MISC_ENABLE_CLR_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) #define BNX2_MISC_ENABLE_CLR_BITS_EMAC_ENABLE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) #define BNX2_MISC_ENABLE_CLR_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define BNX2_MISC_ENABLE_CLR_BITS_RX_MBUF_ENABLE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) #define BNX2_MISC_ENABLE_CLR_BITS_RX_LOOKUP_ENABLE (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define BNX2_MISC_ENABLE_CLR_BITS_RX_PROCESSOR_ENABLE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) #define BNX2_MISC_ENABLE_CLR_BITS_RX_V2P_ENABLE (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define BNX2_MISC_ENABLE_CLR_BITS_RX_BD_CACHE_ENABLE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) #define BNX2_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define BNX2_MISC_ENABLE_CLR_BITS_COMPLETION_ENABLE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) #define BNX2_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define BNX2_MISC_ENABLE_CLR_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) #define BNX2_MISC_ENABLE_CLR_BITS_CONTEXT_ENABLE (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define BNX2_MISC_ENABLE_CLR_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) #define BNX2_MISC_ENABLE_CLR_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define BNX2_MISC_ENABLE_CLR_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) #define BNX2_MISC_ENABLE_CLR_BITS_TIMER_ENABLE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define BNX2_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #define BNX2_MISC_ENABLE_CLR_BITS_UMP_ENABLE (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define BNX2_MISC_ENABLE_CLR_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) #define BNX2_MISC_ENABLE_CLR_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) #define BNX2_MISC_CLOCK_CONTROL_BITS 0x00000818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) #define BNX2_MISC_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_DISABLE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_UNDEF (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_12 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_6 (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_SRC_62 (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED0_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) #define BNX2_MISC_CLOCK_CONTROL_BITS_MIN_POWER (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_100 (0L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_80 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_50 (2L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_40 (4L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_25 (8L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED1_XI (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_STOP (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_17_TE (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_18_TE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_19_TE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED_TE (0xfffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_ALT_MGMT_XI (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED2_XI (0x3fL<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_VCO_XI (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) #define BNX2_MISC_CLOCK_CONTROL_BITS_RESERVED3_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) #define BNX2_MISC_CLOCK_CONTROL_BITS_CORE_CLK_PLL_SPEED_XI (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) #define BNX2_MISC_SPIO 0x0000081c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #define BNX2_MISC_SPIO_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) #define BNX2_MISC_SPIO_SET (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) #define BNX2_MISC_SPIO_CLR (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) #define BNX2_MISC_SPIO_FLOAT (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) #define BNX2_MISC_SPIO_INT 0x00000820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #define BNX2_MISC_SPIO_INT_INT_STATE_TE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define BNX2_MISC_SPIO_INT_OLD_VALUE_TE (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) #define BNX2_MISC_SPIO_INT_OLD_SET_TE (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) #define BNX2_MISC_SPIO_INT_OLD_CLR_TE (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) #define BNX2_MISC_SPIO_INT_INT_STATE_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #define BNX2_MISC_SPIO_INT_OLD_VALUE_XI (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) #define BNX2_MISC_SPIO_INT_OLD_SET_XI (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) #define BNX2_MISC_SPIO_INT_OLD_CLR_XI (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) #define BNX2_MISC_CONFIG_LFSR 0x00000824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define BNX2_MISC_CONFIG_LFSR_DIV (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) #define BNX2_MISC_LFSR_MASK_BITS 0x00000828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) #define BNX2_MISC_LFSR_MASK_BITS_TX_SCHEDULER_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_READ_ENABLE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #define BNX2_MISC_LFSR_MASK_BITS_TX_BD_CACHE_ENABLE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) #define BNX2_MISC_LFSR_MASK_BITS_TX_PROCESSOR_ENABLE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) #define BNX2_MISC_LFSR_MASK_BITS_TX_DMA_ENABLE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) #define BNX2_MISC_LFSR_MASK_BITS_TX_PATCHUP_ENABLE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) #define BNX2_MISC_LFSR_MASK_BITS_TX_PAYLOAD_Q_ENABLE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) #define BNX2_MISC_LFSR_MASK_BITS_TX_HEADER_Q_ENABLE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) #define BNX2_MISC_LFSR_MASK_BITS_TX_ASSEMBLER_ENABLE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) #define BNX2_MISC_LFSR_MASK_BITS_EMAC_ENABLE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_MAC_ENABLE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #define BNX2_MISC_LFSR_MASK_BITS_RX_PARSER_CATCHUP_ENABLE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #define BNX2_MISC_LFSR_MASK_BITS_RX_MBUF_ENABLE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) #define BNX2_MISC_LFSR_MASK_BITS_RX_LOOKUP_ENABLE (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) #define BNX2_MISC_LFSR_MASK_BITS_RX_PROCESSOR_ENABLE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define BNX2_MISC_LFSR_MASK_BITS_RX_V2P_ENABLE (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) #define BNX2_MISC_LFSR_MASK_BITS_RX_BD_CACHE_ENABLE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) #define BNX2_MISC_LFSR_MASK_BITS_RX_DMA_ENABLE (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) #define BNX2_MISC_LFSR_MASK_BITS_COMPLETION_ENABLE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) #define BNX2_MISC_LFSR_MASK_BITS_HOST_COALESCE_ENABLE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) #define BNX2_MISC_LFSR_MASK_BITS_MAILBOX_QUEUE_ENABLE (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define BNX2_MISC_LFSR_MASK_BITS_CONTEXT_ENABLE (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define BNX2_MISC_LFSR_MASK_BITS_CMD_SCHEDULER_ENABLE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) #define BNX2_MISC_LFSR_MASK_BITS_CMD_PROCESSOR_ENABLE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) #define BNX2_MISC_LFSR_MASK_BITS_MGMT_PROCESSOR_ENABLE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #define BNX2_MISC_LFSR_MASK_BITS_TIMER_ENABLE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) #define BNX2_MISC_LFSR_MASK_BITS_DMA_ENGINE_ENABLE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) #define BNX2_MISC_LFSR_MASK_BITS_UMP_ENABLE (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) #define BNX2_MISC_LFSR_MASK_BITS_RV2P_CMD_SCHEDULER_ENABLE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) #define BNX2_MISC_LFSR_MASK_BITS_RSVD_FUTURE_ENABLE (0x7L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) #define BNX2_MISC_ARB_REQ0 0x0000082c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) #define BNX2_MISC_ARB_REQ1 0x00000830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) #define BNX2_MISC_ARB_REQ2 0x00000834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) #define BNX2_MISC_ARB_REQ3 0x00000838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) #define BNX2_MISC_ARB_REQ4 0x0000083c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) #define BNX2_MISC_ARB_FREE0 0x00000840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) #define BNX2_MISC_ARB_FREE1 0x00000844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) #define BNX2_MISC_ARB_FREE2 0x00000848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #define BNX2_MISC_ARB_FREE3 0x0000084c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) #define BNX2_MISC_ARB_FREE4 0x00000850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) #define BNX2_MISC_ARB_REQ_STATUS0 0x00000854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) #define BNX2_MISC_ARB_REQ_STATUS1 0x00000858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) #define BNX2_MISC_ARB_REQ_STATUS2 0x0000085c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) #define BNX2_MISC_ARB_REQ_STATUS3 0x00000860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #define BNX2_MISC_ARB_REQ_STATUS4 0x00000864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) #define BNX2_MISC_ARB_GNT0 0x00000868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) #define BNX2_MISC_ARB_GNT0_0 (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define BNX2_MISC_ARB_GNT0_1 (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define BNX2_MISC_ARB_GNT0_2 (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define BNX2_MISC_ARB_GNT0_3 (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) #define BNX2_MISC_ARB_GNT0_4 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) #define BNX2_MISC_ARB_GNT0_5 (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) #define BNX2_MISC_ARB_GNT0_6 (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) #define BNX2_MISC_ARB_GNT0_7 (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) #define BNX2_MISC_ARB_GNT1 0x0000086c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #define BNX2_MISC_ARB_GNT1_8 (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) #define BNX2_MISC_ARB_GNT1_9 (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define BNX2_MISC_ARB_GNT1_10 (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define BNX2_MISC_ARB_GNT1_11 (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) #define BNX2_MISC_ARB_GNT1_12 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) #define BNX2_MISC_ARB_GNT1_13 (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) #define BNX2_MISC_ARB_GNT1_14 (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) #define BNX2_MISC_ARB_GNT1_15 (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) #define BNX2_MISC_ARB_GNT2 0x00000870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #define BNX2_MISC_ARB_GNT2_16 (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) #define BNX2_MISC_ARB_GNT2_17 (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) #define BNX2_MISC_ARB_GNT2_18 (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) #define BNX2_MISC_ARB_GNT2_19 (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) #define BNX2_MISC_ARB_GNT2_20 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #define BNX2_MISC_ARB_GNT2_21 (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) #define BNX2_MISC_ARB_GNT2_22 (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #define BNX2_MISC_ARB_GNT2_23 (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) #define BNX2_MISC_ARB_GNT3 0x00000874
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) #define BNX2_MISC_ARB_GNT3_24 (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #define BNX2_MISC_ARB_GNT3_25 (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) #define BNX2_MISC_ARB_GNT3_26 (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #define BNX2_MISC_ARB_GNT3_27 (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) #define BNX2_MISC_ARB_GNT3_28 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) #define BNX2_MISC_ARB_GNT3_29 (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) #define BNX2_MISC_ARB_GNT3_30 (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) #define BNX2_MISC_ARB_GNT3_31 (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #define BNX2_MISC_RESERVED1 0x00000878
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) #define BNX2_MISC_RESERVED1_MISC_RESERVED1_VALUE (0x3fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #define BNX2_MISC_RESERVED2 0x0000087c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) #define BNX2_MISC_RESERVED2_PCIE_DIS (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #define BNX2_MISC_RESERVED2_LINK_IN_L23 (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) #define BNX2_MISC_SM_ASF_CONTROL 0x00000880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) #define BNX2_MISC_SM_ASF_CONTROL_ASF_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #define BNX2_MISC_SM_ASF_CONTROL_TSC_EN (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) #define BNX2_MISC_SM_ASF_CONTROL_WG_TO (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #define BNX2_MISC_SM_ASF_CONTROL_HB_TO (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) #define BNX2_MISC_SM_ASF_CONTROL_PA_TO (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) #define BNX2_MISC_SM_ASF_CONTROL_PL_TO (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #define BNX2_MISC_SM_ASF_CONTROL_RT_TO (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) #define BNX2_MISC_SM_ASF_CONTROL_SMB_EVENT (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_EN (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) #define BNX2_MISC_SM_ASF_CONTROL_STRETCH_PULSE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #define BNX2_MISC_SM_ASF_CONTROL_RES (0x3L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) #define BNX2_MISC_SM_ASF_CONTROL_SMB_EN (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #define BNX2_MISC_SM_ASF_CONTROL_SMB_BB_EN (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) #define BNX2_MISC_SM_ASF_CONTROL_SMB_NO_ADDR_FILT (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) #define BNX2_MISC_SM_ASF_CONTROL_SMB_AUTOREAD (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR1 (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #define BNX2_MISC_SM_ASF_CONTROL_NIC_SMB_ADDR2 (0x7fL<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) #define BNX2_MISC_SM_ASF_CONTROL_EN_NIC_SMB_ADDR_0 (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) #define BNX2_MISC_SM_ASF_CONTROL_SMB_EARLY_ATTN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) #define BNX2_MISC_SMB_IN 0x00000884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) #define BNX2_MISC_SMB_IN_DAT_IN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) #define BNX2_MISC_SMB_IN_RDY (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) #define BNX2_MISC_SMB_IN_DONE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) #define BNX2_MISC_SMB_IN_FIRSTBYTE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define BNX2_MISC_SMB_IN_STATUS (0x7L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) #define BNX2_MISC_SMB_IN_STATUS_OK (0x0L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) #define BNX2_MISC_SMB_IN_STATUS_PEC (0x1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) #define BNX2_MISC_SMB_IN_STATUS_OFLOW (0x2L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #define BNX2_MISC_SMB_IN_STATUS_STOP (0x3L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) #define BNX2_MISC_SMB_IN_STATUS_TIMEOUT (0x4L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #define BNX2_MISC_SMB_OUT 0x00000888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) #define BNX2_MISC_SMB_OUT_DAT_OUT (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) #define BNX2_MISC_SMB_OUT_RDY (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #define BNX2_MISC_SMB_OUT_START (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) #define BNX2_MISC_SMB_OUT_LAST (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) #define BNX2_MISC_SMB_OUT_ACC_TYPE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) #define BNX2_MISC_SMB_OUT_ENB_PEC (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) #define BNX2_MISC_SMB_OUT_GET_RX_LEN (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #define BNX2_MISC_SMB_OUT_SMB_READ_LEN (0x3fL<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_OK (0L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_NACK (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_UFLOW (2L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_STOP (3L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_TIMEOUT (4L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_FIRST_LOST (5L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_BADACK (6L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_NACK (9L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) #define BNX2_MISC_SMB_OUT_SMB_OUT_STATUS_SUB_LOST (0xdL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) #define BNX2_MISC_SMB_OUT_SMB_OUT_SLAVEMODE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_EN (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) #define BNX2_MISC_SMB_OUT_SMB_OUT_DAT_IN (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) #define BNX2_MISC_SMB_OUT_SMB_OUT_CLK_IN (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) #define BNX2_MISC_SMB_WATCHDOG 0x0000088c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) #define BNX2_MISC_SMB_WATCHDOG_WATCHDOG (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) #define BNX2_MISC_SMB_HEARTBEAT 0x00000890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) #define BNX2_MISC_SMB_HEARTBEAT_HEARTBEAT (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) #define BNX2_MISC_SMB_POLL_ASF 0x00000894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) #define BNX2_MISC_SMB_POLL_ASF_POLL_ASF (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) #define BNX2_MISC_SMB_POLL_LEGACY 0x00000898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) #define BNX2_MISC_SMB_POLL_LEGACY_POLL_LEGACY (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) #define BNX2_MISC_SMB_RETRAN 0x0000089c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) #define BNX2_MISC_SMB_RETRAN_RETRAN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) #define BNX2_MISC_SMB_TIMESTAMP 0x000008a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) #define BNX2_MISC_SMB_TIMESTAMP_TIMESTAMP (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #define BNX2_MISC_PERR_ENA0 0x000008a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) #define BNX2_MISC_PERR_ENA0_COM_MISC_CTXC (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) #define BNX2_MISC_PERR_ENA0_COM_MISC_REGF (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) #define BNX2_MISC_PERR_ENA0_COM_MISC_SCPAD (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) #define BNX2_MISC_PERR_ENA0_CP_MISC_CTXC (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) #define BNX2_MISC_PERR_ENA0_CP_MISC_REGF (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) #define BNX2_MISC_PERR_ENA0_CP_MISC_SCPAD (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) #define BNX2_MISC_PERR_ENA0_CS_MISC_TMEM (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM0 (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM1 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM2 (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM3 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM4 (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) #define BNX2_MISC_PERR_ENA0_CTX_MISC_ACCM5 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) #define BNX2_MISC_PERR_ENA0_CTX_MISC_PGTBL (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR0 (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR1 (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR2 (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR3 (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DR4 (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW0 (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW1 (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #define BNX2_MISC_PERR_ENA0_DMAE_MISC_DW2 (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) #define BNX2_MISC_PERR_ENA0_HC_MISC_DMA (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) #define BNX2_MISC_PERR_ENA0_MCP_MISC_REGF (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) #define BNX2_MISC_PERR_ENA0_MCP_MISC_SCPAD (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) #define BNX2_MISC_PERR_ENA0_MQ_MISC_CTX (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #define BNX2_MISC_PERR_ENA0_RBDC_MISC (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) #define BNX2_MISC_PERR_ENA0_RBUF_MISC_MB (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) #define BNX2_MISC_PERR_ENA0_RBUF_MISC_PTR (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPC (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) #define BNX2_MISC_PERR_ENA0_RDE_MISC_RPM (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) #define BNX2_MISC_PERR_ENA0_RV2P_MISC_CB0REGS (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #define BNX2_MISC_PERR_ENA0_COM_DMAE_PERR_EN_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) #define BNX2_MISC_PERR_ENA0_CP_DMAE_PERR_EN_XI (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) #define BNX2_MISC_PERR_ENA0_RPM_ACPIBEMEM_PERR_EN_XI (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #define BNX2_MISC_PERR_ENA0_CTX_USAGE_CNT_PERR_EN_XI (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define BNX2_MISC_PERR_ENA0_CTX_PGTBL_PERR_EN_XI (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define BNX2_MISC_PERR_ENA0_CTX_CACHE_PERR_EN_XI (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define BNX2_MISC_PERR_ENA0_CTX_MIRROR_PERR_EN_XI (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define BNX2_MISC_PERR_ENA0_COM_CTXC_PERR_EN_XI (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define BNX2_MISC_PERR_ENA0_COM_SCPAD_PERR_EN_XI (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define BNX2_MISC_PERR_ENA0_CP_CTXC_PERR_EN_XI (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define BNX2_MISC_PERR_ENA0_CP_SCPAD_PERR_EN_XI (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) #define BNX2_MISC_PERR_ENA0_RXP_RBUFC_PERR_EN_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #define BNX2_MISC_PERR_ENA0_RXP_CTXC_PERR_EN_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) #define BNX2_MISC_PERR_ENA0_RXP_SCPAD_PERR_EN_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) #define BNX2_MISC_PERR_ENA0_TPAT_SCPAD_PERR_EN_XI (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define BNX2_MISC_PERR_ENA0_TXP_CTXC_PERR_EN_XI (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define BNX2_MISC_PERR_ENA0_TXP_SCPAD_PERR_EN_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define BNX2_MISC_PERR_ENA0_CS_TMEM_PERR_EN_XI (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) #define BNX2_MISC_PERR_ENA0_MQ_CTX_PERR_EN_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) #define BNX2_MISC_PERR_ENA0_RPM_DFIFOMEM_PERR_EN_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) #define BNX2_MISC_PERR_ENA0_RPC_DFIFOMEM_PERR_EN_XI (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) #define BNX2_MISC_PERR_ENA0_RBUF_PTRMEM_PERR_EN_XI (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) #define BNX2_MISC_PERR_ENA0_RBUF_DATAMEM_PERR_EN_XI (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) #define BNX2_MISC_PERR_ENA0_RV2P_P2IRAM_PERR_EN_XI (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) #define BNX2_MISC_PERR_ENA0_RV2P_P1IRAM_PERR_EN_XI (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) #define BNX2_MISC_PERR_ENA0_RV2P_CB1REGS_PERR_EN_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) #define BNX2_MISC_PERR_ENA0_RV2P_CB0REGS_PERR_EN_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) #define BNX2_MISC_PERR_ENA0_TPBUF_PERR_EN_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) #define BNX2_MISC_PERR_ENA0_THBUF_PERR_EN_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) #define BNX2_MISC_PERR_ENA0_TDMA_PERR_EN_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #define BNX2_MISC_PERR_ENA0_TBDC_PERR_EN_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) #define BNX2_MISC_PERR_ENA0_TSCH_LR_PERR_EN_XI (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) #define BNX2_MISC_PERR_ENA1 0x000008a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) #define BNX2_MISC_PERR_ENA1_RV2P_MISC_CB1REGS (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P1IRAM (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) #define BNX2_MISC_PERR_ENA1_RV2P_MISC_P2IRAM (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) #define BNX2_MISC_PERR_ENA1_RXP_MISC_CTXC (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) #define BNX2_MISC_PERR_ENA1_RXP_MISC_REGF (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #define BNX2_MISC_PERR_ENA1_RXP_MISC_SCPAD (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) #define BNX2_MISC_PERR_ENA1_RXP_MISC_RBUFC (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) #define BNX2_MISC_PERR_ENA1_TBDC_MISC (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) #define BNX2_MISC_PERR_ENA1_TDMA_MISC (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB0 (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) #define BNX2_MISC_PERR_ENA1_THBUF_MISC_MB1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) #define BNX2_MISC_PERR_ENA1_TPAT_MISC_REGF (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #define BNX2_MISC_PERR_ENA1_TPAT_MISC_SCPAD (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) #define BNX2_MISC_PERR_ENA1_TPBUF_MISC_MB (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) #define BNX2_MISC_PERR_ENA1_TSCH_MISC_LR (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) #define BNX2_MISC_PERR_ENA1_TXP_MISC_CTXC (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) #define BNX2_MISC_PERR_ENA1_TXP_MISC_REGF (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) #define BNX2_MISC_PERR_ENA1_TXP_MISC_SCPAD (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIORX (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) #define BNX2_MISC_PERR_ENA1_UMP_MISC_FIOTX (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) #define BNX2_MISC_PERR_ENA1_UMP_MISC_RX (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) #define BNX2_MISC_PERR_ENA1_UMP_MISC_TX (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) #define BNX2_MISC_PERR_ENA1_RDMAQ_MISC (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) #define BNX2_MISC_PERR_ENA1_CSQ_MISC (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) #define BNX2_MISC_PERR_ENA1_CPQ_MISC (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) #define BNX2_MISC_PERR_ENA1_MCPQ_MISC (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) #define BNX2_MISC_PERR_ENA1_RV2PMQ_MISC (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #define BNX2_MISC_PERR_ENA1_RV2PPQ_MISC (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) #define BNX2_MISC_PERR_ENA1_RV2PTQ_MISC (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #define BNX2_MISC_PERR_ENA1_RXPQ_MISC (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) #define BNX2_MISC_PERR_ENA1_RXPCQ_MISC (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) #define BNX2_MISC_PERR_ENA1_RLUPQ_MISC (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #define BNX2_MISC_PERR_ENA1_RBDC_PERR_EN_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) #define BNX2_MISC_PERR_ENA1_RDMA_DFIFO_PERR_EN_XI (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) #define BNX2_MISC_PERR_ENA1_HC_STATS_PERR_EN_XI (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) #define BNX2_MISC_PERR_ENA1_HC_MSIX_PERR_EN_XI (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) #define BNX2_MISC_PERR_ENA1_HC_PRODUCSTB_PERR_EN_XI (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) #define BNX2_MISC_PERR_ENA1_HC_CONSUMSTB_PERR_EN_XI (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) #define BNX2_MISC_PERR_ENA1_TPATQ_PERR_EN_XI (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) #define BNX2_MISC_PERR_ENA1_MCPQ_PERR_EN_XI (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define BNX2_MISC_PERR_ENA1_TDMAQ_PERR_EN_XI (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define BNX2_MISC_PERR_ENA1_TXPQ_PERR_EN_XI (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define BNX2_MISC_PERR_ENA1_COMTQ_PERR_EN_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) #define BNX2_MISC_PERR_ENA1_COMQ_PERR_EN_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #define BNX2_MISC_PERR_ENA1_RLUPQ_PERR_EN_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define BNX2_MISC_PERR_ENA1_RXPQ_PERR_EN_XI (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #define BNX2_MISC_PERR_ENA1_RV2PPQ_PERR_EN_XI (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define BNX2_MISC_PERR_ENA1_RDMAQ_PERR_EN_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define BNX2_MISC_PERR_ENA1_TASQ_PERR_EN_XI (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define BNX2_MISC_PERR_ENA1_TBDRQ_PERR_EN_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define BNX2_MISC_PERR_ENA1_TSCHQ_PERR_EN_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define BNX2_MISC_PERR_ENA1_COMXQ_PERR_EN_XI (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define BNX2_MISC_PERR_ENA1_RXPCQ_PERR_EN_XI (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define BNX2_MISC_PERR_ENA1_RV2PTQ_PERR_EN_XI (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define BNX2_MISC_PERR_ENA1_RV2PMQ_PERR_EN_XI (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) #define BNX2_MISC_PERR_ENA1_CPQ_PERR_EN_XI (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) #define BNX2_MISC_PERR_ENA1_CSQ_PERR_EN_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) #define BNX2_MISC_PERR_ENA1_RLUP_CID_PERR_EN_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) #define BNX2_MISC_PERR_ENA1_RV2PCS_TMEM_PERR_EN_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define BNX2_MISC_PERR_ENA1_RV2PCSQ_PERR_EN_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) #define BNX2_MISC_PERR_ENA1_MQ_IDX_PERR_EN_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) #define BNX2_MISC_PERR_ENA2 0x000008ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) #define BNX2_MISC_PERR_ENA2_COMQ_MISC (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) #define BNX2_MISC_PERR_ENA2_COMXQ_MISC (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) #define BNX2_MISC_PERR_ENA2_COMTQ_MISC (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) #define BNX2_MISC_PERR_ENA2_TSCHQ_MISC (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) #define BNX2_MISC_PERR_ENA2_TBDRQ_MISC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) #define BNX2_MISC_PERR_ENA2_TXPQ_MISC (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) #define BNX2_MISC_PERR_ENA2_TDMAQ_MISC (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) #define BNX2_MISC_PERR_ENA2_TPATQ_MISC (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) #define BNX2_MISC_PERR_ENA2_TASQ_MISC (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) #define BNX2_MISC_PERR_ENA2_TGT_FIFO_PERR_EN_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) #define BNX2_MISC_PERR_ENA2_UMP_TX_PERR_EN_XI (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) #define BNX2_MISC_PERR_ENA2_UMP_RX_PERR_EN_XI (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) #define BNX2_MISC_PERR_ENA2_MCP_ROM_PERR_EN_XI (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) #define BNX2_MISC_PERR_ENA2_MCP_SCPAD_PERR_EN_XI (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) #define BNX2_MISC_PERR_ENA2_HB_MEM_PERR_EN_XI (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #define BNX2_MISC_PERR_ENA2_PCIE_REPLAY_PERR_EN_XI (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) #define BNX2_MISC_DEBUG_VECTOR_SEL 0x000008b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) #define BNX2_MISC_DEBUG_VECTOR_SEL_0 (0xfffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) #define BNX2_MISC_DEBUG_VECTOR_SEL_1 (0xfffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) #define BNX2_MISC_DEBUG_VECTOR_SEL_1_XI (0xfffL<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) #define BNX2_MISC_VREG_CONTROL 0x000008b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) #define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) #define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) #define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) #define BNX2_MISC_VREG_CONTROL_2_5_NOM (7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) #define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) #define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) #define BNX2_MISC_FINAL_CLK_CTL_VAL 0x000008b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) #define BNX2_MISC_FINAL_CLK_CTL_VAL_MISC_FINAL_CLK_CTL_VAL (0x3ffffffL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #define BNX2_MISC_GP_HW_CTL0 0x000008bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) #define BNX2_MISC_GP_HW_CTL0_TX_DRIVE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) #define BNX2_MISC_GP_HW_CTL0_RMII_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) #define BNX2_MISC_GP_HW_CTL0_RMII_CRSDV_SEL (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) #define BNX2_MISC_GP_HW_CTL0_RVMII_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) #define BNX2_MISC_GP_HW_CTL0_FLASH_SAMP_SCLK_NEGEDGE_TE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) #define BNX2_MISC_GP_HW_CTL0_HIDDEN_REVISION_ID_TE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) #define BNX2_MISC_GP_HW_CTL0_HC_CNTL_TMOUT_CTR_RST_TE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) #define BNX2_MISC_GP_HW_CTL0_RESERVED1_XI (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) #define BNX2_MISC_GP_HW_CTL0_ENA_CORE_RST_ON_MAIN_PWR_GOING_AWAY (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) #define BNX2_MISC_GP_HW_CTL0_ENA_SEL_VAUX_B_IN_L2_TE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) #define BNX2_MISC_GP_HW_CTL0_GRC_BNK_FREE_FIX_TE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) #define BNX2_MISC_GP_HW_CTL0_LED_ACT_SEL_TE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) #define BNX2_MISC_GP_HW_CTL0_RESERVED2_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) #define BNX2_MISC_GP_HW_CTL0_UP1_DEF0 (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) #define BNX2_MISC_GP_HW_CTL0_FIBER_MODE_DIS_DEF (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) #define BNX2_MISC_GP_HW_CTL0_FORCE2500_DEF (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) #define BNX2_MISC_GP_HW_CTL0_AUTODETECT_DIS_DEF (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) #define BNX2_MISC_GP_HW_CTL0_PARALLEL_DETECT_DEF (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_3MA (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P5MA (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_2P0MA (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P5MA (5L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_1P0MA (7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_DAI_PWRDN (15L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE2DIS (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PRE1DIS (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT (0x3L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M6P (0L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_M0P (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P0P (2L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_CTAT_P6P (3L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT (0x3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M6P (0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_M0P (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P0P (2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_PTAT_P6P (3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_240UA (0L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_160UA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_400UA (2L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_IAMP_ADJ_320UA (3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ (0x3L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_240UA (0L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_160UA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_400UA (2L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_ICBUF_ADJ_320UA (3L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ (0x3L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P57 (0L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P45 (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P62 (2L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define BNX2_MISC_GP_HW_CTL0_OSCCTRL_XTAL_ADJ_1P66 (3L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define BNX2_MISC_GP_HW_CTL1 0x000008c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define BNX2_MISC_GP_HW_CTL1_1_ATTN_BTN_PRSNT_TE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define BNX2_MISC_GP_HW_CTL1_1_ATTN_IND_PRSNT_TE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define BNX2_MISC_GP_HW_CTL1_1_PWR_IND_PRSNT_TE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define BNX2_MISC_GP_HW_CTL1_0_PCIE_LOOPBACK_TE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define BNX2_MISC_GP_HW_CTL1_RESERVED_SOFT_XI (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define BNX2_MISC_GP_HW_CTL1_RESERVED_HARD_XI (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define BNX2_MISC_NEW_HW_CTL 0x000008c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define BNX2_MISC_NEW_HW_CTL_MAIN_POR_BYPASS (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define BNX2_MISC_NEW_HW_CTL_RINGOSC_ENABLE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL0 (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define BNX2_MISC_NEW_HW_CTL_RINGOSC_SEL1 (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) #define BNX2_MISC_NEW_HW_CTL_RESERVED_SHARED (0xfffL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define BNX2_MISC_NEW_HW_CTL_RESERVED_SPLIT (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define BNX2_MISC_NEW_CORE_CTL 0x000008c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_SUCCESS (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) #define BNX2_MISC_NEW_CORE_CTL_LINK_HOLDOFF_REQ (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) #define BNX2_MISC_NEW_CORE_CTL_DMA_ENABLE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) #define BNX2_MISC_NEW_CORE_CTL_RESERVED_CMN (0x3fffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) #define BNX2_MISC_NEW_CORE_CTL_RESERVED_TC (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) #define BNX2_MISC_ECO_HW_CTL 0x000008cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) #define BNX2_MISC_ECO_HW_CTL_LARGE_GRC_TMOUT_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) #define BNX2_MISC_ECO_HW_CTL_RESERVED_SOFT (0x7fffL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) #define BNX2_MISC_ECO_HW_CTL_RESERVED_HARD (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) #define BNX2_MISC_ECO_CORE_CTL 0x000008d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) #define BNX2_MISC_ECO_CORE_CTL_RESERVED_SOFT (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) #define BNX2_MISC_ECO_CORE_CTL_RESERVED_HARD (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) #define BNX2_MISC_PPIO 0x000008d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) #define BNX2_MISC_PPIO_VALUE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) #define BNX2_MISC_PPIO_SET (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) #define BNX2_MISC_PPIO_CLR (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) #define BNX2_MISC_PPIO_FLOAT (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) #define BNX2_MISC_PPIO_INT 0x000008d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) #define BNX2_MISC_PPIO_INT_INT_STATE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) #define BNX2_MISC_PPIO_INT_OLD_VALUE (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) #define BNX2_MISC_PPIO_INT_OLD_SET (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) #define BNX2_MISC_PPIO_INT_OLD_CLR (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) #define BNX2_MISC_RESET_NUMS 0x000008dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) #define BNX2_MISC_RESET_NUMS_NUM_HARD_RESETS (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) #define BNX2_MISC_RESET_NUMS_NUM_PCIE_RESETS (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) #define BNX2_MISC_RESET_NUMS_NUM_PERSTB_RESETS (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) #define BNX2_MISC_RESET_NUMS_NUM_CMN_RESETS (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) #define BNX2_MISC_RESET_NUMS_NUM_PORT_RESETS (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) #define BNX2_MISC_CS16_ERR 0x000008e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) #define BNX2_MISC_CS16_ERR_ENA_PCI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) #define BNX2_MISC_CS16_ERR_ENA_RDMA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) #define BNX2_MISC_CS16_ERR_ENA_TDMA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) #define BNX2_MISC_CS16_ERR_ENA_EMAC (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) #define BNX2_MISC_CS16_ERR_ENA_CTX (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) #define BNX2_MISC_CS16_ERR_ENA_TBDR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) #define BNX2_MISC_CS16_ERR_ENA_RBDC (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) #define BNX2_MISC_CS16_ERR_ENA_COM (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) #define BNX2_MISC_CS16_ERR_ENA_CP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) #define BNX2_MISC_CS16_ERR_STA_PCI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) #define BNX2_MISC_CS16_ERR_STA_RDMA (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) #define BNX2_MISC_CS16_ERR_STA_TDMA (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) #define BNX2_MISC_CS16_ERR_STA_EMAC (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) #define BNX2_MISC_CS16_ERR_STA_CTX (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) #define BNX2_MISC_CS16_ERR_STA_TBDR (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) #define BNX2_MISC_CS16_ERR_STA_RBDC (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) #define BNX2_MISC_CS16_ERR_STA_COM (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) #define BNX2_MISC_CS16_ERR_STA_CP (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) #define BNX2_MISC_SPIO_EVENT 0x000008e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #define BNX2_MISC_SPIO_EVENT_ENABLE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) #define BNX2_MISC_PPIO_EVENT 0x000008e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) #define BNX2_MISC_PPIO_EVENT_ENABLE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) #define BNX2_MISC_DUAL_MEDIA_CTRL 0x000008ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_X (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_C (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) #define BNX2_MISC_DUAL_MEDIA_CTRL_BOND_ID_S (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP_PIN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_SIGDET (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_SIGDET (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_SIGDET (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_SIGDET (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) #define BNX2_MISC_DUAL_MEDIA_CTRL_LCPLL_RST (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES1_RST (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) #define BNX2_MISC_DUAL_MEDIA_CTRL_SERDES0_RST (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY1_RST (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY0_RST (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_CTRL (0x7L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) #define BNX2_MISC_DUAL_MEDIA_CTRL_PORT_SWAP (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) #define BNX2_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ (0xfL<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER1_IDDQ (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_SER0_IDDQ (2L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY1_IDDQ (4L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) #define BNX2_MISC_DUAL_MEDIA_CTRL_PHY_SERDES_IDDQ_PHY0_IDDQ (8L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) #define BNX2_MISC_OTP_CMD1 0x000008f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) #define BNX2_MISC_OTP_CMD1_FMODE (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) #define BNX2_MISC_OTP_CMD1_FMODE_IDLE (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) #define BNX2_MISC_OTP_CMD1_FMODE_WRITE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) #define BNX2_MISC_OTP_CMD1_FMODE_INIT (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) #define BNX2_MISC_OTP_CMD1_FMODE_SET (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) #define BNX2_MISC_OTP_CMD1_FMODE_RST (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) #define BNX2_MISC_OTP_CMD1_FMODE_VERIFY (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED0 (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) #define BNX2_MISC_OTP_CMD1_FMODE_RESERVED1 (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) #define BNX2_MISC_OTP_CMD1_USEPINS (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) #define BNX2_MISC_OTP_CMD1_PROGSEL (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) #define BNX2_MISC_OTP_CMD1_PROGSTART (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) #define BNX2_MISC_OTP_CMD1_PCOUNT (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) #define BNX2_MISC_OTP_CMD1_PBYP (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) #define BNX2_MISC_OTP_CMD1_VSEL (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) #define BNX2_MISC_OTP_CMD1_TM (0x7L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) #define BNX2_MISC_OTP_CMD1_SADBYP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) #define BNX2_MISC_OTP_CMD1_DEBUG (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) #define BNX2_MISC_OTP_CMD2 0x000008f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) #define BNX2_MISC_OTP_CMD2_OTP_ROM_ADDR (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) #define BNX2_MISC_OTP_CMD2_DOSEL (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) #define BNX2_MISC_OTP_CMD2_DOSEL_0 (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) #define BNX2_MISC_OTP_CMD2_DOSEL_1 (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) #define BNX2_MISC_OTP_CMD2_DOSEL_127 (127L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) #define BNX2_MISC_OTP_STATUS 0x000008f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) #define BNX2_MISC_OTP_STATUS_DATA (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) #define BNX2_MISC_OTP_STATUS_VALID (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) #define BNX2_MISC_OTP_STATUS_BUSY (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) #define BNX2_MISC_OTP_STATUS_BUSYSM (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) #define BNX2_MISC_OTP_STATUS_DONE (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #define BNX2_MISC_OTP_SHIFT1_CMD 0x000008fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) #define BNX2_MISC_OTP_SHIFT1_CMD_RESET_MODE_N (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_DONE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_START (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) #define BNX2_MISC_OTP_SHIFT1_CMD_LOAD_DATA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) #define BNX2_MISC_OTP_SHIFT1_CMD_SHIFT_SELECT (0x1fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) #define BNX2_MISC_OTP_SHIFT1_DATA 0x00000900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) #define BNX2_MISC_OTP_SHIFT2_CMD 0x00000904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) #define BNX2_MISC_OTP_SHIFT2_CMD_RESET_MODE_N (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_DONE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_START (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) #define BNX2_MISC_OTP_SHIFT2_CMD_LOAD_DATA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) #define BNX2_MISC_OTP_SHIFT2_CMD_SHIFT_SELECT (0x1fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #define BNX2_MISC_OTP_SHIFT2_DATA 0x00000908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) #define BNX2_MISC_BIST_CS0 0x0000090c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) #define BNX2_MISC_BIST_CS0_MBIST_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) #define BNX2_MISC_BIST_CS0_BIST_SETUP (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) #define BNX2_MISC_BIST_CS0_MBIST_ASYNC_RESET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) #define BNX2_MISC_BIST_CS0_MBIST_DONE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) #define BNX2_MISC_BIST_CS0_MBIST_GO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) #define BNX2_MISC_BIST_CS0_BIST_OVERRIDE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) #define BNX2_MISC_BIST_MEMSTATUS0 0x00000910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) #define BNX2_MISC_BIST_CS1 0x00000914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) #define BNX2_MISC_BIST_CS1_MBIST_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) #define BNX2_MISC_BIST_CS1_BIST_SETUP (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) #define BNX2_MISC_BIST_CS1_MBIST_ASYNC_RESET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) #define BNX2_MISC_BIST_CS1_MBIST_DONE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) #define BNX2_MISC_BIST_CS1_MBIST_GO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) #define BNX2_MISC_BIST_MEMSTATUS1 0x00000918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) #define BNX2_MISC_BIST_CS2 0x0000091c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) #define BNX2_MISC_BIST_CS2_MBIST_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) #define BNX2_MISC_BIST_CS2_BIST_SETUP (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) #define BNX2_MISC_BIST_CS2_MBIST_ASYNC_RESET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) #define BNX2_MISC_BIST_CS2_MBIST_DONE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) #define BNX2_MISC_BIST_CS2_MBIST_GO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) #define BNX2_MISC_BIST_MEMSTATUS2 0x00000920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) #define BNX2_MISC_BIST_CS3 0x00000924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) #define BNX2_MISC_BIST_CS3_MBIST_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) #define BNX2_MISC_BIST_CS3_BIST_SETUP (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) #define BNX2_MISC_BIST_CS3_MBIST_ASYNC_RESET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) #define BNX2_MISC_BIST_CS3_MBIST_DONE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #define BNX2_MISC_BIST_CS3_MBIST_GO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) #define BNX2_MISC_BIST_MEMSTATUS3 0x00000928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) #define BNX2_MISC_BIST_CS4 0x0000092c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) #define BNX2_MISC_BIST_CS4_MBIST_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) #define BNX2_MISC_BIST_CS4_BIST_SETUP (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) #define BNX2_MISC_BIST_CS4_MBIST_ASYNC_RESET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) #define BNX2_MISC_BIST_CS4_MBIST_DONE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) #define BNX2_MISC_BIST_CS4_MBIST_GO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) #define BNX2_MISC_BIST_MEMSTATUS4 0x00000930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #define BNX2_MISC_BIST_CS5 0x00000934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) #define BNX2_MISC_BIST_CS5_MBIST_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #define BNX2_MISC_BIST_CS5_BIST_SETUP (0x3L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) #define BNX2_MISC_BIST_CS5_MBIST_ASYNC_RESET (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) #define BNX2_MISC_BIST_CS5_MBIST_DONE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) #define BNX2_MISC_BIST_CS5_MBIST_GO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) #define BNX2_MISC_BIST_MEMSTATUS5 0x00000938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) #define BNX2_MISC_MEM_TM0 0x0000093c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) #define BNX2_MISC_MEM_TM0_PCIE_REPLAY_TM (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) #define BNX2_MISC_MEM_TM0_MCP_SCPAD (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) #define BNX2_MISC_MEM_TM0_UMP_TM (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) #define BNX2_MISC_MEM_TM0_HB_MEM_TM (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) #define BNX2_MISC_USPLL_CTRL 0x00000940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) #define BNX2_MISC_USPLL_CTRL_PH_DET_DIS (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) #define BNX2_MISC_USPLL_CTRL_FREQ_DET_DIS (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) #define BNX2_MISC_USPLL_CTRL_LCPX (0x3fL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) #define BNX2_MISC_USPLL_CTRL_RX (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) #define BNX2_MISC_USPLL_CTRL_VC_EN (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) #define BNX2_MISC_USPLL_CTRL_VCO_MG (0x3L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) #define BNX2_MISC_USPLL_CTRL_KVCO_XF (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) #define BNX2_MISC_USPLL_CTRL_KVCO_XS (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) #define BNX2_MISC_USPLL_CTRL_TESTD_EN (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) #define BNX2_MISC_USPLL_CTRL_TESTD_SEL (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) #define BNX2_MISC_USPLL_CTRL_TESTA_EN (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) #define BNX2_MISC_USPLL_CTRL_TESTA_SEL (0x3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) #define BNX2_MISC_USPLL_CTRL_ATTEN_FREF (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) #define BNX2_MISC_USPLL_CTRL_DIGITAL_RST (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) #define BNX2_MISC_USPLL_CTRL_ANALOG_RST (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) #define BNX2_MISC_USPLL_CTRL_LOCK (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) #define BNX2_MISC_PERR_STATUS0 0x00000944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) #define BNX2_MISC_PERR_STATUS0_COM_DMAE_PERR (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) #define BNX2_MISC_PERR_STATUS0_CP_DMAE_PERR (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) #define BNX2_MISC_PERR_STATUS0_RPM_ACPIBEMEM_PERR (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) #define BNX2_MISC_PERR_STATUS0_CTX_USAGE_CNT_PERR (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) #define BNX2_MISC_PERR_STATUS0_CTX_PGTBL_PERR (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) #define BNX2_MISC_PERR_STATUS0_CTX_CACHE_PERR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) #define BNX2_MISC_PERR_STATUS0_CTX_MIRROR_PERR (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) #define BNX2_MISC_PERR_STATUS0_COM_CTXC_PERR (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) #define BNX2_MISC_PERR_STATUS0_COM_SCPAD_PERR (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) #define BNX2_MISC_PERR_STATUS0_CP_CTXC_PERR (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) #define BNX2_MISC_PERR_STATUS0_CP_SCPAD_PERR (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) #define BNX2_MISC_PERR_STATUS0_RXP_RBUFC_PERR (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) #define BNX2_MISC_PERR_STATUS0_RXP_CTXC_PERR (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) #define BNX2_MISC_PERR_STATUS0_RXP_SCPAD_PERR (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) #define BNX2_MISC_PERR_STATUS0_TPAT_SCPAD_PERR (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) #define BNX2_MISC_PERR_STATUS0_TXP_CTXC_PERR (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) #define BNX2_MISC_PERR_STATUS0_TXP_SCPAD_PERR (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) #define BNX2_MISC_PERR_STATUS0_CS_TMEM_PERR (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) #define BNX2_MISC_PERR_STATUS0_MQ_CTX_PERR (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) #define BNX2_MISC_PERR_STATUS0_RPM_DFIFOMEM_PERR (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) #define BNX2_MISC_PERR_STATUS0_RPC_DFIFOMEM_PERR (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) #define BNX2_MISC_PERR_STATUS0_RBUF_PTRMEM_PERR (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) #define BNX2_MISC_PERR_STATUS0_RBUF_DATAMEM_PERR (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) #define BNX2_MISC_PERR_STATUS0_RV2P_P2IRAM_PERR (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) #define BNX2_MISC_PERR_STATUS0_RV2P_P1IRAM_PERR (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) #define BNX2_MISC_PERR_STATUS0_RV2P_CB1REGS_PERR (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) #define BNX2_MISC_PERR_STATUS0_RV2P_CB0REGS_PERR (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) #define BNX2_MISC_PERR_STATUS0_TPBUF_PERR (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) #define BNX2_MISC_PERR_STATUS0_THBUF_PERR (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) #define BNX2_MISC_PERR_STATUS0_TDMA_PERR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) #define BNX2_MISC_PERR_STATUS0_TBDC_PERR (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) #define BNX2_MISC_PERR_STATUS0_TSCH_LR_PERR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) #define BNX2_MISC_PERR_STATUS1 0x00000948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) #define BNX2_MISC_PERR_STATUS1_RBDC_PERR (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) #define BNX2_MISC_PERR_STATUS1_RDMA_DFIFO_PERR (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) #define BNX2_MISC_PERR_STATUS1_HC_STATS_PERR (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) #define BNX2_MISC_PERR_STATUS1_HC_MSIX_PERR (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) #define BNX2_MISC_PERR_STATUS1_HC_PRODUCSTB_PERR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) #define BNX2_MISC_PERR_STATUS1_HC_CONSUMSTB_PERR (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) #define BNX2_MISC_PERR_STATUS1_TPATQ_PERR (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) #define BNX2_MISC_PERR_STATUS1_MCPQ_PERR (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) #define BNX2_MISC_PERR_STATUS1_TDMAQ_PERR (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) #define BNX2_MISC_PERR_STATUS1_TXPQ_PERR (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) #define BNX2_MISC_PERR_STATUS1_COMTQ_PERR (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) #define BNX2_MISC_PERR_STATUS1_COMQ_PERR (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) #define BNX2_MISC_PERR_STATUS1_RLUPQ_PERR (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) #define BNX2_MISC_PERR_STATUS1_RXPQ_PERR (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) #define BNX2_MISC_PERR_STATUS1_RV2PPQ_PERR (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define BNX2_MISC_PERR_STATUS1_RDMAQ_PERR (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define BNX2_MISC_PERR_STATUS1_TASQ_PERR (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define BNX2_MISC_PERR_STATUS1_TBDRQ_PERR (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define BNX2_MISC_PERR_STATUS1_TSCHQ_PERR (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) #define BNX2_MISC_PERR_STATUS1_COMXQ_PERR (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) #define BNX2_MISC_PERR_STATUS1_RXPCQ_PERR (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) #define BNX2_MISC_PERR_STATUS1_RV2PTQ_PERR (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) #define BNX2_MISC_PERR_STATUS1_RV2PMQ_PERR (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) #define BNX2_MISC_PERR_STATUS1_CPQ_PERR (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) #define BNX2_MISC_PERR_STATUS1_CSQ_PERR (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) #define BNX2_MISC_PERR_STATUS1_RLUP_CID_PERR (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) #define BNX2_MISC_PERR_STATUS1_RV2PCS_TMEM_PERR (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) #define BNX2_MISC_PERR_STATUS1_RV2PCSQ_PERR (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) #define BNX2_MISC_PERR_STATUS1_MQ_IDX_PERR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) #define BNX2_MISC_PERR_STATUS2 0x0000094c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) #define BNX2_MISC_PERR_STATUS2_TGT_FIFO_PERR (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) #define BNX2_MISC_PERR_STATUS2_UMP_TX_PERR (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) #define BNX2_MISC_PERR_STATUS2_UMP_RX_PERR (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) #define BNX2_MISC_PERR_STATUS2_MCP_ROM_PERR (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) #define BNX2_MISC_PERR_STATUS2_MCP_SCPAD_PERR (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) #define BNX2_MISC_PERR_STATUS2_HB_MEM_PERR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #define BNX2_MISC_PERR_STATUS2_PCIE_REPLAY_PERR (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) #define BNX2_MISC_LCPLL_CTRL0 0x00000950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #define BNX2_MISC_LCPLL_CTRL0_OAC (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) #define BNX2_MISC_LCPLL_CTRL0_OAC_NEGTWENTY (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) #define BNX2_MISC_LCPLL_CTRL0_OAC_ZERO (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) #define BNX2_MISC_LCPLL_CTRL0_OAC_TWENTY (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) #define BNX2_MISC_LCPLL_CTRL0_OAC_FORTY (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL (0x7L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_360 (0L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_480 (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_600 (3L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) #define BNX2_MISC_LCPLL_CTRL0_ICP_CTRL_720 (7L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) #define BNX2_MISC_LCPLL_CTRL0_BIAS_CTRL (0x3L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) #define BNX2_MISC_LCPLL_CTRL0_PLL_OBSERVE (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL (0x3L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_0 (0L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_1 (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) #define BNX2_MISC_LCPLL_CTRL0_VTH_CTRL_2 (2L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) #define BNX2_MISC_LCPLL_CTRL0_PLLSEQSTART (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) #define BNX2_MISC_LCPLL_CTRL0_RESERVED (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) #define BNX2_MISC_LCPLL_CTRL0_CAPRETRY_EN (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) #define BNX2_MISC_LCPLL_CTRL0_FREQMONITOR_EN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) #define BNX2_MISC_LCPLL_CTRL0_FREQDETRESTART_EN (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) #define BNX2_MISC_LCPLL_CTRL0_FREQDETRETRY_EN (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE_EN (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFDONE (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCEFPASS (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE_EN (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPDONE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS_EN (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) #define BNX2_MISC_LCPLL_CTRL0_PLLFORCECAPPASS (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) #define BNX2_MISC_LCPLL_CTRL0_CAPRESTART (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) #define BNX2_MISC_LCPLL_CTRL0_CAPSELECTM_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) #define BNX2_MISC_LCPLL_CTRL1 0x00000954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) #define BNX2_MISC_LCPLL_CTRL1_CAPSELECTM (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN_EN (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) #define BNX2_MISC_LCPLL_CTRL1_CAPFORCESLOWDOWN (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) #define BNX2_MISC_LCPLL_CTRL1_SLOWDN_XOR (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) #define BNX2_MISC_LCPLL_STATUS 0x00000958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) #define BNX2_MISC_LCPLL_STATUS_FREQDONE_SM (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) #define BNX2_MISC_LCPLL_STATUS_FREQPASS_SM (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) #define BNX2_MISC_LCPLL_STATUS_PLLSEQDONE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) #define BNX2_MISC_LCPLL_STATUS_PLLSEQPASS (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) #define BNX2_MISC_LCPLL_STATUS_PLLSTATE (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) #define BNX2_MISC_LCPLL_STATUS_CAPSTATE (0x7L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) #define BNX2_MISC_LCPLL_STATUS_CAPSELECT (0x1fL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_0 (0L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) #define BNX2_MISC_LCPLL_STATUS_SLOWDN_INDICATOR_1 (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) #define BNX2_MISC_OSCFUNDS_CTRL 0x0000095c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_OFF (0L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) #define BNX2_MISC_OSCFUNDS_CTRL_FREQ_MON_ON (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM (0x3L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_0 (0L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_2 (2L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) #define BNX2_MISC_OSCFUNDS_CTRL_XTAL_ADJCM_3 (3L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_0 (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_1 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_2 (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) #define BNX2_MISC_OSCFUNDS_CTRL_ICBUF_ADJ_3 (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ (0x3L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_2 (2L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) #define BNX2_MISC_OSCFUNDS_CTRL_IAMP_ADJ_3 (3L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) * nvm_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) * offset: 0x6400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) #define BNX2_NVM_COMMAND 0x00006400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) #define BNX2_NVM_COMMAND_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) #define BNX2_NVM_COMMAND_DONE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) #define BNX2_NVM_COMMAND_DOIT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) #define BNX2_NVM_COMMAND_WR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) #define BNX2_NVM_COMMAND_ERASE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) #define BNX2_NVM_COMMAND_FIRST (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) #define BNX2_NVM_COMMAND_LAST (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) #define BNX2_NVM_COMMAND_WREN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) #define BNX2_NVM_COMMAND_WRDI (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) #define BNX2_NVM_COMMAND_EWSR (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) #define BNX2_NVM_COMMAND_WRSR (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) #define BNX2_NVM_COMMAND_RD_ID (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) #define BNX2_NVM_COMMAND_RD_STATUS (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) #define BNX2_NVM_COMMAND_MODE_256 (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) #define BNX2_NVM_STATUS 0x00006404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) #define BNX2_NVM_STATUS_PI_FSM_STATE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) #define BNX2_NVM_STATUS_EE_FSM_STATE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) #define BNX2_NVM_STATUS_EQ_FSM_STATE (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) #define BNX2_NVM_STATUS_SPI_FSM_STATE_XI (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_IDLE_XI (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD0_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD1_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH0_XI (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CMD_FINISH1_XI (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ADDR0_XI (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA0_XI (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA1_XI (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WRITE_DATA2_XI (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA0_XI (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA1_XI (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_DATA2_XI (11L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID0_XI (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID1_XI (13L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID2_XI (14L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID3_XI (15L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_READ_STATUS_RDID4_XI (16L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_CHECK_BUSY0_XI (17L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_ST_WREN_XI (18L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) #define BNX2_NVM_STATUS_SPI_FSM_STATE_SPI_WAIT_XI (19L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) #define BNX2_NVM_WRITE 0x00006408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_BIT_BANG (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EECLK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_EEDATA (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO (16L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI (32L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SI_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SO_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_CS_B_XI (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) #define BNX2_NVM_WRITE_NVM_WRITE_VALUE_SCLK_XI (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) #define BNX2_NVM_ADDR 0x0000640c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE (0xffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_BIT_BANG (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EECLK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_EEDATA (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO (16L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI (32L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SI_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SO_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_CS_B_XI (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) #define BNX2_NVM_ADDR_NVM_ADDR_VALUE_SCLK_XI (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) #define BNX2_NVM_READ 0x00006410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) #define BNX2_NVM_READ_NVM_READ_VALUE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) #define BNX2_NVM_READ_NVM_READ_VALUE_BIT_BANG (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) #define BNX2_NVM_READ_NVM_READ_VALUE_EECLK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) #define BNX2_NVM_READ_NVM_READ_VALUE_EEDATA (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) #define BNX2_NVM_READ_NVM_READ_VALUE_SO (16L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) #define BNX2_NVM_READ_NVM_READ_VALUE_SI (32L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) #define BNX2_NVM_READ_NVM_READ_VALUE_SI_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) #define BNX2_NVM_READ_NVM_READ_VALUE_SO_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) #define BNX2_NVM_READ_NVM_READ_VALUE_CS_B_XI (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #define BNX2_NVM_READ_NVM_READ_VALUE_SCLK_XI (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) #define BNX2_NVM_CFG1 0x00006414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) #define BNX2_NVM_CFG1_FLASH_MODE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) #define BNX2_NVM_CFG1_BUFFER_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) #define BNX2_NVM_CFG1_PASS_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) #define BNX2_NVM_CFG1_BITBANG_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) #define BNX2_NVM_CFG1_STATUS_BIT (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) #define BNX2_NVM_CFG1_STATUS_BIT_FLASH_RDY (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) #define BNX2_NVM_CFG1_STATUS_BIT_BUFFER_RDY (7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) #define BNX2_NVM_CFG1_SPI_CLK_DIV (0xfL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) #define BNX2_NVM_CFG1_SEE_CLK_DIV (0x7ffL<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) #define BNX2_NVM_CFG1_STRAP_CONTROL_0 (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) #define BNX2_NVM_CFG1_PROTECT_MODE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) #define BNX2_NVM_CFG1_FLASH_SIZE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) #define BNX2_NVM_CFG1_FW_USTRAP_1 (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) #define BNX2_NVM_CFG1_FW_USTRAP_0 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) #define BNX2_NVM_CFG1_FW_USTRAP_2 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) #define BNX2_NVM_CFG1_FW_USTRAP_3 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) #define BNX2_NVM_CFG1_FW_FLASH_TYPE_EN (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) #define BNX2_NVM_CFG1_COMPAT_BYPASSS (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) #define BNX2_NVM_CFG2 0x00006418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #define BNX2_NVM_CFG2_ERASE_CMD (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) #define BNX2_NVM_CFG2_DUMMY (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) #define BNX2_NVM_CFG2_STATUS_CMD (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) #define BNX2_NVM_CFG2_READ_ID (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) #define BNX2_NVM_CFG3 0x0000641c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) #define BNX2_NVM_CFG3_BUFFER_RD_CMD (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) #define BNX2_NVM_CFG3_WRITE_CMD (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) #define BNX2_NVM_CFG3_BUFFER_WRITE_CMD (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) #define BNX2_NVM_CFG3_READ_CMD (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) #define BNX2_NVM_SW_ARB 0x00006420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) #define BNX2_NVM_SW_ARB_ARB_REQ_SET0 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) #define BNX2_NVM_SW_ARB_ARB_REQ_SET1 (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) #define BNX2_NVM_SW_ARB_ARB_REQ_SET2 (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) #define BNX2_NVM_SW_ARB_ARB_REQ_SET3 (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) #define BNX2_NVM_SW_ARB_ARB_REQ_CLR0 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) #define BNX2_NVM_SW_ARB_ARB_REQ_CLR1 (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) #define BNX2_NVM_SW_ARB_ARB_REQ_CLR2 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) #define BNX2_NVM_SW_ARB_ARB_REQ_CLR3 (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) #define BNX2_NVM_SW_ARB_ARB_ARB0 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) #define BNX2_NVM_SW_ARB_ARB_ARB1 (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) #define BNX2_NVM_SW_ARB_ARB_ARB2 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) #define BNX2_NVM_SW_ARB_ARB_ARB3 (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) #define BNX2_NVM_SW_ARB_REQ0 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) #define BNX2_NVM_SW_ARB_REQ1 (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) #define BNX2_NVM_SW_ARB_REQ2 (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) #define BNX2_NVM_SW_ARB_REQ3 (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) #define BNX2_NVM_ACCESS_ENABLE 0x00006424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) #define BNX2_NVM_ACCESS_ENABLE_EN (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) #define BNX2_NVM_ACCESS_ENABLE_WR_EN (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) #define BNX2_NVM_WRITE1 0x00006428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) #define BNX2_NVM_WRITE1_WREN_CMD (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) #define BNX2_NVM_WRITE1_WRDI_CMD (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) #define BNX2_NVM_WRITE1_SR_DATA (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) #define BNX2_NVM_CFG4 0x0000642c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) #define BNX2_NVM_CFG4_FLASH_SIZE (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) #define BNX2_NVM_CFG4_FLASH_SIZE_1MBIT (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) #define BNX2_NVM_CFG4_FLASH_SIZE_2MBIT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) #define BNX2_NVM_CFG4_FLASH_SIZE_4MBIT (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) #define BNX2_NVM_CFG4_FLASH_SIZE_8MBIT (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) #define BNX2_NVM_CFG4_FLASH_SIZE_16MBIT (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) #define BNX2_NVM_CFG4_FLASH_SIZE_32MBIT (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) #define BNX2_NVM_CFG4_FLASH_SIZE_64MBIT (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) #define BNX2_NVM_CFG4_FLASH_SIZE_128MBIT (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) #define BNX2_NVM_CFG4_FLASH_VENDOR (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) #define BNX2_NVM_CFG4_FLASH_VENDOR_ST (0L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) #define BNX2_NVM_CFG4_FLASH_VENDOR_ATMEL (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT8 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT9 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT10 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #define BNX2_NVM_CFG4_MODE_256_EMPTY_BIT_LOC_BIT11 (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) #define BNX2_NVM_CFG4_STATUS_BIT_POLARITY (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) #define BNX2_NVM_CFG4_RESERVED (0x1ffffffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) #define BNX2_NVM_RECONFIG 0x00006430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ST (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) #define BNX2_NVM_RECONFIG_ORIG_STRAP_VALUE_ATMEL (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) #define BNX2_NVM_RECONFIG_RECONFIG_STRAP_VALUE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) #define BNX2_NVM_RECONFIG_RESERVED (0x7fffffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #define BNX2_NVM_RECONFIG_RECONFIG_DONE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * dma_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * offset: 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) #define BNX2_DMA_COMMAND 0x00000c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) #define BNX2_DMA_COMMAND_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) #define BNX2_DMA_STATUS 0x00000c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) #define BNX2_DMA_STATUS_PAR_ERROR_STATE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) #define BNX2_DMA_STATUS_READ_TRANSFERS_STAT (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) #define BNX2_DMA_STATUS_READ_DELAY_PCI_CLKS_STAT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) #define BNX2_DMA_STATUS_BIG_READ_TRANSFERS_STAT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) #define BNX2_DMA_STATUS_BIG_READ_DELAY_PCI_CLKS_STAT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) #define BNX2_DMA_STATUS_BIG_READ_RETRY_AFTER_DATA_STAT (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) #define BNX2_DMA_STATUS_WRITE_TRANSFERS_STAT (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) #define BNX2_DMA_STATUS_WRITE_DELAY_PCI_CLKS_STAT (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) #define BNX2_DMA_STATUS_BIG_WRITE_TRANSFERS_STAT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) #define BNX2_DMA_STATUS_BIG_WRITE_DELAY_PCI_CLKS_STAT (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) #define BNX2_DMA_STATUS_BIG_WRITE_RETRY_AFTER_DATA_STAT (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) #define BNX2_DMA_STATUS_GLOBAL_ERR_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) #define BNX2_DMA_STATUS_BME_XI (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) #define BNX2_DMA_CONFIG 0x00000c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) #define BNX2_DMA_CONFIG_DATA_BYTE_SWAP (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) #define BNX2_DMA_CONFIG_DATA_WORD_SWAP (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) #define BNX2_DMA_CONFIG_CNTL_BYTE_SWAP (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) #define BNX2_DMA_CONFIG_CNTL_WORD_SWAP (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) #define BNX2_DMA_CONFIG_ONE_DMA (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) #define BNX2_DMA_CONFIG_CNTL_TWO_DMA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) #define BNX2_DMA_CONFIG_CNTL_FPGA_MODE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) #define BNX2_DMA_CONFIG_CNTL_PING_PONG_DMA (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) #define BNX2_DMA_CONFIG_CNTL_PCI_COMP_DLY (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) #define BNX2_DMA_CONFIG_NO_RCHANS_IN_USE (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) #define BNX2_DMA_CONFIG_NO_WCHANS_IN_USE (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) #define BNX2_DMA_CONFIG_PCI_CLK_CMP_BITS (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) #define BNX2_DMA_CONFIG_PCI_FAST_CLK_CMP (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) #define BNX2_DMA_CONFIG_BIG_SIZE (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) #define BNX2_DMA_CONFIG_BIG_SIZE_NONE (0x0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) #define BNX2_DMA_CONFIG_BIG_SIZE_64 (0x1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) #define BNX2_DMA_CONFIG_BIG_SIZE_128 (0x2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) #define BNX2_DMA_CONFIG_BIG_SIZE_256 (0x4L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) #define BNX2_DMA_CONFIG_BIG_SIZE_512 (0x8L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) #define BNX2_DMA_CONFIG_DAT_WBSWAP_MODE_XI (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) #define BNX2_DMA_CONFIG_CTL_WBSWAP_MODE_XI (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) #define BNX2_DMA_CONFIG_MAX_PL_XI (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) #define BNX2_DMA_CONFIG_MAX_PL_128B_XI (0L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) #define BNX2_DMA_CONFIG_MAX_PL_256B_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) #define BNX2_DMA_CONFIG_MAX_PL_512B_XI (2L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) #define BNX2_DMA_CONFIG_MAX_PL_EN_XI (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) #define BNX2_DMA_CONFIG_MAX_RRS_XI (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) #define BNX2_DMA_CONFIG_MAX_RRS_128B_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) #define BNX2_DMA_CONFIG_MAX_RRS_256B_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) #define BNX2_DMA_CONFIG_MAX_RRS_512B_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) #define BNX2_DMA_CONFIG_MAX_RRS_1024B_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) #define BNX2_DMA_CONFIG_MAX_RRS_2048B_XI (4L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) #define BNX2_DMA_CONFIG_MAX_RRS_4096B_XI (5L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) #define BNX2_DMA_CONFIG_MAX_RRS_EN_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) #define BNX2_DMA_CONFIG_NO_64SWAP_EN_XI (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) #define BNX2_DMA_BLACKOUT 0x00000c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) #define BNX2_DMA_BLACKOUT_RD_RETRY_BLACKOUT (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) #define BNX2_DMA_BLACKOUT_2ND_RD_RETRY_BLACKOUT (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) #define BNX2_DMA_BLACKOUT_WR_RETRY_BLACKOUT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) #define BNX2_DMA_READ_MASTER_SETTING_0 0x00000c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_NO_SNOOP (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_RELAX_ORDER (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PRIORITY (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_TRAFFIC_CLASS (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) #define BNX2_DMA_READ_MASTER_SETTING_0_TBDC_PARAM_EN (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_NO_SNOOP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_RELAX_ORDER (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PRIORITY (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_TRAFFIC_CLASS (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) #define BNX2_DMA_READ_MASTER_SETTING_0_RBDC_PARAM_EN (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_NO_SNOOP (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_RELAX_ORDER (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PRIORITY (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_TRAFFIC_CLASS (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) #define BNX2_DMA_READ_MASTER_SETTING_0_TDMA_PARAM_EN (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) #define BNX2_DMA_READ_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) #define BNX2_DMA_READ_MASTER_SETTING_1 0x00000c14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) #define BNX2_DMA_READ_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) #define BNX2_DMA_READ_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) #define BNX2_DMA_READ_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) #define BNX2_DMA_READ_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) #define BNX2_DMA_READ_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) #define BNX2_DMA_READ_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) #define BNX2_DMA_READ_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) #define BNX2_DMA_READ_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) #define BNX2_DMA_WRITE_MASTER_SETTING_0 0x00000c18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_NO_SNOOP (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_RELAX_ORDER (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PRIORITY (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_CS_VLD (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_TRAFFIC_CLASS (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) #define BNX2_DMA_WRITE_MASTER_SETTING_0_HC_PARAM_EN (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_NO_SNOOP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_RELAX_ORDER (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PRIORITY (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_CS_VLD (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_TRAFFIC_CLASS (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) #define BNX2_DMA_WRITE_MASTER_SETTING_0_RDMA_PARAM_EN (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_NO_SNOOP (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_RELAX_ORDER (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PRIORITY (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_CS_VLD (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_TRAFFIC_CLASS (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) #define BNX2_DMA_WRITE_MASTER_SETTING_0_CTX_PARAM_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) #define BNX2_DMA_WRITE_MASTER_SETTING_1 0x00000c1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_NO_SNOOP (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_RELAX_ORDER (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PRIORITY (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_CS_VLD (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_TRAFFIC_CLASS (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) #define BNX2_DMA_WRITE_MASTER_SETTING_1_COM_PARAM_EN (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_NO_SNOOP (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_RELAX_ORDER (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PRIORITY (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_CS_VLD (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_TRAFFIC_CLASS (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) #define BNX2_DMA_WRITE_MASTER_SETTING_1_CP_PARAM_EN (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) #define BNX2_DMA_ARBITER 0x00000c20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) #define BNX2_DMA_ARBITER_NUM_READS (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) #define BNX2_DMA_ARBITER_WR_ARB_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) #define BNX2_DMA_ARBITER_WR_ARB_MODE_STRICT (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) #define BNX2_DMA_ARBITER_WR_ARB_MODE_RND_RBN (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) #define BNX2_DMA_ARBITER_RD_ARB_MODE (0x3L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) #define BNX2_DMA_ARBITER_RD_ARB_MODE_STRICT (0L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) #define BNX2_DMA_ARBITER_RD_ARB_MODE_RND_RBN (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) #define BNX2_DMA_ARBITER_RD_ARB_MODE_WGT_RND_RBN (2L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) #define BNX2_DMA_ARBITER_ALT_MODE_EN (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) #define BNX2_DMA_ARBITER_RR_MODE (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) #define BNX2_DMA_ARBITER_TIMER_MODE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) #define BNX2_DMA_ARBITER_OUSTD_READ_REQ (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) #define BNX2_DMA_ARB_TIMERS 0x00000c24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) #define BNX2_DMA_ARB_TIMERS_RD_DRR_WAIT_TIME (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) #define BNX2_DMA_ARB_TIMERS_TM_MIN_TIMEOUT (0xffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) #define BNX2_DMA_ARB_TIMERS_TM_MAX_TIMEOUT (0xfffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) #define BNX2_DMA_DEBUG_VECT_PEEK 0x00000c2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) #define BNX2_DMA_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) #define BNX2_DMA_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) #define BNX2_DMA_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) #define BNX2_DMA_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) #define BNX2_DMA_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) #define BNX2_DMA_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) #define BNX2_DMA_TAG_RAM_00 0x00000c30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) #define BNX2_DMA_TAG_RAM_00_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) #define BNX2_DMA_TAG_RAM_00_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) #define BNX2_DMA_TAG_RAM_00_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) #define BNX2_DMA_TAG_RAM_00_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) #define BNX2_DMA_TAG_RAM_00_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) #define BNX2_DMA_TAG_RAM_00_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) #define BNX2_DMA_TAG_RAM_00_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) #define BNX2_DMA_TAG_RAM_00_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) #define BNX2_DMA_TAG_RAM_00_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) #define BNX2_DMA_TAG_RAM_00_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) #define BNX2_DMA_TAG_RAM_00_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) #define BNX2_DMA_TAG_RAM_00_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) #define BNX2_DMA_TAG_RAM_00_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) #define BNX2_DMA_TAG_RAM_00_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) #define BNX2_DMA_TAG_RAM_01 0x00000c34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) #define BNX2_DMA_TAG_RAM_01_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) #define BNX2_DMA_TAG_RAM_01_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) #define BNX2_DMA_TAG_RAM_01_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) #define BNX2_DMA_TAG_RAM_01_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) #define BNX2_DMA_TAG_RAM_01_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) #define BNX2_DMA_TAG_RAM_01_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) #define BNX2_DMA_TAG_RAM_01_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #define BNX2_DMA_TAG_RAM_01_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) #define BNX2_DMA_TAG_RAM_01_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) #define BNX2_DMA_TAG_RAM_01_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) #define BNX2_DMA_TAG_RAM_01_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) #define BNX2_DMA_TAG_RAM_01_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) #define BNX2_DMA_TAG_RAM_01_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) #define BNX2_DMA_TAG_RAM_01_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) #define BNX2_DMA_TAG_RAM_02 0x00000c38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) #define BNX2_DMA_TAG_RAM_02_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) #define BNX2_DMA_TAG_RAM_02_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) #define BNX2_DMA_TAG_RAM_02_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) #define BNX2_DMA_TAG_RAM_02_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) #define BNX2_DMA_TAG_RAM_02_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) #define BNX2_DMA_TAG_RAM_02_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) #define BNX2_DMA_TAG_RAM_02_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) #define BNX2_DMA_TAG_RAM_02_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) #define BNX2_DMA_TAG_RAM_02_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) #define BNX2_DMA_TAG_RAM_02_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) #define BNX2_DMA_TAG_RAM_02_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) #define BNX2_DMA_TAG_RAM_02_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) #define BNX2_DMA_TAG_RAM_02_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) #define BNX2_DMA_TAG_RAM_02_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) #define BNX2_DMA_TAG_RAM_03 0x00000c3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) #define BNX2_DMA_TAG_RAM_03_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) #define BNX2_DMA_TAG_RAM_03_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) #define BNX2_DMA_TAG_RAM_03_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) #define BNX2_DMA_TAG_RAM_03_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) #define BNX2_DMA_TAG_RAM_03_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) #define BNX2_DMA_TAG_RAM_03_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) #define BNX2_DMA_TAG_RAM_03_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) #define BNX2_DMA_TAG_RAM_03_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) #define BNX2_DMA_TAG_RAM_03_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) #define BNX2_DMA_TAG_RAM_03_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) #define BNX2_DMA_TAG_RAM_03_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) #define BNX2_DMA_TAG_RAM_03_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) #define BNX2_DMA_TAG_RAM_03_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) #define BNX2_DMA_TAG_RAM_03_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) #define BNX2_DMA_TAG_RAM_04 0x00000c40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) #define BNX2_DMA_TAG_RAM_04_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) #define BNX2_DMA_TAG_RAM_04_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) #define BNX2_DMA_TAG_RAM_04_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) #define BNX2_DMA_TAG_RAM_04_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) #define BNX2_DMA_TAG_RAM_04_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) #define BNX2_DMA_TAG_RAM_04_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) #define BNX2_DMA_TAG_RAM_04_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) #define BNX2_DMA_TAG_RAM_04_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) #define BNX2_DMA_TAG_RAM_04_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) #define BNX2_DMA_TAG_RAM_04_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) #define BNX2_DMA_TAG_RAM_04_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) #define BNX2_DMA_TAG_RAM_04_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) #define BNX2_DMA_TAG_RAM_04_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) #define BNX2_DMA_TAG_RAM_04_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #define BNX2_DMA_TAG_RAM_05 0x00000c44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) #define BNX2_DMA_TAG_RAM_05_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #define BNX2_DMA_TAG_RAM_05_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) #define BNX2_DMA_TAG_RAM_05_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #define BNX2_DMA_TAG_RAM_05_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) #define BNX2_DMA_TAG_RAM_05_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) #define BNX2_DMA_TAG_RAM_05_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #define BNX2_DMA_TAG_RAM_05_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) #define BNX2_DMA_TAG_RAM_05_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) #define BNX2_DMA_TAG_RAM_05_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #define BNX2_DMA_TAG_RAM_05_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) #define BNX2_DMA_TAG_RAM_05_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #define BNX2_DMA_TAG_RAM_05_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #define BNX2_DMA_TAG_RAM_05_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) #define BNX2_DMA_TAG_RAM_05_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) #define BNX2_DMA_TAG_RAM_06 0x00000c48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) #define BNX2_DMA_TAG_RAM_06_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) #define BNX2_DMA_TAG_RAM_06_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) #define BNX2_DMA_TAG_RAM_06_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) #define BNX2_DMA_TAG_RAM_06_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) #define BNX2_DMA_TAG_RAM_06_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) #define BNX2_DMA_TAG_RAM_06_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) #define BNX2_DMA_TAG_RAM_06_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #define BNX2_DMA_TAG_RAM_06_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) #define BNX2_DMA_TAG_RAM_06_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) #define BNX2_DMA_TAG_RAM_06_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) #define BNX2_DMA_TAG_RAM_06_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) #define BNX2_DMA_TAG_RAM_06_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) #define BNX2_DMA_TAG_RAM_06_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) #define BNX2_DMA_TAG_RAM_06_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) #define BNX2_DMA_TAG_RAM_07 0x00000c4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) #define BNX2_DMA_TAG_RAM_07_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) #define BNX2_DMA_TAG_RAM_07_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #define BNX2_DMA_TAG_RAM_07_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) #define BNX2_DMA_TAG_RAM_07_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) #define BNX2_DMA_TAG_RAM_07_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) #define BNX2_DMA_TAG_RAM_07_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) #define BNX2_DMA_TAG_RAM_07_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) #define BNX2_DMA_TAG_RAM_07_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) #define BNX2_DMA_TAG_RAM_07_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) #define BNX2_DMA_TAG_RAM_07_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) #define BNX2_DMA_TAG_RAM_07_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) #define BNX2_DMA_TAG_RAM_07_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) #define BNX2_DMA_TAG_RAM_07_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) #define BNX2_DMA_TAG_RAM_07_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) #define BNX2_DMA_TAG_RAM_08 0x00000c50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) #define BNX2_DMA_TAG_RAM_08_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) #define BNX2_DMA_TAG_RAM_08_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #define BNX2_DMA_TAG_RAM_08_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) #define BNX2_DMA_TAG_RAM_08_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) #define BNX2_DMA_TAG_RAM_08_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) #define BNX2_DMA_TAG_RAM_08_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) #define BNX2_DMA_TAG_RAM_08_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) #define BNX2_DMA_TAG_RAM_08_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) #define BNX2_DMA_TAG_RAM_08_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) #define BNX2_DMA_TAG_RAM_08_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) #define BNX2_DMA_TAG_RAM_08_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) #define BNX2_DMA_TAG_RAM_08_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) #define BNX2_DMA_TAG_RAM_08_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) #define BNX2_DMA_TAG_RAM_08_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) #define BNX2_DMA_TAG_RAM_09 0x00000c54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) #define BNX2_DMA_TAG_RAM_09_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) #define BNX2_DMA_TAG_RAM_09_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) #define BNX2_DMA_TAG_RAM_09_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) #define BNX2_DMA_TAG_RAM_09_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) #define BNX2_DMA_TAG_RAM_09_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) #define BNX2_DMA_TAG_RAM_09_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) #define BNX2_DMA_TAG_RAM_09_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) #define BNX2_DMA_TAG_RAM_09_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) #define BNX2_DMA_TAG_RAM_09_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) #define BNX2_DMA_TAG_RAM_09_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) #define BNX2_DMA_TAG_RAM_09_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) #define BNX2_DMA_TAG_RAM_09_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) #define BNX2_DMA_TAG_RAM_09_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) #define BNX2_DMA_TAG_RAM_09_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) #define BNX2_DMA_TAG_RAM_10 0x00000c58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) #define BNX2_DMA_TAG_RAM_10_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) #define BNX2_DMA_TAG_RAM_10_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) #define BNX2_DMA_TAG_RAM_10_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) #define BNX2_DMA_TAG_RAM_10_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) #define BNX2_DMA_TAG_RAM_10_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) #define BNX2_DMA_TAG_RAM_10_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) #define BNX2_DMA_TAG_RAM_10_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) #define BNX2_DMA_TAG_RAM_10_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) #define BNX2_DMA_TAG_RAM_10_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) #define BNX2_DMA_TAG_RAM_10_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) #define BNX2_DMA_TAG_RAM_10_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) #define BNX2_DMA_TAG_RAM_10_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) #define BNX2_DMA_TAG_RAM_10_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) #define BNX2_DMA_TAG_RAM_10_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) #define BNX2_DMA_TAG_RAM_11 0x00000c5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) #define BNX2_DMA_TAG_RAM_11_CHANNEL (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) #define BNX2_DMA_TAG_RAM_11_MASTER (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) #define BNX2_DMA_TAG_RAM_11_MASTER_CTX (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) #define BNX2_DMA_TAG_RAM_11_MASTER_RBDC (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) #define BNX2_DMA_TAG_RAM_11_MASTER_TBDC (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) #define BNX2_DMA_TAG_RAM_11_MASTER_COM (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) #define BNX2_DMA_TAG_RAM_11_MASTER_CP (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) #define BNX2_DMA_TAG_RAM_11_MASTER_TDMA (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) #define BNX2_DMA_TAG_RAM_11_SWAP (0x3L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) #define BNX2_DMA_TAG_RAM_11_SWAP_CONFIG (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) #define BNX2_DMA_TAG_RAM_11_SWAP_DATA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) #define BNX2_DMA_TAG_RAM_11_SWAP_CONTROL (2L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) #define BNX2_DMA_TAG_RAM_11_FUNCTION (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) #define BNX2_DMA_TAG_RAM_11_VALID (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) #define BNX2_DMA_RCHAN_STAT_22 0x00000c60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) #define BNX2_DMA_RCHAN_STAT_30 0x00000c64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) #define BNX2_DMA_RCHAN_STAT_31 0x00000c68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) #define BNX2_DMA_RCHAN_STAT_32 0x00000c6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) #define BNX2_DMA_RCHAN_STAT_40 0x00000c70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) #define BNX2_DMA_RCHAN_STAT_41 0x00000c74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) #define BNX2_DMA_RCHAN_STAT_42 0x00000c78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) #define BNX2_DMA_RCHAN_STAT_50 0x00000c7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) #define BNX2_DMA_RCHAN_STAT_51 0x00000c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) #define BNX2_DMA_RCHAN_STAT_52 0x00000c84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) #define BNX2_DMA_RCHAN_STAT_60 0x00000c88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) #define BNX2_DMA_RCHAN_STAT_61 0x00000c8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) #define BNX2_DMA_RCHAN_STAT_62 0x00000c90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) #define BNX2_DMA_RCHAN_STAT_70 0x00000c94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) #define BNX2_DMA_RCHAN_STAT_71 0x00000c98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) #define BNX2_DMA_RCHAN_STAT_72 0x00000c9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) #define BNX2_DMA_WCHAN_STAT_00 0x00000ca0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) #define BNX2_DMA_WCHAN_STAT_00_WCHAN_STA_HOST_ADDR_LOW (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) #define BNX2_DMA_WCHAN_STAT_01 0x00000ca4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) #define BNX2_DMA_WCHAN_STAT_01_WCHAN_STA_HOST_ADDR_HIGH (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) #define BNX2_DMA_WCHAN_STAT_02 0x00000ca8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) #define BNX2_DMA_WCHAN_STAT_02_LENGTH (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) #define BNX2_DMA_WCHAN_STAT_02_WORD_SWAP (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) #define BNX2_DMA_WCHAN_STAT_02_BYTE_SWAP (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) #define BNX2_DMA_WCHAN_STAT_02_PRIORITY_LVL (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) #define BNX2_DMA_WCHAN_STAT_10 0x00000cac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) #define BNX2_DMA_WCHAN_STAT_11 0x00000cb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) #define BNX2_DMA_WCHAN_STAT_12 0x00000cb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) #define BNX2_DMA_WCHAN_STAT_20 0x00000cb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) #define BNX2_DMA_WCHAN_STAT_21 0x00000cbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) #define BNX2_DMA_WCHAN_STAT_22 0x00000cc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) #define BNX2_DMA_WCHAN_STAT_30 0x00000cc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) #define BNX2_DMA_WCHAN_STAT_31 0x00000cc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) #define BNX2_DMA_WCHAN_STAT_32 0x00000ccc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) #define BNX2_DMA_WCHAN_STAT_40 0x00000cd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) #define BNX2_DMA_WCHAN_STAT_41 0x00000cd4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) #define BNX2_DMA_WCHAN_STAT_42 0x00000cd8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) #define BNX2_DMA_WCHAN_STAT_50 0x00000cdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #define BNX2_DMA_WCHAN_STAT_51 0x00000ce0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) #define BNX2_DMA_WCHAN_STAT_52 0x00000ce4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) #define BNX2_DMA_WCHAN_STAT_60 0x00000ce8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) #define BNX2_DMA_WCHAN_STAT_61 0x00000cec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) #define BNX2_DMA_WCHAN_STAT_62 0x00000cf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) #define BNX2_DMA_WCHAN_STAT_70 0x00000cf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) #define BNX2_DMA_WCHAN_STAT_71 0x00000cf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) #define BNX2_DMA_WCHAN_STAT_72 0x00000cfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) #define BNX2_DMA_ARB_STAT_00 0x00000d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) #define BNX2_DMA_ARB_STAT_00_MASTER (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) #define BNX2_DMA_ARB_STAT_00_MASTER_ENC (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) #define BNX2_DMA_ARB_STAT_00_CUR_BINMSTR (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) #define BNX2_DMA_ARB_STAT_01 0x00000d04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) #define BNX2_DMA_ARB_STAT_01_LPR_RPTR (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) #define BNX2_DMA_ARB_STAT_01_LPR_WPTR (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) #define BNX2_DMA_ARB_STAT_01_LPB_RPTR (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) #define BNX2_DMA_ARB_STAT_01_LPB_WPTR (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) #define BNX2_DMA_ARB_STAT_01_HPR_RPTR (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) #define BNX2_DMA_ARB_STAT_01_HPR_WPTR (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) #define BNX2_DMA_ARB_STAT_01_HPB_RPTR (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) #define BNX2_DMA_ARB_STAT_01_HPB_WPTR (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) #define BNX2_DMA_FUSE_CTRL0_CMD 0x00000f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) #define BNX2_DMA_FUSE_CTRL0_CMD_PWRUP_DONE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT_DONE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) #define BNX2_DMA_FUSE_CTRL0_CMD_SHIFT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) #define BNX2_DMA_FUSE_CTRL0_CMD_LOAD (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) #define BNX2_DMA_FUSE_CTRL0_CMD_SEL (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) #define BNX2_DMA_FUSE_CTRL0_DATA 0x00000f04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) #define BNX2_DMA_FUSE_CTRL1_CMD 0x00000f08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) #define BNX2_DMA_FUSE_CTRL1_CMD_PWRUP_DONE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT_DONE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) #define BNX2_DMA_FUSE_CTRL1_CMD_SHIFT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) #define BNX2_DMA_FUSE_CTRL1_CMD_LOAD (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) #define BNX2_DMA_FUSE_CTRL1_CMD_SEL (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) #define BNX2_DMA_FUSE_CTRL1_DATA 0x00000f0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) #define BNX2_DMA_FUSE_CTRL2_CMD 0x00000f10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) #define BNX2_DMA_FUSE_CTRL2_CMD_PWRUP_DONE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT_DONE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) #define BNX2_DMA_FUSE_CTRL2_CMD_SHIFT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) #define BNX2_DMA_FUSE_CTRL2_CMD_LOAD (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) #define BNX2_DMA_FUSE_CTRL2_CMD_SEL (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) #define BNX2_DMA_FUSE_CTRL2_DATA 0x00000f14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) * context_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) * offset: 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) #define BNX2_CTX_COMMAND 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) #define BNX2_CTX_COMMAND_ENABLED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) #define BNX2_CTX_COMMAND_DISABLE_USAGE_CNT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) #define BNX2_CTX_COMMAND_DISABLE_PLRU (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) #define BNX2_CTX_COMMAND_DISABLE_COMBINE_READ (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) #define BNX2_CTX_COMMAND_FLUSH_AHEAD (0x1fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) #define BNX2_CTX_COMMAND_MEM_INIT (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) #define BNX2_CTX_COMMAND_PAGE_SIZE (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) #define BNX2_CTX_COMMAND_PAGE_SIZE_256 (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) #define BNX2_CTX_COMMAND_PAGE_SIZE_512 (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) #define BNX2_CTX_COMMAND_PAGE_SIZE_1K (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) #define BNX2_CTX_COMMAND_PAGE_SIZE_2K (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) #define BNX2_CTX_COMMAND_PAGE_SIZE_4K (4L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) #define BNX2_CTX_COMMAND_PAGE_SIZE_8K (5L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) #define BNX2_CTX_COMMAND_PAGE_SIZE_16K (6L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) #define BNX2_CTX_COMMAND_PAGE_SIZE_32K (7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) #define BNX2_CTX_COMMAND_PAGE_SIZE_64K (8L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) #define BNX2_CTX_COMMAND_PAGE_SIZE_128K (9L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) #define BNX2_CTX_COMMAND_PAGE_SIZE_256K (10L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) #define BNX2_CTX_COMMAND_PAGE_SIZE_512K (11L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) #define BNX2_CTX_COMMAND_PAGE_SIZE_1M (12L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) #define BNX2_CTX_STATUS 0x00001004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) #define BNX2_CTX_STATUS_LOCK_WAIT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) #define BNX2_CTX_STATUS_READ_STAT (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) #define BNX2_CTX_STATUS_WRITE_STAT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) #define BNX2_CTX_STATUS_ACC_STALL_STAT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) #define BNX2_CTX_STATUS_LOCK_STALL_STAT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) #define BNX2_CTX_STATUS_EXT_READ_STAT (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) #define BNX2_CTX_STATUS_EXT_WRITE_STAT (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) #define BNX2_CTX_STATUS_MISS_STAT (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #define BNX2_CTX_STATUS_HIT_STAT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) #define BNX2_CTX_STATUS_DEAD_LOCK (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) #define BNX2_CTX_STATUS_USAGE_CNT_ERR (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) #define BNX2_CTX_STATUS_INVALID_PAGE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #define BNX2_CTX_VIRT_ADDR 0x00001008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) #define BNX2_CTX_VIRT_ADDR_VIRT_ADDR (0x7fffL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) #define BNX2_CTX_PAGE_TBL 0x0000100c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) #define BNX2_CTX_PAGE_TBL_PAGE_TBL (0x3fffL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) #define BNX2_CTX_DATA_ADR 0x00001010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) #define BNX2_CTX_DATA_ADR_DATA_ADR (0x7ffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) #define BNX2_CTX_DATA 0x00001014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) #define BNX2_CTX_LOCK 0x00001018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) #define BNX2_CTX_LOCK_TYPE (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_VOID (0x0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_PROTOCOL (0x1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TX (0x2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_TIMER (0x4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) #define BNX2_CTX_LOCK_TYPE_LOCK_TYPE_COMPLETE (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) #define BNX2_CTX_LOCK_TYPE_VOID_XI (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) #define BNX2_CTX_LOCK_TYPE_PROTOCOL_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) #define BNX2_CTX_LOCK_TYPE_TX_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) #define BNX2_CTX_LOCK_TYPE_TIMER_XI (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) #define BNX2_CTX_LOCK_TYPE_COMPLETE_XI (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) #define BNX2_CTX_LOCK_CID_VALUE (0x3fffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) #define BNX2_CTX_LOCK_GRANTED (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) #define BNX2_CTX_LOCK_MODE (0x7L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) #define BNX2_CTX_LOCK_MODE_UNLOCK (0x0L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) #define BNX2_CTX_LOCK_MODE_IMMEDIATE (0x1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) #define BNX2_CTX_LOCK_MODE_SURE (0x2L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) #define BNX2_CTX_LOCK_STATUS (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) #define BNX2_CTX_LOCK_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) #define BNX2_CTX_CTX_CTRL 0x0000101c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) #define BNX2_CTX_CTX_CTRL_CTX_ADDR (0x7ffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) #define BNX2_CTX_CTX_CTRL_MOD_USAGE_CNT (0x3L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) #define BNX2_CTX_CTX_CTRL_NO_RAM_ACC (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) #define BNX2_CTX_CTX_CTRL_PREFETCH_SIZE (0x3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) #define BNX2_CTX_CTX_CTRL_ATTR (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) #define BNX2_CTX_CTX_CTRL_WRITE_REQ (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) #define BNX2_CTX_CTX_CTRL_READ_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) #define BNX2_CTX_CTX_DATA 0x00001020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) #define BNX2_CTX_ACCESS_STATUS 0x00001040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) #define BNX2_CTX_ACCESS_STATUS_MASTERENCODED (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYSM (0x3L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) #define BNX2_CTX_ACCESS_STATUS_PAGETABLEINITSM (0x3L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) #define BNX2_CTX_ACCESS_STATUS_ACCESSMEMORYINITSM (0x3L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) #define BNX2_CTX_ACCESS_STATUS_QUALIFIED_REQUEST (0x7ffL<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) #define BNX2_CTX_ACCESS_STATUS_CAMMASTERENCODED_XI (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) #define BNX2_CTX_ACCESS_STATUS_CACHEMASTERENCODED_XI (0x1fL<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) #define BNX2_CTX_ACCESS_STATUS_REQUEST_XI (0x3fffffL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) #define BNX2_CTX_DBG_LOCK_STATUS 0x00001044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) #define BNX2_CTX_DBG_LOCK_STATUS_SM (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) #define BNX2_CTX_DBG_LOCK_STATUS_MATCH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) #define BNX2_CTX_CACHE_CTRL_STATUS 0x00001048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) #define BNX2_CTX_CACHE_CTRL_STATUS_RFIFO_OVERFLOW (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) #define BNX2_CTX_CACHE_CTRL_STATUS_INVALID_READ_COMP (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) #define BNX2_CTX_CACHE_CTRL_STATUS_FLUSH_START (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) #define BNX2_CTX_CACHE_CTRL_STATUS_FREE_ENTRY_CNT (0x3fL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) #define BNX2_CTX_CACHE_CTRL_STATUS_CACHE_ENTRY_NEEDED (0x3fL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN0_ACTIVE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN1_ACTIVE (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN2_ACTIVE (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN3_ACTIVE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN4_ACTIVE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN5_ACTIVE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN6_ACTIVE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN7_ACTIVE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN8_ACTIVE (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN9_ACTIVE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) #define BNX2_CTX_CACHE_CTRL_STATUS_RD_CHAN10_ACTIVE (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) #define BNX2_CTX_CACHE_CTRL_SM_STATUS 0x0000104c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_DWC (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_WFIFOC (0x7L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RTAGC (0x7L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #define BNX2_CTX_CACHE_CTRL_SM_STATUS_CS_RFIFOC (0x7L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) #define BNX2_CTX_CACHE_CTRL_SM_STATUS_INVALID_BLK_ADDR (0x7fffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) #define BNX2_CTX_CACHE_STATUS 0x00001050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) #define BNX2_CTX_CACHE_STATUS_HELD_ENTRIES (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) #define BNX2_CTX_CACHE_STATUS_MAX_HELD_ENTRIES (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) #define BNX2_CTX_DMA_STATUS 0x00001054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) #define BNX2_CTX_DMA_STATUS_RD_CHAN0_STATUS (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) #define BNX2_CTX_DMA_STATUS_RD_CHAN1_STATUS (0x3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) #define BNX2_CTX_DMA_STATUS_RD_CHAN2_STATUS (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) #define BNX2_CTX_DMA_STATUS_RD_CHAN3_STATUS (0x3L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) #define BNX2_CTX_DMA_STATUS_RD_CHAN4_STATUS (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) #define BNX2_CTX_DMA_STATUS_RD_CHAN5_STATUS (0x3L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) #define BNX2_CTX_DMA_STATUS_RD_CHAN6_STATUS (0x3L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) #define BNX2_CTX_DMA_STATUS_RD_CHAN7_STATUS (0x3L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) #define BNX2_CTX_DMA_STATUS_RD_CHAN8_STATUS (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) #define BNX2_CTX_DMA_STATUS_RD_CHAN9_STATUS (0x3L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) #define BNX2_CTX_DMA_STATUS_RD_CHAN10_STATUS (0x3L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) #define BNX2_CTX_REP_STATUS 0x00001058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) #define BNX2_CTX_REP_STATUS_ERROR_ENTRY (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) #define BNX2_CTX_REP_STATUS_ERROR_CLIENT_ID (0x1fL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) #define BNX2_CTX_REP_STATUS_USAGE_CNT_MAX_ERR (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) #define BNX2_CTX_REP_STATUS_USAGE_CNT_MIN_ERR (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) #define BNX2_CTX_REP_STATUS_USAGE_CNT_MISS_ERR (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) #define BNX2_CTX_CKSUM_ERROR_STATUS 0x0000105c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) #define BNX2_CTX_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) #define BNX2_CTX_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) #define BNX2_CTX_CHNL_LOCK_STATUS_0 0x00001080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) #define BNX2_CTX_CHNL_LOCK_STATUS_0_CID (0x3fffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE (0x3L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) #define BNX2_CTX_CHNL_LOCK_STATUS_0_MODE_XI (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) #define BNX2_CTX_CHNL_LOCK_STATUS_0_TYPE_XI (0x7L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) #define BNX2_CTX_CHNL_LOCK_STATUS_1 0x00001084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) #define BNX2_CTX_CHNL_LOCK_STATUS_2 0x00001088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) #define BNX2_CTX_CHNL_LOCK_STATUS_3 0x0000108c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) #define BNX2_CTX_CHNL_LOCK_STATUS_4 0x00001090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) #define BNX2_CTX_CHNL_LOCK_STATUS_5 0x00001094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) #define BNX2_CTX_CHNL_LOCK_STATUS_6 0x00001098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) #define BNX2_CTX_CHNL_LOCK_STATUS_7 0x0000109c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) #define BNX2_CTX_CHNL_LOCK_STATUS_8 0x000010a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) #define BNX2_CTX_CHNL_LOCK_STATUS_9 0x000010a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) #define BNX2_CTX_CACHE_DATA 0x000010c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) #define BNX2_CTX_HOST_PAGE_TBL_CTRL 0x000010c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) #define BNX2_CTX_HOST_PAGE_TBL_CTRL_PAGE_TBL_ADDR (0x1ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) #define BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #define BNX2_CTX_HOST_PAGE_TBL_CTRL_READ_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) #define BNX2_CTX_HOST_PAGE_TBL_DATA0 0x000010cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) #define BNX2_CTX_HOST_PAGE_TBL_DATA0_VALUE (0xffffffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #define BNX2_CTX_HOST_PAGE_TBL_DATA1 0x000010d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) #define BNX2_CTX_CAM_CTRL 0x000010d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) #define BNX2_CTX_CAM_CTRL_CAM_ADDR (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) #define BNX2_CTX_CAM_CTRL_RESET (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) #define BNX2_CTX_CAM_CTRL_INVALIDATE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) #define BNX2_CTX_CAM_CTRL_SEARCH (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) #define BNX2_CTX_CAM_CTRL_WRITE_REQ (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) #define BNX2_CTX_CAM_CTRL_READ_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) * emac_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) * offset: 0x1400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) #define BNX2_EMAC_MODE 0x00001400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) #define BNX2_EMAC_MODE_RESET (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) #define BNX2_EMAC_MODE_HALF_DUPLEX (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) #define BNX2_EMAC_MODE_PORT (0x3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) #define BNX2_EMAC_MODE_PORT_NONE (0L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) #define BNX2_EMAC_MODE_PORT_MII (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) #define BNX2_EMAC_MODE_PORT_GMII (2L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) #define BNX2_EMAC_MODE_PORT_MII_10M (3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) #define BNX2_EMAC_MODE_MAC_LOOP (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) #define BNX2_EMAC_MODE_25G_MODE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) #define BNX2_EMAC_MODE_TAGGED_MAC_CTL (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) #define BNX2_EMAC_MODE_TX_BURST (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) #define BNX2_EMAC_MODE_MAX_DEFER_DROP_ENA (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) #define BNX2_EMAC_MODE_EXT_LINK_POL (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) #define BNX2_EMAC_MODE_FORCE_LINK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) #define BNX2_EMAC_MODE_SERDES_MODE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) #define BNX2_EMAC_MODE_BOND_OVRD (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) #define BNX2_EMAC_MODE_MPKT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) #define BNX2_EMAC_MODE_MPKT_RCVD (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) #define BNX2_EMAC_MODE_ACPI_RCVD (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) #define BNX2_EMAC_STATUS 0x00001404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) #define BNX2_EMAC_STATUS_LINK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) #define BNX2_EMAC_STATUS_LINK_CHANGE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) #define BNX2_EMAC_STATUS_SERDES_AUTONEG_COMPLETE (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) #define BNX2_EMAC_STATUS_SERDES_AUTONEG_CHANGE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) #define BNX2_EMAC_STATUS_SERDES_NXT_PG_CHANGE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0 (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) #define BNX2_EMAC_STATUS_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) #define BNX2_EMAC_STATUS_MI_COMPLETE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) #define BNX2_EMAC_STATUS_MI_INT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) #define BNX2_EMAC_STATUS_AP_ERROR (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) #define BNX2_EMAC_STATUS_PARITY_ERROR_STATE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) #define BNX2_EMAC_ATTENTION_ENA 0x00001408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) #define BNX2_EMAC_ATTENTION_ENA_LINK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) #define BNX2_EMAC_ATTENTION_ENA_AUTONEG_CHANGE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) #define BNX2_EMAC_ATTENTION_ENA_NXT_PG_CHANGE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) #define BNX2_EMAC_ATTENTION_ENA_SERDES_RX_CONFIG_IS_0_CHANGE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) #define BNX2_EMAC_ATTENTION_ENA_MI_COMPLETE (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) #define BNX2_EMAC_ATTENTION_ENA_MI_INT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) #define BNX2_EMAC_ATTENTION_ENA_AP_ERROR (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) #define BNX2_EMAC_LED 0x0000140c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) #define BNX2_EMAC_LED_OVERRIDE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) #define BNX2_EMAC_LED_1000MB_OVERRIDE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) #define BNX2_EMAC_LED_100MB_OVERRIDE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) #define BNX2_EMAC_LED_10MB_OVERRIDE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) #define BNX2_EMAC_LED_TRAFFIC_OVERRIDE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) #define BNX2_EMAC_LED_BLNK_TRAFFIC (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) #define BNX2_EMAC_LED_TRAFFIC (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) #define BNX2_EMAC_LED_1000MB (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) #define BNX2_EMAC_LED_100MB (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) #define BNX2_EMAC_LED_10MB (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) #define BNX2_EMAC_LED_TRAFFIC_STAT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) #define BNX2_EMAC_LED_2500MB (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) #define BNX2_EMAC_LED_2500MB_OVERRIDE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) #define BNX2_EMAC_LED_ACTIVITY_SEL (0x3L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) #define BNX2_EMAC_LED_ACTIVITY_SEL_0 (0L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) #define BNX2_EMAC_LED_ACTIVITY_SEL_1 (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) #define BNX2_EMAC_LED_ACTIVITY_SEL_2 (2L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) #define BNX2_EMAC_LED_ACTIVITY_SEL_3 (3L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) #define BNX2_EMAC_LED_BLNK_RATE (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) #define BNX2_EMAC_LED_BLNK_RATE_ENA (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) #define BNX2_EMAC_MAC_MATCH0 0x00001410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) #define BNX2_EMAC_MAC_MATCH1 0x00001414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) #define BNX2_EMAC_MAC_MATCH2 0x00001418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) #define BNX2_EMAC_MAC_MATCH3 0x0000141c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) #define BNX2_EMAC_MAC_MATCH4 0x00001420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) #define BNX2_EMAC_MAC_MATCH5 0x00001424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) #define BNX2_EMAC_MAC_MATCH6 0x00001428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) #define BNX2_EMAC_MAC_MATCH7 0x0000142c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) #define BNX2_EMAC_MAC_MATCH8 0x00001430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) #define BNX2_EMAC_MAC_MATCH9 0x00001434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) #define BNX2_EMAC_MAC_MATCH10 0x00001438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) #define BNX2_EMAC_MAC_MATCH11 0x0000143c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) #define BNX2_EMAC_MAC_MATCH12 0x00001440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) #define BNX2_EMAC_MAC_MATCH13 0x00001444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) #define BNX2_EMAC_MAC_MATCH14 0x00001448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) #define BNX2_EMAC_MAC_MATCH15 0x0000144c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) #define BNX2_EMAC_MAC_MATCH16 0x00001450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) #define BNX2_EMAC_MAC_MATCH17 0x00001454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) #define BNX2_EMAC_MAC_MATCH18 0x00001458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) #define BNX2_EMAC_MAC_MATCH19 0x0000145c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) #define BNX2_EMAC_MAC_MATCH20 0x00001460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) #define BNX2_EMAC_MAC_MATCH21 0x00001464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) #define BNX2_EMAC_MAC_MATCH22 0x00001468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) #define BNX2_EMAC_MAC_MATCH23 0x0000146c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) #define BNX2_EMAC_MAC_MATCH24 0x00001470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) #define BNX2_EMAC_MAC_MATCH25 0x00001474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) #define BNX2_EMAC_MAC_MATCH26 0x00001478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) #define BNX2_EMAC_MAC_MATCH27 0x0000147c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) #define BNX2_EMAC_MAC_MATCH28 0x00001480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) #define BNX2_EMAC_MAC_MATCH29 0x00001484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) #define BNX2_EMAC_MAC_MATCH30 0x00001488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) #define BNX2_EMAC_MAC_MATCH31 0x0000148c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) #define BNX2_EMAC_BACKOFF_SEED 0x00001498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) #define BNX2_EMAC_BACKOFF_SEED_EMAC_BACKOFF_SEED (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) #define BNX2_EMAC_RX_MTU_SIZE 0x0000149c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) #define BNX2_EMAC_RX_MTU_SIZE_MTU_SIZE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) #define BNX2_EMAC_RX_MTU_SIZE_JUMBO_ENA (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) #define BNX2_EMAC_SERDES_CNTL 0x000014a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) #define BNX2_EMAC_SERDES_CNTL_RXR (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) #define BNX2_EMAC_SERDES_CNTL_RXG (0x3L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) #define BNX2_EMAC_SERDES_CNTL_RXCKSEL (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) #define BNX2_EMAC_SERDES_CNTL_TXBIAS (0x7L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) #define BNX2_EMAC_SERDES_CNTL_BGMAX (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) #define BNX2_EMAC_SERDES_CNTL_BGMIN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) #define BNX2_EMAC_SERDES_CNTL_TXMODE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) #define BNX2_EMAC_SERDES_CNTL_TXEDGE (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) #define BNX2_EMAC_SERDES_CNTL_SERDES_MODE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) #define BNX2_EMAC_SERDES_CNTL_PLLTEST (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) #define BNX2_EMAC_SERDES_CNTL_CDET_EN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) #define BNX2_EMAC_SERDES_CNTL_TBI_LBK (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) #define BNX2_EMAC_SERDES_CNTL_REMOTE_LBK (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) #define BNX2_EMAC_SERDES_CNTL_REV_PHASE (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) #define BNX2_EMAC_SERDES_CNTL_REGCTL12 (0x3L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) #define BNX2_EMAC_SERDES_CNTL_REGCTL25 (0x3L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) #define BNX2_EMAC_SERDES_STATUS 0x000014a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) #define BNX2_EMAC_SERDES_STATUS_RX_STAT (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) #define BNX2_EMAC_SERDES_STATUS_COMMA_DET (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) #define BNX2_EMAC_MDIO_COMM 0x000014ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) #define BNX2_EMAC_MDIO_COMM_DATA (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) #define BNX2_EMAC_MDIO_COMM_REG_ADDR (0x1fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) #define BNX2_EMAC_MDIO_COMM_PHY_ADDR (0x1fL<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) #define BNX2_EMAC_MDIO_COMM_COMMAND (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_0 (0L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) #define BNX2_EMAC_MDIO_COMM_COMMAND_ADDRESS (0L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) #define BNX2_EMAC_MDIO_COMM_COMMAND_READ (2L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_22_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) #define BNX2_EMAC_MDIO_COMM_COMMAND_WRITE_45_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_22_XI (2L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_INC_45_XI (2L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) #define BNX2_EMAC_MDIO_COMM_COMMAND_UNDEFINED_3 (3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) #define BNX2_EMAC_MDIO_COMM_COMMAND_READ_45 (3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) #define BNX2_EMAC_MDIO_COMM_FAIL (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) #define BNX2_EMAC_MDIO_COMM_START_BUSY (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) #define BNX2_EMAC_MDIO_COMM_DISEXT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) #define BNX2_EMAC_MDIO_STATUS 0x000014b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) #define BNX2_EMAC_MDIO_STATUS_LINK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) #define BNX2_EMAC_MDIO_STATUS_10MB (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) #define BNX2_EMAC_MDIO_MODE 0x000014b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) #define BNX2_EMAC_MDIO_MODE_SHORT_PREAMBLE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) #define BNX2_EMAC_MDIO_MODE_AUTO_POLL (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) #define BNX2_EMAC_MDIO_MODE_BIT_BANG (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) #define BNX2_EMAC_MDIO_MODE_MDIO (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) #define BNX2_EMAC_MDIO_MODE_MDIO_OE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) #define BNX2_EMAC_MDIO_MODE_MDC (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) #define BNX2_EMAC_MDIO_MODE_MDINT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) #define BNX2_EMAC_MDIO_MODE_EXT_MDINT (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT (0x1fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) #define BNX2_EMAC_MDIO_MODE_CLOCK_CNT_XI (0x3fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) #define BNX2_EMAC_MDIO_MODE_CLAUSE_45_XI (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) #define BNX2_EMAC_MDIO_AUTO_STATUS 0x000014b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) #define BNX2_EMAC_MDIO_AUTO_STATUS_AUTO_ERR (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) #define BNX2_EMAC_TX_MODE 0x000014bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) #define BNX2_EMAC_TX_MODE_RESET (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) #define BNX2_EMAC_TX_MODE_CS16_TEST (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) #define BNX2_EMAC_TX_MODE_EXT_PAUSE_EN (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) #define BNX2_EMAC_TX_MODE_FLOW_EN (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) #define BNX2_EMAC_TX_MODE_BIG_BACKOFF (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) #define BNX2_EMAC_TX_MODE_LONG_PAUSE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) #define BNX2_EMAC_TX_MODE_LINK_AWARE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) #define BNX2_EMAC_TX_STATUS 0x000014c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) #define BNX2_EMAC_TX_STATUS_XOFFED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) #define BNX2_EMAC_TX_STATUS_XOFF_SENT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) #define BNX2_EMAC_TX_STATUS_XON_SENT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) #define BNX2_EMAC_TX_STATUS_LINK_UP (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) #define BNX2_EMAC_TX_STATUS_UNDERRUN (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #define BNX2_EMAC_TX_STATUS_CS16_ERROR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) #define BNX2_EMAC_TX_LENGTHS 0x000014c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) #define BNX2_EMAC_TX_LENGTHS_SLOT (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) #define BNX2_EMAC_TX_LENGTHS_IPG (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) #define BNX2_EMAC_TX_LENGTHS_IPG_CRS (0x3L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) #define BNX2_EMAC_RX_MODE 0x000014c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) #define BNX2_EMAC_RX_MODE_RESET (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) #define BNX2_EMAC_RX_MODE_FLOW_EN (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) #define BNX2_EMAC_RX_MODE_KEEP_MAC_CONTROL (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) #define BNX2_EMAC_RX_MODE_KEEP_PAUSE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) #define BNX2_EMAC_RX_MODE_ACCEPT_OVERSIZE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) #define BNX2_EMAC_RX_MODE_ACCEPT_RUNTS (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) #define BNX2_EMAC_RX_MODE_LLC_CHK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) #define BNX2_EMAC_RX_MODE_PROMISCUOUS (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) #define BNX2_EMAC_RX_MODE_NO_CRC_CHK (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) #define BNX2_EMAC_RX_MODE_KEEP_VLAN_TAG (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) #define BNX2_EMAC_RX_MODE_FILT_BROADCAST (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) #define BNX2_EMAC_RX_MODE_SORT_MODE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) #define BNX2_EMAC_RX_STATUS 0x000014cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) #define BNX2_EMAC_RX_STATUS_FFED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) #define BNX2_EMAC_RX_STATUS_FF_RECEIVED (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) #define BNX2_EMAC_RX_STATUS_N_RECEIVED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) #define BNX2_EMAC_MULTICAST_HASH0 0x000014d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) #define BNX2_EMAC_MULTICAST_HASH1 0x000014d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) #define BNX2_EMAC_MULTICAST_HASH2 0x000014d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) #define BNX2_EMAC_MULTICAST_HASH3 0x000014dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) #define BNX2_EMAC_MULTICAST_HASH4 0x000014e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) #define BNX2_EMAC_MULTICAST_HASH5 0x000014e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) #define BNX2_EMAC_MULTICAST_HASH6 0x000014e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) #define BNX2_EMAC_MULTICAST_HASH7 0x000014ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) #define BNX2_EMAC_CKSUM_ERROR_STATUS 0x000014f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) #define BNX2_EMAC_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) #define BNX2_EMAC_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #define BNX2_EMAC_RX_STAT_IFHCINOCTETS 0x00001500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) #define BNX2_EMAC_RX_STAT_IFHCINBADOCTETS 0x00001504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) #define BNX2_EMAC_RX_STAT_ETHERSTATSFRAGMENTS 0x00001508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) #define BNX2_EMAC_RX_STAT_IFHCINUCASTPKTS 0x0000150c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) #define BNX2_EMAC_RX_STAT_IFHCINMULTICASTPKTS 0x00001510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) #define BNX2_EMAC_RX_STAT_IFHCINBROADCASTPKTS 0x00001514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) #define BNX2_EMAC_RX_STAT_DOT3STATSFCSERRORS 0x00001518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) #define BNX2_EMAC_RX_STAT_DOT3STATSALIGNMENTERRORS 0x0000151c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) #define BNX2_EMAC_RX_STAT_DOT3STATSCARRIERSENSEERRORS 0x00001520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) #define BNX2_EMAC_RX_STAT_XONPAUSEFRAMESRECEIVED 0x00001524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) #define BNX2_EMAC_RX_STAT_XOFFPAUSEFRAMESRECEIVED 0x00001528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) #define BNX2_EMAC_RX_STAT_MACCONTROLFRAMESRECEIVED 0x0000152c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) #define BNX2_EMAC_RX_STAT_XOFFSTATEENTERED 0x00001530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) #define BNX2_EMAC_RX_STAT_DOT3STATSFRAMESTOOLONG 0x00001534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) #define BNX2_EMAC_RX_STAT_ETHERSTATSJABBERS 0x00001538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) #define BNX2_EMAC_RX_STAT_ETHERSTATSUNDERSIZEPKTS 0x0000153c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS64OCTETS 0x00001540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x00001544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001548
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x0000154c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001550
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x00001554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) #define BNX2_EMAC_RX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001558
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) #define BNX2_EMAC_RXMAC_DEBUG0 0x0000155c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) #define BNX2_EMAC_RXMAC_DEBUG1 0x00001560
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_NE_BYTE_COUNT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) #define BNX2_EMAC_RXMAC_DEBUG1_LENGTH_OUT_RANGE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) #define BNX2_EMAC_RXMAC_DEBUG1_BAD_CRC (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) #define BNX2_EMAC_RXMAC_DEBUG1_RX_ERROR (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) #define BNX2_EMAC_RXMAC_DEBUG1_ALIGN_ERROR (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) #define BNX2_EMAC_RXMAC_DEBUG1_LAST_DATA (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) #define BNX2_EMAC_RXMAC_DEBUG1_ODD_BYTE_START (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) #define BNX2_EMAC_RXMAC_DEBUG1_BYTE_COUNT (0xffffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) #define BNX2_EMAC_RXMAC_DEBUG1_SLOT_TIME (0xffL<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) #define BNX2_EMAC_RXMAC_DEBUG2 0x00001564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_IDLE (0x0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SFD (0x1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DATA (0x2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SKEEP (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_EXT (0x4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_DROP (0x5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_SDROP (0x6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) #define BNX2_EMAC_RXMAC_DEBUG2_SM_STATE_FC (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE (0xfL<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_IDLE (0x0L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA0 (0x1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA1 (0x2L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA2 (0x3L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_DATA3 (0x4L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_ABORT (0x5L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_WAIT (0x6L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_STATUS (0x7L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) #define BNX2_EMAC_RXMAC_DEBUG2_IDI_STATE_LAST (0x8L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) #define BNX2_EMAC_RXMAC_DEBUG2_BYTE_IN (0xffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) #define BNX2_EMAC_RXMAC_DEBUG2_FALSEC (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) #define BNX2_EMAC_RXMAC_DEBUG2_TAGGED (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_IDLE (0L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) #define BNX2_EMAC_RXMAC_DEBUG2_PAUSE_STATE_PAUSED (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) #define BNX2_EMAC_RXMAC_DEBUG2_SE_COUNTER (0xfL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) #define BNX2_EMAC_RXMAC_DEBUG2_QUANTA (0x1fL<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) #define BNX2_EMAC_RXMAC_DEBUG3 0x00001568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) #define BNX2_EMAC_RXMAC_DEBUG3_PAUSE_CTR (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) #define BNX2_EMAC_RXMAC_DEBUG3_TMP_PAUSE_CTR (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) #define BNX2_EMAC_RXMAC_DEBUG4 0x0000156c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) #define BNX2_EMAC_RXMAC_DEBUG4_TYPE_FIELD (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE (0x3fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_IDLE (0x0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC2 (0x1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UMAC3 (0x2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UNI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC3 (0x5L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA1 (0x6L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MMAC2 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA2 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PSA3 (0x8L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC2 (0x9L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC3 (0xaL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT1 (0xeL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MWAIT2 (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MCHECK (0x10L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MC (0x11L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC2 (0x12L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC3 (0x13L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA1 (0x14L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA2 (0x15L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BSA3 (0x16L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BTYPE (0x17L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_BC (0x18L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PTYPE (0x19L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_CMD (0x1aL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MAC (0x1bL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_LATCH (0x1cL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XOFF (0x1dL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_XON (0x1eL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_PAUSED (0x1fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_NPAUSED (0x20L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TTYPE (0x21L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_TVAL (0x22L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA1 (0x23L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA2 (0x24L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_USA3 (0x25L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTYPE (0x26L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTTYPE (0x27L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_UTVAL (0x28L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_MTYPE (0x29L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) #define BNX2_EMAC_RXMAC_DEBUG4_FILT_STATE_DROP (0x2aL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) #define BNX2_EMAC_RXMAC_DEBUG4_DROP_PKT (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) #define BNX2_EMAC_RXMAC_DEBUG4_SLOT_FILLED (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) #define BNX2_EMAC_RXMAC_DEBUG4_FALSE_CARRIER (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) #define BNX2_EMAC_RXMAC_DEBUG4_LAST_DATA (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) #define BNX2_EMAC_RXMAC_DEBUG4_SFD_FOUND (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) #define BNX2_EMAC_RXMAC_DEBUG4_ADVANCE (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) #define BNX2_EMAC_RXMAC_DEBUG4_START (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) #define BNX2_EMAC_RXMAC_DEBUG5 0x00001570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_IDLE (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_EOF (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_WAIT_STAT (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4FCRC (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4RDE (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_SET_EOF4ALL (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) #define BNX2_EMAC_RXMAC_DEBUG5_PS_IDISM_1WD_WAIT_STAT (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1 (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_VDW (0x0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_STAT (0x1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_AEOF (0x2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_NEOF (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SOF (0x4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SAEOF (0x6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF1_SNEOF (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) #define BNX2_EMAC_RXMAC_DEBUG5_EOF_DETECTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) #define BNX2_EMAC_RXMAC_DEBUG5_CCODE_BUF0 (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) #define BNX2_EMAC_RXMAC_DEBUG5_RPM_IDI_FIFO_FULL (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_CCODE (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_DATA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) #define BNX2_EMAC_RXMAC_DEBUG5_LOAD_STAT (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) #define BNX2_EMAC_RXMAC_DEBUG5_CLR_STAT (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_CCODE (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) #define BNX2_EMAC_RXMAC_DEBUG5_IDI_RPM_ACCEPT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) #define BNX2_EMAC_RXMAC_DEBUG5_FMLEN (0xfffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) #define BNX2_EMAC_RX_STAT_FALSECARRIERERRORS 0x00001574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) #define BNX2_EMAC_RX_STAT_AC0 0x00001580
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) #define BNX2_EMAC_RX_STAT_AC1 0x00001584
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) #define BNX2_EMAC_RX_STAT_AC2 0x00001588
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) #define BNX2_EMAC_RX_STAT_AC3 0x0000158c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) #define BNX2_EMAC_RX_STAT_AC4 0x00001590
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) #define BNX2_EMAC_RX_STAT_AC5 0x00001594
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) #define BNX2_EMAC_RX_STAT_AC6 0x00001598
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) #define BNX2_EMAC_RX_STAT_AC7 0x0000159c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) #define BNX2_EMAC_RX_STAT_AC8 0x000015a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) #define BNX2_EMAC_RX_STAT_AC9 0x000015a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) #define BNX2_EMAC_RX_STAT_AC10 0x000015a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) #define BNX2_EMAC_RX_STAT_AC11 0x000015ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) #define BNX2_EMAC_RX_STAT_AC12 0x000015b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) #define BNX2_EMAC_RX_STAT_AC13 0x000015b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) #define BNX2_EMAC_RX_STAT_AC14 0x000015b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) #define BNX2_EMAC_RX_STAT_AC15 0x000015bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) #define BNX2_EMAC_RX_STAT_AC16 0x000015c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) #define BNX2_EMAC_RX_STAT_AC17 0x000015c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) #define BNX2_EMAC_RX_STAT_AC18 0x000015c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) #define BNX2_EMAC_RX_STAT_AC19 0x000015cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) #define BNX2_EMAC_RX_STAT_AC20 0x000015d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) #define BNX2_EMAC_RX_STAT_AC21 0x000015d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) #define BNX2_EMAC_RX_STAT_AC22 0x000015d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) #define BNX2_EMAC_RXMAC_SUC_DBG_OVERRUNVEC 0x000015dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) #define BNX2_EMAC_RX_STAT_AC_28 0x000015f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) #define BNX2_EMAC_TX_STAT_IFHCOUTOCTETS 0x00001600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) #define BNX2_EMAC_TX_STAT_IFHCOUTBADOCTETS 0x00001604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) #define BNX2_EMAC_TX_STAT_ETHERSTATSCOLLISIONS 0x00001608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) #define BNX2_EMAC_TX_STAT_OUTXONSENT 0x0000160c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) #define BNX2_EMAC_TX_STAT_OUTXOFFSENT 0x00001610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) #define BNX2_EMAC_TX_STAT_FLOWCONTROLDONE 0x00001614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) #define BNX2_EMAC_TX_STAT_DOT3STATSSINGLECOLLISIONFRAMES 0x00001618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) #define BNX2_EMAC_TX_STAT_DOT3STATSMULTIPLECOLLISIONFRAMES 0x0000161c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) #define BNX2_EMAC_TX_STAT_DOT3STATSDEFERREDTRANSMISSIONS 0x00001620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) #define BNX2_EMAC_TX_STAT_DOT3STATSEXCESSIVECOLLISIONS 0x00001624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) #define BNX2_EMAC_TX_STAT_DOT3STATSLATECOLLISIONS 0x00001628
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) #define BNX2_EMAC_TX_STAT_IFHCOUTUCASTPKTS 0x0000162c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) #define BNX2_EMAC_TX_STAT_IFHCOUTMULTICASTPKTS 0x00001630
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) #define BNX2_EMAC_TX_STAT_IFHCOUTBROADCASTPKTS 0x00001634
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS64OCTETS 0x00001638
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS65OCTETSTO127OCTETS 0x0000163c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS128OCTETSTO255OCTETS 0x00001640
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS256OCTETSTO511OCTETS 0x00001644
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS512OCTETSTO1023OCTETS 0x00001648
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTS1024OCTETSTO1522OCTETS 0x0000164c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) #define BNX2_EMAC_TX_STAT_ETHERSTATSPKTSOVER1522OCTETS 0x00001650
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) #define BNX2_EMAC_TX_STAT_DOT3STATSINTERNALMACTRANSMITERRORS 0x00001654
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) #define BNX2_EMAC_TXMAC_DEBUG0 0x00001658
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) #define BNX2_EMAC_TXMAC_DEBUG1 0x0000165c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_IDLE (0x0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_START0 (0x1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA0 (0x4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA1 (0x5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA2 (0x6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_DATA3 (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT0 (0x8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) #define BNX2_EMAC_TXMAC_DEBUG1_ODI_STATE_WAIT1 (0x9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) #define BNX2_EMAC_TXMAC_DEBUG1_CRS_ENABLE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) #define BNX2_EMAC_TXMAC_DEBUG1_BAD_CRC (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) #define BNX2_EMAC_TXMAC_DEBUG1_SE_COUNTER (0xfL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) #define BNX2_EMAC_TXMAC_DEBUG1_SEND_PAUSE (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) #define BNX2_EMAC_TXMAC_DEBUG1_LATE_COLLISION (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) #define BNX2_EMAC_TXMAC_DEBUG1_MAX_DEFER (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) #define BNX2_EMAC_TXMAC_DEBUG1_DEFERRED (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) #define BNX2_EMAC_TXMAC_DEBUG1_ONE_BYTE (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) #define BNX2_EMAC_TXMAC_DEBUG1_IPG_TIME (0xfL<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) #define BNX2_EMAC_TXMAC_DEBUG1_SLOT_TIME (0xffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) #define BNX2_EMAC_TXMAC_DEBUG2 0x00001660
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) #define BNX2_EMAC_TXMAC_DEBUG2_BACK_OFF (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) #define BNX2_EMAC_TXMAC_DEBUG2_BYTE_COUNT (0xffffL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) #define BNX2_EMAC_TXMAC_DEBUG2_COL_COUNT (0x1fL<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) #define BNX2_EMAC_TXMAC_DEBUG2_COL_BIT (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) #define BNX2_EMAC_TXMAC_DEBUG3 0x00001664
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_IDLE (0x0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE1 (0x1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_PRE2 (0x2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SFD (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_DATA (0x4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC1 (0x5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_CRC2 (0x6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EXT (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATB (0x8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_STATG (0x9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_JAM (0xaL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_EJAM (0xbL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BJAM (0xcL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_SWAIT (0xdL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) #define BNX2_EMAC_TXMAC_DEBUG3_SM_STATE_BACKOFF (0xeL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_IDLE (0x0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_WAIT (0x1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_UNI (0x2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_MC (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC2 (0x4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC3 (0x5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) #define BNX2_EMAC_TXMAC_DEBUG3_FILT_STATE_BC (0x6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) #define BNX2_EMAC_TXMAC_DEBUG3_CRS_DONE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) #define BNX2_EMAC_TXMAC_DEBUG3_XOFF (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) #define BNX2_EMAC_TXMAC_DEBUG3_SE_COUNTER (0xfL<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) #define BNX2_EMAC_TXMAC_DEBUG3_QUANTA_COUNTER (0x1fL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) #define BNX2_EMAC_TXMAC_DEBUG4 0x00001668
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_COUNTER (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_IDLE (0x0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA1 (0x2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA2 (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC3 (0x4L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC2 (0x5L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_MCA3 (0x6L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_SRC1 (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC1 (0x8L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CRC2 (0x9L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TIME (0xaL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_TYPE (0xcL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_WAIT (0xdL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) #define BNX2_EMAC_TXMAC_DEBUG4_PAUSE_STATE_CMD (0xeL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) #define BNX2_EMAC_TXMAC_DEBUG4_STATS0_VALID (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) #define BNX2_EMAC_TXMAC_DEBUG4_APPEND_CRC (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) #define BNX2_EMAC_TXMAC_DEBUG4_SLOT_FILLED (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) #define BNX2_EMAC_TXMAC_DEBUG4_MAX_DEFER (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) #define BNX2_EMAC_TXMAC_DEBUG4_SEND_EXTEND (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) #define BNX2_EMAC_TXMAC_DEBUG4_SEND_PADDING (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) #define BNX2_EMAC_TXMAC_DEBUG4_EOF_LOC (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) #define BNX2_EMAC_TXMAC_DEBUG4_COLLIDING (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) #define BNX2_EMAC_TXMAC_DEBUG4_COL_IN (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) #define BNX2_EMAC_TXMAC_DEBUG4_BURSTING (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) #define BNX2_EMAC_TXMAC_DEBUG4_ADVANCE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) #define BNX2_EMAC_TXMAC_DEBUG4_GO (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) #define BNX2_EMAC_TX_STAT_AC0 0x00001680
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) #define BNX2_EMAC_TX_STAT_AC1 0x00001684
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) #define BNX2_EMAC_TX_STAT_AC2 0x00001688
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) #define BNX2_EMAC_TX_STAT_AC3 0x0000168c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) #define BNX2_EMAC_TX_STAT_AC4 0x00001690
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) #define BNX2_EMAC_TX_STAT_AC5 0x00001694
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) #define BNX2_EMAC_TX_STAT_AC6 0x00001698
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) #define BNX2_EMAC_TX_STAT_AC7 0x0000169c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) #define BNX2_EMAC_TX_STAT_AC8 0x000016a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) #define BNX2_EMAC_TX_STAT_AC9 0x000016a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) #define BNX2_EMAC_TX_STAT_AC10 0x000016a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) #define BNX2_EMAC_TX_STAT_AC11 0x000016ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) #define BNX2_EMAC_TX_STAT_AC12 0x000016b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) #define BNX2_EMAC_TX_STAT_AC13 0x000016b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) #define BNX2_EMAC_TX_STAT_AC14 0x000016b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) #define BNX2_EMAC_TX_STAT_AC15 0x000016bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) #define BNX2_EMAC_TX_STAT_AC16 0x000016c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) #define BNX2_EMAC_TX_STAT_AC17 0x000016c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) #define BNX2_EMAC_TX_STAT_AC18 0x000016c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) #define BNX2_EMAC_TX_STAT_AC19 0x000016cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) #define BNX2_EMAC_TX_STAT_AC20 0x000016d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) #define BNX2_EMAC_TXMAC_SUC_DBG_OVERRUNVEC 0x000016d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) #define BNX2_EMAC_TX_RATE_LIMIT_CTRL 0x000016fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_INC (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_TX_THROTTLE_NUM (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) #define BNX2_EMAC_TX_RATE_LIMIT_CTRL_RATE_LIMITER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) * rpm_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) * offset: 0x1800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) #define BNX2_RPM_COMMAND 0x00001800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) #define BNX2_RPM_COMMAND_ENABLED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) #define BNX2_RPM_COMMAND_OVERRUN_ABORT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) #define BNX2_RPM_STATUS 0x00001804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) #define BNX2_RPM_STATUS_MBUF_WAIT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) #define BNX2_RPM_STATUS_FREE_WAIT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) #define BNX2_RPM_CONFIG 0x00001808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) #define BNX2_RPM_CONFIG_NO_PSD_HDR_CKSUM (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) #define BNX2_RPM_CONFIG_ACPI_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) #define BNX2_RPM_CONFIG_ACPI_KEEP (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) #define BNX2_RPM_CONFIG_MP_KEEP (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) #define BNX2_RPM_CONFIG_SORT_VECT_VAL (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) #define BNX2_RPM_CONFIG_DISABLE_WOL_ASSERT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) #define BNX2_RPM_CONFIG_IGNORE_VLAN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) #define BNX2_RPM_MGMT_PKT_CTRL 0x0000180c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_SORT (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_RULE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_DISCARD_EN (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) #define BNX2_RPM_MGMT_PKT_CTRL_MGMT_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) #define BNX2_RPM_VLAN_MATCH0 0x00001810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) #define BNX2_RPM_VLAN_MATCH0_RPM_VLAN_MTCH0_VALUE (0xfffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) #define BNX2_RPM_VLAN_MATCH1 0x00001814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) #define BNX2_RPM_VLAN_MATCH1_RPM_VLAN_MTCH1_VALUE (0xfffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) #define BNX2_RPM_VLAN_MATCH2 0x00001818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) #define BNX2_RPM_VLAN_MATCH2_RPM_VLAN_MTCH2_VALUE (0xfffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) #define BNX2_RPM_VLAN_MATCH3 0x0000181c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) #define BNX2_RPM_VLAN_MATCH3_RPM_VLAN_MTCH3_VALUE (0xfffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) #define BNX2_RPM_SORT_USER0 0x00001820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) #define BNX2_RPM_SORT_USER0_PM_EN (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) #define BNX2_RPM_SORT_USER0_BC_EN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) #define BNX2_RPM_SORT_USER0_MC_EN (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) #define BNX2_RPM_SORT_USER0_MC_HSH_EN (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) #define BNX2_RPM_SORT_USER0_PROM_EN (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) #define BNX2_RPM_SORT_USER0_VLAN_EN (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) #define BNX2_RPM_SORT_USER0_PROM_VLAN (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) #define BNX2_RPM_SORT_USER0_VLAN_NOTMATCH (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) #define BNX2_RPM_SORT_USER0_ENA (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) #define BNX2_RPM_SORT_USER1 0x00001824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) #define BNX2_RPM_SORT_USER1_PM_EN (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) #define BNX2_RPM_SORT_USER1_BC_EN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) #define BNX2_RPM_SORT_USER1_MC_EN (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) #define BNX2_RPM_SORT_USER1_MC_HSH_EN (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) #define BNX2_RPM_SORT_USER1_PROM_EN (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) #define BNX2_RPM_SORT_USER1_VLAN_EN (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) #define BNX2_RPM_SORT_USER1_PROM_VLAN (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) #define BNX2_RPM_SORT_USER1_ENA (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) #define BNX2_RPM_SORT_USER2 0x00001828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) #define BNX2_RPM_SORT_USER2_PM_EN (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) #define BNX2_RPM_SORT_USER2_BC_EN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) #define BNX2_RPM_SORT_USER2_MC_EN (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) #define BNX2_RPM_SORT_USER2_MC_HSH_EN (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) #define BNX2_RPM_SORT_USER2_PROM_EN (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) #define BNX2_RPM_SORT_USER2_VLAN_EN (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) #define BNX2_RPM_SORT_USER2_PROM_VLAN (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) #define BNX2_RPM_SORT_USER2_ENA (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) #define BNX2_RPM_SORT_USER3 0x0000182c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) #define BNX2_RPM_SORT_USER3_PM_EN (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) #define BNX2_RPM_SORT_USER3_BC_EN (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) #define BNX2_RPM_SORT_USER3_MC_EN (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) #define BNX2_RPM_SORT_USER3_MC_HSH_EN (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) #define BNX2_RPM_SORT_USER3_PROM_EN (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) #define BNX2_RPM_SORT_USER3_VLAN_EN (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) #define BNX2_RPM_SORT_USER3_PROM_VLAN (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) #define BNX2_RPM_SORT_USER3_ENA (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) #define BNX2_RPM_STAT_L2_FILTER_DISCARDS 0x00001840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) #define BNX2_RPM_STAT_RULE_CHECKER_DISCARDS 0x00001844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) #define BNX2_RPM_STAT_IFINFTQDISCARDS 0x00001848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) #define BNX2_RPM_STAT_IFINMBUFDISCARD 0x0000184c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) #define BNX2_RPM_STAT_RULE_CHECKER_P4_HIT 0x00001850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0 0x00001854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION0_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1 0x00001858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION1_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2 0x0000185c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION2_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3 0x00001860
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION3_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4 0x00001864
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION4_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5 0x00001868
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION5_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6 0x0000186c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION6_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7 0x00001870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_LEN_TYPE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) #define BNX2_RPM_IPV6_PROGRAMMABLE_EXTENSION7_NEXT_HEADER_EN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) #define BNX2_RPM_STAT_AC0 0x00001880
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) #define BNX2_RPM_STAT_AC1 0x00001884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) #define BNX2_RPM_STAT_AC2 0x00001888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) #define BNX2_RPM_STAT_AC3 0x0000188c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) #define BNX2_RPM_STAT_AC4 0x00001890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) #define BNX2_RPM_RC_CNTL_16 0x000018e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) #define BNX2_RPM_RC_CNTL_16_OFFSET (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) #define BNX2_RPM_RC_CNTL_16_CLASS (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) #define BNX2_RPM_RC_CNTL_16_PRIORITY (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) #define BNX2_RPM_RC_CNTL_16_P4 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_START (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_IP (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_UDP (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_DATA (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_TCP_UDP (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) #define BNX2_RPM_RC_CNTL_16_HDR_TYPE_ICMPV6 (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) #define BNX2_RPM_RC_CNTL_16_COMP (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) #define BNX2_RPM_RC_CNTL_16_COMP_EQUAL (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) #define BNX2_RPM_RC_CNTL_16_COMP_NEQUAL (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) #define BNX2_RPM_RC_CNTL_16_COMP_GREATER (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) #define BNX2_RPM_RC_CNTL_16_COMP_LESS (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) #define BNX2_RPM_RC_CNTL_16_MAP (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) #define BNX2_RPM_RC_CNTL_16_SBIT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) #define BNX2_RPM_RC_CNTL_16_CMDSEL (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) #define BNX2_RPM_RC_CNTL_16_DISCARD (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) #define BNX2_RPM_RC_CNTL_16_MASK (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) #define BNX2_RPM_RC_CNTL_16_P1 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) #define BNX2_RPM_RC_CNTL_16_P2 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) #define BNX2_RPM_RC_CNTL_16_P3 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) #define BNX2_RPM_RC_CNTL_16_NBIT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) #define BNX2_RPM_RC_VALUE_MASK_16 0x000018e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) #define BNX2_RPM_RC_VALUE_MASK_16_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) #define BNX2_RPM_RC_VALUE_MASK_16_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) #define BNX2_RPM_RC_CNTL_17 0x000018e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) #define BNX2_RPM_RC_CNTL_17_OFFSET (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) #define BNX2_RPM_RC_CNTL_17_CLASS (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) #define BNX2_RPM_RC_CNTL_17_PRIORITY (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) #define BNX2_RPM_RC_CNTL_17_P4 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_START (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_IP (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_UDP (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_DATA (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_TCP_UDP (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) #define BNX2_RPM_RC_CNTL_17_HDR_TYPE_ICMPV6 (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) #define BNX2_RPM_RC_CNTL_17_COMP (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) #define BNX2_RPM_RC_CNTL_17_COMP_EQUAL (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) #define BNX2_RPM_RC_CNTL_17_COMP_NEQUAL (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) #define BNX2_RPM_RC_CNTL_17_COMP_GREATER (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) #define BNX2_RPM_RC_CNTL_17_COMP_LESS (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) #define BNX2_RPM_RC_CNTL_17_MAP (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) #define BNX2_RPM_RC_CNTL_17_SBIT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) #define BNX2_RPM_RC_CNTL_17_CMDSEL (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) #define BNX2_RPM_RC_CNTL_17_DISCARD (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) #define BNX2_RPM_RC_CNTL_17_MASK (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) #define BNX2_RPM_RC_CNTL_17_P1 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) #define BNX2_RPM_RC_CNTL_17_P2 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) #define BNX2_RPM_RC_CNTL_17_P3 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) #define BNX2_RPM_RC_CNTL_17_NBIT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) #define BNX2_RPM_RC_VALUE_MASK_17 0x000018ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) #define BNX2_RPM_RC_VALUE_MASK_17_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) #define BNX2_RPM_RC_VALUE_MASK_17_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) #define BNX2_RPM_RC_CNTL_18 0x000018f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) #define BNX2_RPM_RC_CNTL_18_OFFSET (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #define BNX2_RPM_RC_CNTL_18_CLASS (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) #define BNX2_RPM_RC_CNTL_18_PRIORITY (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) #define BNX2_RPM_RC_CNTL_18_P4 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_START (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_IP (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_UDP (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_DATA (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_TCP_UDP (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) #define BNX2_RPM_RC_CNTL_18_HDR_TYPE_ICMPV6 (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) #define BNX2_RPM_RC_CNTL_18_COMP (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) #define BNX2_RPM_RC_CNTL_18_COMP_EQUAL (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) #define BNX2_RPM_RC_CNTL_18_COMP_NEQUAL (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) #define BNX2_RPM_RC_CNTL_18_COMP_GREATER (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) #define BNX2_RPM_RC_CNTL_18_COMP_LESS (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) #define BNX2_RPM_RC_CNTL_18_MAP (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) #define BNX2_RPM_RC_CNTL_18_SBIT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) #define BNX2_RPM_RC_CNTL_18_CMDSEL (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) #define BNX2_RPM_RC_CNTL_18_DISCARD (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) #define BNX2_RPM_RC_CNTL_18_MASK (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) #define BNX2_RPM_RC_CNTL_18_P1 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) #define BNX2_RPM_RC_CNTL_18_P2 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) #define BNX2_RPM_RC_CNTL_18_P3 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) #define BNX2_RPM_RC_CNTL_18_NBIT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) #define BNX2_RPM_RC_VALUE_MASK_18 0x000018f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) #define BNX2_RPM_RC_VALUE_MASK_18_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) #define BNX2_RPM_RC_VALUE_MASK_18_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) #define BNX2_RPM_RC_CNTL_19 0x000018f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) #define BNX2_RPM_RC_CNTL_19_OFFSET (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) #define BNX2_RPM_RC_CNTL_19_CLASS (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) #define BNX2_RPM_RC_CNTL_19_PRIORITY (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) #define BNX2_RPM_RC_CNTL_19_P4 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_START (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_IP (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_UDP (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_DATA (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_TCP_UDP (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) #define BNX2_RPM_RC_CNTL_19_HDR_TYPE_ICMPV6 (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) #define BNX2_RPM_RC_CNTL_19_COMP (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) #define BNX2_RPM_RC_CNTL_19_COMP_EQUAL (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) #define BNX2_RPM_RC_CNTL_19_COMP_NEQUAL (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) #define BNX2_RPM_RC_CNTL_19_COMP_GREATER (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) #define BNX2_RPM_RC_CNTL_19_COMP_LESS (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) #define BNX2_RPM_RC_CNTL_19_MAP (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) #define BNX2_RPM_RC_CNTL_19_SBIT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) #define BNX2_RPM_RC_CNTL_19_CMDSEL (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) #define BNX2_RPM_RC_CNTL_19_DISCARD (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) #define BNX2_RPM_RC_CNTL_19_MASK (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) #define BNX2_RPM_RC_CNTL_19_P1 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) #define BNX2_RPM_RC_CNTL_19_P2 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) #define BNX2_RPM_RC_CNTL_19_P3 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) #define BNX2_RPM_RC_CNTL_19_NBIT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) #define BNX2_RPM_RC_VALUE_MASK_19 0x000018fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) #define BNX2_RPM_RC_VALUE_MASK_19_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) #define BNX2_RPM_RC_VALUE_MASK_19_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) #define BNX2_RPM_RC_CNTL_0 0x00001900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) #define BNX2_RPM_RC_CNTL_0_OFFSET (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) #define BNX2_RPM_RC_CNTL_0_CLASS (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) #define BNX2_RPM_RC_CNTL_0_PRIORITY (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) #define BNX2_RPM_RC_CNTL_0_P4 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_START (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_IP (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_UDP (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_DATA (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_TCP_UDP (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) #define BNX2_RPM_RC_CNTL_0_HDR_TYPE_ICMPV6 (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) #define BNX2_RPM_RC_CNTL_0_COMP (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) #define BNX2_RPM_RC_CNTL_0_COMP_EQUAL (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) #define BNX2_RPM_RC_CNTL_0_COMP_NEQUAL (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) #define BNX2_RPM_RC_CNTL_0_COMP_GREATER (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) #define BNX2_RPM_RC_CNTL_0_COMP_LESS (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) #define BNX2_RPM_RC_CNTL_0_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) #define BNX2_RPM_RC_CNTL_0_SBIT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) #define BNX2_RPM_RC_CNTL_0_CMDSEL (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) #define BNX2_RPM_RC_CNTL_0_MAP (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) #define BNX2_RPM_RC_CNTL_0_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) #define BNX2_RPM_RC_CNTL_0_DISCARD (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) #define BNX2_RPM_RC_CNTL_0_MASK (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) #define BNX2_RPM_RC_CNTL_0_P1 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) #define BNX2_RPM_RC_CNTL_0_P2 (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) #define BNX2_RPM_RC_CNTL_0_P3 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) #define BNX2_RPM_RC_CNTL_0_NBIT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) #define BNX2_RPM_RC_VALUE_MASK_0 0x00001904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) #define BNX2_RPM_RC_VALUE_MASK_0_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) #define BNX2_RPM_RC_VALUE_MASK_0_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) #define BNX2_RPM_RC_CNTL_1 0x00001908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) #define BNX2_RPM_RC_CNTL_1_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) #define BNX2_RPM_RC_CNTL_1_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) #define BNX2_RPM_RC_CNTL_1_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) #define BNX2_RPM_RC_CNTL_1_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) #define BNX2_RPM_RC_CNTL_1_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) #define BNX2_RPM_RC_CNTL_1_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) #define BNX2_RPM_RC_CNTL_1_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) #define BNX2_RPM_RC_CNTL_1_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) #define BNX2_RPM_RC_CNTL_1_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) #define BNX2_RPM_RC_CNTL_1_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) #define BNX2_RPM_RC_CNTL_1_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) #define BNX2_RPM_RC_CNTL_1_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) #define BNX2_RPM_RC_CNTL_1_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) #define BNX2_RPM_RC_CNTL_1_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) #define BNX2_RPM_RC_CNTL_1_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) #define BNX2_RPM_RC_CNTL_1_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) #define BNX2_RPM_RC_CNTL_1_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) #define BNX2_RPM_RC_CNTL_1_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) #define BNX2_RPM_RC_CNTL_1_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) #define BNX2_RPM_RC_CNTL_1_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) #define BNX2_RPM_RC_CNTL_1_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) #define BNX2_RPM_RC_VALUE_MASK_1 0x0000190c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) #define BNX2_RPM_RC_VALUE_MASK_1_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) #define BNX2_RPM_RC_VALUE_MASK_1_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) #define BNX2_RPM_RC_CNTL_2 0x00001910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) #define BNX2_RPM_RC_CNTL_2_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) #define BNX2_RPM_RC_CNTL_2_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) #define BNX2_RPM_RC_CNTL_2_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) #define BNX2_RPM_RC_CNTL_2_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) #define BNX2_RPM_RC_CNTL_2_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) #define BNX2_RPM_RC_CNTL_2_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) #define BNX2_RPM_RC_CNTL_2_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) #define BNX2_RPM_RC_CNTL_2_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) #define BNX2_RPM_RC_CNTL_2_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) #define BNX2_RPM_RC_CNTL_2_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) #define BNX2_RPM_RC_CNTL_2_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) #define BNX2_RPM_RC_CNTL_2_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) #define BNX2_RPM_RC_CNTL_2_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) #define BNX2_RPM_RC_CNTL_2_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) #define BNX2_RPM_RC_CNTL_2_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) #define BNX2_RPM_RC_CNTL_2_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) #define BNX2_RPM_RC_CNTL_2_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) #define BNX2_RPM_RC_CNTL_2_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) #define BNX2_RPM_RC_CNTL_2_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) #define BNX2_RPM_RC_CNTL_2_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) #define BNX2_RPM_RC_CNTL_2_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) #define BNX2_RPM_RC_VALUE_MASK_2 0x00001914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) #define BNX2_RPM_RC_VALUE_MASK_2_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) #define BNX2_RPM_RC_VALUE_MASK_2_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) #define BNX2_RPM_RC_CNTL_3 0x00001918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) #define BNX2_RPM_RC_CNTL_3_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) #define BNX2_RPM_RC_CNTL_3_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) #define BNX2_RPM_RC_CNTL_3_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) #define BNX2_RPM_RC_CNTL_3_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) #define BNX2_RPM_RC_CNTL_3_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) #define BNX2_RPM_RC_CNTL_3_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) #define BNX2_RPM_RC_CNTL_3_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) #define BNX2_RPM_RC_CNTL_3_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) #define BNX2_RPM_RC_CNTL_3_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) #define BNX2_RPM_RC_CNTL_3_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) #define BNX2_RPM_RC_CNTL_3_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) #define BNX2_RPM_RC_CNTL_3_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) #define BNX2_RPM_RC_CNTL_3_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) #define BNX2_RPM_RC_CNTL_3_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) #define BNX2_RPM_RC_CNTL_3_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) #define BNX2_RPM_RC_CNTL_3_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) #define BNX2_RPM_RC_CNTL_3_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) #define BNX2_RPM_RC_CNTL_3_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) #define BNX2_RPM_RC_CNTL_3_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) #define BNX2_RPM_RC_CNTL_3_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) #define BNX2_RPM_RC_CNTL_3_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) #define BNX2_RPM_RC_VALUE_MASK_3 0x0000191c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) #define BNX2_RPM_RC_VALUE_MASK_3_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) #define BNX2_RPM_RC_VALUE_MASK_3_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) #define BNX2_RPM_RC_CNTL_4 0x00001920
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) #define BNX2_RPM_RC_CNTL_4_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) #define BNX2_RPM_RC_CNTL_4_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) #define BNX2_RPM_RC_CNTL_4_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) #define BNX2_RPM_RC_CNTL_4_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) #define BNX2_RPM_RC_CNTL_4_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) #define BNX2_RPM_RC_CNTL_4_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) #define BNX2_RPM_RC_CNTL_4_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) #define BNX2_RPM_RC_CNTL_4_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) #define BNX2_RPM_RC_CNTL_4_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) #define BNX2_RPM_RC_CNTL_4_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) #define BNX2_RPM_RC_CNTL_4_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) #define BNX2_RPM_RC_CNTL_4_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) #define BNX2_RPM_RC_CNTL_4_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) #define BNX2_RPM_RC_CNTL_4_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) #define BNX2_RPM_RC_CNTL_4_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) #define BNX2_RPM_RC_CNTL_4_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) #define BNX2_RPM_RC_CNTL_4_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) #define BNX2_RPM_RC_CNTL_4_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) #define BNX2_RPM_RC_CNTL_4_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) #define BNX2_RPM_RC_CNTL_4_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) #define BNX2_RPM_RC_CNTL_4_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) #define BNX2_RPM_RC_VALUE_MASK_4 0x00001924
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) #define BNX2_RPM_RC_VALUE_MASK_4_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) #define BNX2_RPM_RC_VALUE_MASK_4_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) #define BNX2_RPM_RC_CNTL_5 0x00001928
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) #define BNX2_RPM_RC_CNTL_5_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) #define BNX2_RPM_RC_CNTL_5_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) #define BNX2_RPM_RC_CNTL_5_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) #define BNX2_RPM_RC_CNTL_5_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) #define BNX2_RPM_RC_CNTL_5_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) #define BNX2_RPM_RC_CNTL_5_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) #define BNX2_RPM_RC_CNTL_5_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) #define BNX2_RPM_RC_CNTL_5_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) #define BNX2_RPM_RC_CNTL_5_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) #define BNX2_RPM_RC_CNTL_5_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) #define BNX2_RPM_RC_CNTL_5_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) #define BNX2_RPM_RC_CNTL_5_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) #define BNX2_RPM_RC_CNTL_5_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) #define BNX2_RPM_RC_CNTL_5_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) #define BNX2_RPM_RC_CNTL_5_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) #define BNX2_RPM_RC_CNTL_5_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) #define BNX2_RPM_RC_CNTL_5_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) #define BNX2_RPM_RC_CNTL_5_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) #define BNX2_RPM_RC_CNTL_5_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584) #define BNX2_RPM_RC_CNTL_5_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) #define BNX2_RPM_RC_CNTL_5_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) #define BNX2_RPM_RC_VALUE_MASK_5 0x0000192c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) #define BNX2_RPM_RC_VALUE_MASK_5_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) #define BNX2_RPM_RC_VALUE_MASK_5_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) #define BNX2_RPM_RC_CNTL_6 0x00001930
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) #define BNX2_RPM_RC_CNTL_6_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) #define BNX2_RPM_RC_CNTL_6_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) #define BNX2_RPM_RC_CNTL_6_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) #define BNX2_RPM_RC_CNTL_6_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) #define BNX2_RPM_RC_CNTL_6_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) #define BNX2_RPM_RC_CNTL_6_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) #define BNX2_RPM_RC_CNTL_6_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) #define BNX2_RPM_RC_CNTL_6_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) #define BNX2_RPM_RC_CNTL_6_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) #define BNX2_RPM_RC_CNTL_6_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609) #define BNX2_RPM_RC_CNTL_6_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) #define BNX2_RPM_RC_CNTL_6_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) #define BNX2_RPM_RC_CNTL_6_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) #define BNX2_RPM_RC_CNTL_6_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) #define BNX2_RPM_RC_CNTL_6_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) #define BNX2_RPM_RC_CNTL_6_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) #define BNX2_RPM_RC_CNTL_6_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) #define BNX2_RPM_RC_CNTL_6_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) #define BNX2_RPM_RC_CNTL_6_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) #define BNX2_RPM_RC_CNTL_6_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) #define BNX2_RPM_RC_CNTL_6_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) #define BNX2_RPM_RC_VALUE_MASK_6 0x00001934
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) #define BNX2_RPM_RC_VALUE_MASK_6_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) #define BNX2_RPM_RC_VALUE_MASK_6_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) #define BNX2_RPM_RC_CNTL_7 0x00001938
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626) #define BNX2_RPM_RC_CNTL_7_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) #define BNX2_RPM_RC_CNTL_7_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) #define BNX2_RPM_RC_CNTL_7_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) #define BNX2_RPM_RC_CNTL_7_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) #define BNX2_RPM_RC_CNTL_7_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) #define BNX2_RPM_RC_CNTL_7_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) #define BNX2_RPM_RC_CNTL_7_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) #define BNX2_RPM_RC_CNTL_7_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641) #define BNX2_RPM_RC_CNTL_7_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) #define BNX2_RPM_RC_CNTL_7_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) #define BNX2_RPM_RC_CNTL_7_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) #define BNX2_RPM_RC_CNTL_7_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) #define BNX2_RPM_RC_CNTL_7_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) #define BNX2_RPM_RC_CNTL_7_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) #define BNX2_RPM_RC_CNTL_7_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) #define BNX2_RPM_RC_CNTL_7_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) #define BNX2_RPM_RC_CNTL_7_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) #define BNX2_RPM_RC_CNTL_7_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) #define BNX2_RPM_RC_CNTL_7_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) #define BNX2_RPM_RC_CNTL_7_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) #define BNX2_RPM_RC_CNTL_7_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655) #define BNX2_RPM_RC_VALUE_MASK_7 0x0000193c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) #define BNX2_RPM_RC_VALUE_MASK_7_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) #define BNX2_RPM_RC_VALUE_MASK_7_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) #define BNX2_RPM_RC_CNTL_8 0x00001940
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) #define BNX2_RPM_RC_CNTL_8_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) #define BNX2_RPM_RC_CNTL_8_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) #define BNX2_RPM_RC_CNTL_8_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) #define BNX2_RPM_RC_CNTL_8_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) #define BNX2_RPM_RC_CNTL_8_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) #define BNX2_RPM_RC_CNTL_8_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) #define BNX2_RPM_RC_CNTL_8_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) #define BNX2_RPM_RC_CNTL_8_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) #define BNX2_RPM_RC_CNTL_8_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) #define BNX2_RPM_RC_CNTL_8_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) #define BNX2_RPM_RC_CNTL_8_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) #define BNX2_RPM_RC_CNTL_8_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) #define BNX2_RPM_RC_CNTL_8_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) #define BNX2_RPM_RC_CNTL_8_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) #define BNX2_RPM_RC_CNTL_8_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) #define BNX2_RPM_RC_CNTL_8_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683) #define BNX2_RPM_RC_CNTL_8_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) #define BNX2_RPM_RC_CNTL_8_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) #define BNX2_RPM_RC_CNTL_8_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) #define BNX2_RPM_RC_CNTL_8_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) #define BNX2_RPM_RC_CNTL_8_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) #define BNX2_RPM_RC_VALUE_MASK_8 0x00001944
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) #define BNX2_RPM_RC_VALUE_MASK_8_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691) #define BNX2_RPM_RC_VALUE_MASK_8_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) #define BNX2_RPM_RC_CNTL_9 0x00001948
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) #define BNX2_RPM_RC_CNTL_9_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) #define BNX2_RPM_RC_CNTL_9_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) #define BNX2_RPM_RC_CNTL_9_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) #define BNX2_RPM_RC_CNTL_9_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) #define BNX2_RPM_RC_CNTL_9_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) #define BNX2_RPM_RC_CNTL_9_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) #define BNX2_RPM_RC_CNTL_9_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708) #define BNX2_RPM_RC_CNTL_9_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) #define BNX2_RPM_RC_CNTL_9_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) #define BNX2_RPM_RC_CNTL_9_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) #define BNX2_RPM_RC_CNTL_9_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) #define BNX2_RPM_RC_CNTL_9_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) #define BNX2_RPM_RC_CNTL_9_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714) #define BNX2_RPM_RC_CNTL_9_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) #define BNX2_RPM_RC_CNTL_9_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) #define BNX2_RPM_RC_CNTL_9_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) #define BNX2_RPM_RC_CNTL_9_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) #define BNX2_RPM_RC_CNTL_9_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) #define BNX2_RPM_RC_CNTL_9_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) #define BNX2_RPM_RC_CNTL_9_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) #define BNX2_RPM_RC_CNTL_9_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) #define BNX2_RPM_RC_VALUE_MASK_9 0x0000194c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) #define BNX2_RPM_RC_VALUE_MASK_9_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) #define BNX2_RPM_RC_VALUE_MASK_9_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) #define BNX2_RPM_RC_CNTL_10 0x00001950
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) #define BNX2_RPM_RC_CNTL_10_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729) #define BNX2_RPM_RC_CNTL_10_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) #define BNX2_RPM_RC_CNTL_10_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) #define BNX2_RPM_RC_CNTL_10_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) #define BNX2_RPM_RC_CNTL_10_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) #define BNX2_RPM_RC_CNTL_10_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) #define BNX2_RPM_RC_CNTL_10_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) #define BNX2_RPM_RC_CNTL_10_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) #define BNX2_RPM_RC_CNTL_10_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) #define BNX2_RPM_RC_CNTL_10_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) #define BNX2_RPM_RC_CNTL_10_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) #define BNX2_RPM_RC_CNTL_10_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) #define BNX2_RPM_RC_CNTL_10_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) #define BNX2_RPM_RC_CNTL_10_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) #define BNX2_RPM_RC_CNTL_10_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) #define BNX2_RPM_RC_CNTL_10_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) #define BNX2_RPM_RC_CNTL_10_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) #define BNX2_RPM_RC_CNTL_10_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) #define BNX2_RPM_RC_CNTL_10_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) #define BNX2_RPM_RC_CNTL_10_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) #define BNX2_RPM_RC_CNTL_10_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) #define BNX2_RPM_RC_VALUE_MASK_10 0x00001954
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) #define BNX2_RPM_RC_VALUE_MASK_10_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) #define BNX2_RPM_RC_VALUE_MASK_10_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) #define BNX2_RPM_RC_CNTL_11 0x00001958
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) #define BNX2_RPM_RC_CNTL_11_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) #define BNX2_RPM_RC_CNTL_11_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) #define BNX2_RPM_RC_CNTL_11_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) #define BNX2_RPM_RC_CNTL_11_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) #define BNX2_RPM_RC_CNTL_11_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) #define BNX2_RPM_RC_CNTL_11_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) #define BNX2_RPM_RC_CNTL_11_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) #define BNX2_RPM_RC_CNTL_11_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) #define BNX2_RPM_RC_CNTL_11_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) #define BNX2_RPM_RC_CNTL_11_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) #define BNX2_RPM_RC_CNTL_11_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) #define BNX2_RPM_RC_CNTL_11_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) #define BNX2_RPM_RC_CNTL_11_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) #define BNX2_RPM_RC_CNTL_11_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) #define BNX2_RPM_RC_CNTL_11_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) #define BNX2_RPM_RC_CNTL_11_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) #define BNX2_RPM_RC_CNTL_11_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) #define BNX2_RPM_RC_CNTL_11_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) #define BNX2_RPM_RC_CNTL_11_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) #define BNX2_RPM_RC_CNTL_11_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) #define BNX2_RPM_RC_CNTL_11_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) #define BNX2_RPM_RC_VALUE_MASK_11 0x0000195c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) #define BNX2_RPM_RC_VALUE_MASK_11_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) #define BNX2_RPM_RC_VALUE_MASK_11_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) #define BNX2_RPM_RC_CNTL_12 0x00001960
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) #define BNX2_RPM_RC_CNTL_12_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) #define BNX2_RPM_RC_CNTL_12_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) #define BNX2_RPM_RC_CNTL_12_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) #define BNX2_RPM_RC_CNTL_12_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) #define BNX2_RPM_RC_CNTL_12_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) #define BNX2_RPM_RC_CNTL_12_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) #define BNX2_RPM_RC_CNTL_12_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) #define BNX2_RPM_RC_CNTL_12_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) #define BNX2_RPM_RC_CNTL_12_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) #define BNX2_RPM_RC_CNTL_12_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) #define BNX2_RPM_RC_CNTL_12_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) #define BNX2_RPM_RC_CNTL_12_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) #define BNX2_RPM_RC_CNTL_12_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) #define BNX2_RPM_RC_CNTL_12_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) #define BNX2_RPM_RC_CNTL_12_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) #define BNX2_RPM_RC_CNTL_12_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819) #define BNX2_RPM_RC_CNTL_12_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) #define BNX2_RPM_RC_CNTL_12_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) #define BNX2_RPM_RC_CNTL_12_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) #define BNX2_RPM_RC_CNTL_12_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) #define BNX2_RPM_RC_CNTL_12_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) #define BNX2_RPM_RC_VALUE_MASK_12 0x00001964
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) #define BNX2_RPM_RC_VALUE_MASK_12_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) #define BNX2_RPM_RC_VALUE_MASK_12_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) #define BNX2_RPM_RC_CNTL_13 0x00001968
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) #define BNX2_RPM_RC_CNTL_13_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) #define BNX2_RPM_RC_CNTL_13_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) #define BNX2_RPM_RC_CNTL_13_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) #define BNX2_RPM_RC_CNTL_13_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) #define BNX2_RPM_RC_CNTL_13_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) #define BNX2_RPM_RC_CNTL_13_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) #define BNX2_RPM_RC_CNTL_13_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) #define BNX2_RPM_RC_CNTL_13_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) #define BNX2_RPM_RC_CNTL_13_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846) #define BNX2_RPM_RC_CNTL_13_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) #define BNX2_RPM_RC_CNTL_13_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) #define BNX2_RPM_RC_CNTL_13_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) #define BNX2_RPM_RC_CNTL_13_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) #define BNX2_RPM_RC_CNTL_13_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) #define BNX2_RPM_RC_CNTL_13_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852) #define BNX2_RPM_RC_CNTL_13_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) #define BNX2_RPM_RC_CNTL_13_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) #define BNX2_RPM_RC_CNTL_13_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) #define BNX2_RPM_RC_CNTL_13_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) #define BNX2_RPM_RC_CNTL_13_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) #define BNX2_RPM_RC_CNTL_13_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) #define BNX2_RPM_RC_VALUE_MASK_13 0x0000196c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) #define BNX2_RPM_RC_VALUE_MASK_13_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) #define BNX2_RPM_RC_VALUE_MASK_13_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) #define BNX2_RPM_RC_CNTL_14 0x00001970
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) #define BNX2_RPM_RC_CNTL_14_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) #define BNX2_RPM_RC_CNTL_14_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) #define BNX2_RPM_RC_CNTL_14_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) #define BNX2_RPM_RC_CNTL_14_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) #define BNX2_RPM_RC_CNTL_14_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) #define BNX2_RPM_RC_CNTL_14_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) #define BNX2_RPM_RC_CNTL_14_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) #define BNX2_RPM_RC_CNTL_14_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) #define BNX2_RPM_RC_CNTL_14_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) #define BNX2_RPM_RC_CNTL_14_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) #define BNX2_RPM_RC_CNTL_14_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) #define BNX2_RPM_RC_CNTL_14_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) #define BNX2_RPM_RC_CNTL_14_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) #define BNX2_RPM_RC_CNTL_14_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) #define BNX2_RPM_RC_CNTL_14_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) #define BNX2_RPM_RC_CNTL_14_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) #define BNX2_RPM_RC_CNTL_14_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) #define BNX2_RPM_RC_CNTL_14_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) #define BNX2_RPM_RC_CNTL_14_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) #define BNX2_RPM_RC_CNTL_14_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) #define BNX2_RPM_RC_CNTL_14_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) #define BNX2_RPM_RC_VALUE_MASK_14 0x00001974
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894) #define BNX2_RPM_RC_VALUE_MASK_14_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) #define BNX2_RPM_RC_VALUE_MASK_14_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) #define BNX2_RPM_RC_CNTL_15 0x00001978
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) #define BNX2_RPM_RC_CNTL_15_A (0x3ffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) #define BNX2_RPM_RC_CNTL_15_B (0xfffL<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) #define BNX2_RPM_RC_CNTL_15_OFFSET_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) #define BNX2_RPM_RC_CNTL_15_CLASS_XI (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) #define BNX2_RPM_RC_CNTL_15_PRIORITY_XI (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) #define BNX2_RPM_RC_CNTL_15_P4_XI (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_START_XI (0L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_IP_XI (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_XI (2L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_UDP_XI (3L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_DATA_XI (4L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_TCP_UDP_XI (5L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) #define BNX2_RPM_RC_CNTL_15_HDR_TYPE_ICMPV6_XI (6L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) #define BNX2_RPM_RC_CNTL_15_COMP_XI (0x3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913) #define BNX2_RPM_RC_CNTL_15_COMP_EQUAL_XI (0L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) #define BNX2_RPM_RC_CNTL_15_COMP_NEQUAL_XI (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) #define BNX2_RPM_RC_CNTL_15_COMP_GREATER_XI (2L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) #define BNX2_RPM_RC_CNTL_15_COMP_LESS_XI (3L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) #define BNX2_RPM_RC_CNTL_15_MAP_XI (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) #define BNX2_RPM_RC_CNTL_15_SBIT_XI (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) #define BNX2_RPM_RC_CNTL_15_CMDSEL_XI (0x1fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) #define BNX2_RPM_RC_CNTL_15_DISCARD_XI (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) #define BNX2_RPM_RC_CNTL_15_MASK_XI (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) #define BNX2_RPM_RC_CNTL_15_P1_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) #define BNX2_RPM_RC_CNTL_15_P2_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) #define BNX2_RPM_RC_CNTL_15_P3_XI (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) #define BNX2_RPM_RC_CNTL_15_NBIT_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) #define BNX2_RPM_RC_VALUE_MASK_15 0x0000197c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) #define BNX2_RPM_RC_VALUE_MASK_15_VALUE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) #define BNX2_RPM_RC_VALUE_MASK_15_MASK (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) #define BNX2_RPM_RC_CONFIG 0x00001980
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) #define BNX2_RPM_RC_CONFIG_RULE_ENABLE (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) #define BNX2_RPM_RC_CONFIG_RULE_ENABLE_XI (0xfffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) #define BNX2_RPM_RC_CONFIG_DEF_CLASS (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935) #define BNX2_RPM_RC_CONFIG_KNUM_OVERWRITE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) #define BNX2_RPM_DEBUG0 0x00001984
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) #define BNX2_RPM_DEBUG0_FM_BCNT (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) #define BNX2_RPM_DEBUG0_T_DATA_OFST_VLD (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940) #define BNX2_RPM_DEBUG0_T_UDP_OFST_VLD (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) #define BNX2_RPM_DEBUG0_T_TCP_OFST_VLD (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) #define BNX2_RPM_DEBUG0_T_IP_OFST_VLD (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) #define BNX2_RPM_DEBUG0_IP_MORE_FRGMT (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) #define BNX2_RPM_DEBUG0_T_IP_NO_TCP_UDP_HDR (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) #define BNX2_RPM_DEBUG0_LLC_SNAP (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) #define BNX2_RPM_DEBUG0_FM_STARTED (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) #define BNX2_RPM_DEBUG0_DONE (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) #define BNX2_RPM_DEBUG0_WAIT_4_DONE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) #define BNX2_RPM_DEBUG0_USE_TPBUF_CKSUM (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) #define BNX2_RPM_DEBUG0_RX_NO_PSD_HDR_CKSUM (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) #define BNX2_RPM_DEBUG0_IGNORE_VLAN (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) #define BNX2_RPM_DEBUG0_RP_ENA_ACTIVE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) #define BNX2_RPM_DEBUG1 0x00001988
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955) #define BNX2_RPM_DEBUG1_FSM_CUR_ST (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IDLE (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_ALL (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IPLLC (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B6_IP (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ETYPE_B2_IP (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP_START (16L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_IP (32L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_TCP (64L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_UDP (128L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_AH (256L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP (512L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ESP_PAYLOAD (1024L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_DATA (2048L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRY (0x2000L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_ADD_CARRYOUT (0x4000L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) #define BNX2_RPM_DEBUG1_FSM_CUR_ST_LATCH_RESULT (0x8000L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) #define BNX2_RPM_DEBUG1_HDR_BCNT (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) #define BNX2_RPM_DEBUG1_UNKNOWN_ETYPE_D (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D2 (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) #define BNX2_RPM_DEBUG1_VLAN_REMOVED_D1 (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) #define BNX2_RPM_DEBUG1_EOF_0XTRA_WD (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) #define BNX2_RPM_DEBUG2 0x0000198c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) #define BNX2_RPM_DEBUG2_CMD_HIT_VEC (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) #define BNX2_RPM_DEBUG2_IP_BCNT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) #define BNX2_RPM_DEBUG2_THIS_CMD_M4 (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) #define BNX2_RPM_DEBUG2_THIS_CMD_M3 (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) #define BNX2_RPM_DEBUG2_THIS_CMD_M2 (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) #define BNX2_RPM_DEBUG2_THIS_CMD_M1 (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) #define BNX2_RPM_DEBUG2_IPIPE_EMPTY (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) #define BNX2_RPM_DEBUG2_FM_DISCARD (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D2 (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) #define BNX2_RPM_DEBUG2_LAST_RULE_IN_FM_D1 (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) #define BNX2_RPM_DEBUG3 0x00001990
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) #define BNX2_RPM_DEBUG3_AVAIL_MBUF_PTR (0x1ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) #define BNX2_RPM_DEBUG3_RDE_RLUPQ_WR_REQ_INT (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_LAST_INT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) #define BNX2_RPM_DEBUG3_RDE_RBUF_WR_REQ_INT (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) #define BNX2_RPM_DEBUG3_RDE_RBUF_FREE_REQ (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) #define BNX2_RPM_DEBUG3_RDE_RBUF_ALLOC_REQ (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) #define BNX2_RPM_DEBUG3_DFSM_MBUF_NOTAVAIL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) #define BNX2_RPM_DEBUG3_RBUF_RDE_SOF_DROP (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) #define BNX2_RPM_DEBUG3_DFIFO_VLD_ENTRY_CT (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) #define BNX2_RPM_DEBUG3_RDE_SRC_FIFO_ALMFULL (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) #define BNX2_RPM_DEBUG3_DROP_NXT_VLD (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) #define BNX2_RPM_DEBUG3_DROP_NXT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) #define BNX2_RPM_DEBUG3_FTQ_FSM (0x3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) #define BNX2_RPM_DEBUG3_FTQ_FSM_IDLE (0x0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_ACK (0x1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) #define BNX2_RPM_DEBUG3_FTQ_FSM_WAIT_FREE (0x2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) #define BNX2_RPM_DEBUG3_MBWRITE_FSM (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_SOF (0x0L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_GET_MBUF (0x1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DMA_DATA (0x2L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DATA (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_EOF (0x4L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_MF_ACK (0x5L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_WAIT_DROP_NXT_VLD (0x6L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) #define BNX2_RPM_DEBUG3_MBWRITE_FSM_DONE (0x7L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) #define BNX2_RPM_DEBUG3_MBFREE_FSM (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) #define BNX2_RPM_DEBUG3_MBFREE_FSM_IDLE (0L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) #define BNX2_RPM_DEBUG3_MBFREE_FSM_WAIT_ACK (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) #define BNX2_RPM_DEBUG3_MBALLOC_FSM (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) #define BNX2_RPM_DEBUG3_MBALLOC_FSM_ET_MBUF (0x0L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) #define BNX2_RPM_DEBUG3_MBALLOC_FSM_IVE_MBUF (0x1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) #define BNX2_RPM_DEBUG3_CCODE_EOF_ERROR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) #define BNX2_RPM_DEBUG4 0x00001994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) #define BNX2_RPM_DEBUG4_DFSM_MBUF_CLUSTER (0x1ffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) #define BNX2_RPM_DEBUG4_DFIFO_CUR_CCODE (0x7L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) #define BNX2_RPM_DEBUG4_MBWRITE_FSM (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) #define BNX2_RPM_DEBUG4_DFIFO_EMPTY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) #define BNX2_RPM_DEBUG5 0x00001998
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) #define BNX2_RPM_DEBUG5_RDROP_WPTR (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) #define BNX2_RPM_DEBUG5_RDROP_ACPI_RPTR (0x1fL<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) #define BNX2_RPM_DEBUG5_RDROP_MC_RPTR (0x1fL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) #define BNX2_RPM_DEBUG5_RDROP_RC_RPTR (0x1fL<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) #define BNX2_RPM_DEBUG5_RDROP_ACPI_EMPTY (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) #define BNX2_RPM_DEBUG5_RDROP_MC_EMPTY (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) #define BNX2_RPM_DEBUG5_RDROP_AEOF_VEC_AT_RDROP_MC_RPTR (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) #define BNX2_RPM_DEBUG5_HOLDREG_WOL_DROP_INT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) #define BNX2_RPM_DEBUG5_HOLDREG_DISCARD (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) #define BNX2_RPM_DEBUG5_HOLDREG_MBUF_NOTAVAIL (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) #define BNX2_RPM_DEBUG5_HOLDREG_MC_EMPTY (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) #define BNX2_RPM_DEBUG5_HOLDREG_RC_EMPTY (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) #define BNX2_RPM_DEBUG5_HOLDREG_FC_EMPTY (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) #define BNX2_RPM_DEBUG5_HOLDREG_ACPI_EMPTY (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) #define BNX2_RPM_DEBUG5_HOLDREG_FULL_T (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) #define BNX2_RPM_DEBUG5_HOLDREG_RD (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) #define BNX2_RPM_DEBUG6 0x0000199c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) #define BNX2_RPM_DEBUG6_ACPI_VEC (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) #define BNX2_RPM_DEBUG6_VEC (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) #define BNX2_RPM_DEBUG7 0x000019a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) #define BNX2_RPM_DEBUG7_RPM_DBG7_LAST_CRC (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) #define BNX2_RPM_DEBUG8 0x000019a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_IDLE (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W1_ADDR (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W2_ADDR (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_W3_ADDR (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_SOF_WAIT_THBUF (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_DATA (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W0_ADDR (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W1_ADDR (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W2_ADDR (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_W3_ADDR (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) #define BNX2_RPM_DEBUG8_PS_ACPI_FSM_WAIT_THBUF (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068) #define BNX2_RPM_DEBUG8_COMPARE_AT_W0 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) #define BNX2_RPM_DEBUG8_COMPARE_AT_W3_DATA (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070) #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_WAIT (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W3 (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072) #define BNX2_RPM_DEBUG8_COMPARE_AT_SOF_W2 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) #define BNX2_RPM_DEBUG8_EOF_W_LTEQ6_VLDBYTES (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) #define BNX2_RPM_DEBUG8_EOF_W_LTEQ4_VLDBYTES (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) #define BNX2_RPM_DEBUG8_NXT_EOF_W_12_VLDBYTES (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) #define BNX2_RPM_DEBUG8_EOF_DET (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) #define BNX2_RPM_DEBUG8_SOF_DET (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) #define BNX2_RPM_DEBUG8_WAIT_4_SOF (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) #define BNX2_RPM_DEBUG8_ALL_DONE (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) #define BNX2_RPM_DEBUG8_THBUF_ADDR (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) #define BNX2_RPM_DEBUG8_BYTE_CTR (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) #define BNX2_RPM_DEBUG9 0x000019a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) #define BNX2_RPM_DEBUG9_OUTFIFO_COUNT (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) #define BNX2_RPM_DEBUG9_RDE_ACPI_RDY (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) #define BNX2_RPM_DEBUG9_VLD_RD_ENTRY_CT (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) #define BNX2_RPM_DEBUG9_OUTFIFO_OVERRUN_OCCURRED (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) #define BNX2_RPM_DEBUG9_INFIFO_OVERRUN_OCCURRED (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089) #define BNX2_RPM_DEBUG9_ACPI_MATCH_INT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090) #define BNX2_RPM_DEBUG9_ACPI_ENABLE_SYN (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) #define BNX2_RPM_DEBUG9_BEMEM_R_XI (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) #define BNX2_RPM_DEBUG9_EO_XI (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) #define BNX2_RPM_DEBUG9_AEOF_DE_XI (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4094) #define BNX2_RPM_DEBUG9_SO_XI (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4095) #define BNX2_RPM_DEBUG9_WD64_CT_XI (0x1fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4096) #define BNX2_RPM_DEBUG9_EOF_VLDBYTE_XI (0x7L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4097) #define BNX2_RPM_DEBUG9_ACPI_RDE_PAT_ID_XI (0xfL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4098) #define BNX2_RPM_DEBUG9_CALCRC_RESULT_XI (0x3ffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4099) #define BNX2_RPM_DEBUG9_DATA_IN_VL_XI (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4100) #define BNX2_RPM_DEBUG9_CALCRC_BUFFER_VLD_XI (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4102) #define BNX2_RPM_ACPI_DBG_BUF_W00 0x000019c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4103) #define BNX2_RPM_ACPI_DBG_BUF_W01 0x000019c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4104) #define BNX2_RPM_ACPI_DBG_BUF_W02 0x000019c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4105) #define BNX2_RPM_ACPI_DBG_BUF_W03 0x000019cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4106) #define BNX2_RPM_ACPI_DBG_BUF_W10 0x000019d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4107) #define BNX2_RPM_ACPI_DBG_BUF_W11 0x000019d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4108) #define BNX2_RPM_ACPI_DBG_BUF_W12 0x000019d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4109) #define BNX2_RPM_ACPI_DBG_BUF_W13 0x000019dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4110) #define BNX2_RPM_ACPI_DBG_BUF_W20 0x000019e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4111) #define BNX2_RPM_ACPI_DBG_BUF_W21 0x000019e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4112) #define BNX2_RPM_ACPI_DBG_BUF_W22 0x000019e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4113) #define BNX2_RPM_ACPI_DBG_BUF_W23 0x000019ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4114) #define BNX2_RPM_ACPI_DBG_BUF_W30 0x000019f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4115) #define BNX2_RPM_ACPI_DBG_BUF_W31 0x000019f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4116) #define BNX2_RPM_ACPI_DBG_BUF_W32 0x000019f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4117) #define BNX2_RPM_ACPI_DBG_BUF_W33 0x000019fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4118) #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL 0x00001a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4119) #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_BYTE_ADDRESS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4120) #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_DEBUGRD (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4121) #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_MODE (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4122) #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_INIT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4123) #define BNX2_RPM_ACPI_BYTE_ENABLE_CTRL_WR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4125) #define BNX2_RPM_ACPI_PATTERN_CTRL 0x00001a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4126) #define BNX2_RPM_ACPI_PATTERN_CTRL_PATTERN_ID (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4127) #define BNX2_RPM_ACPI_PATTERN_CTRL_CRC_SM_CLR (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4128) #define BNX2_RPM_ACPI_PATTERN_CTRL_WR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4130) #define BNX2_RPM_ACPI_DATA 0x00001a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4131) #define BNX2_RPM_ACPI_DATA_PATTERN_BE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4133) #define BNX2_RPM_ACPI_PATTERN_LEN0 0x00001a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4134) #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN3 (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4135) #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN2 (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4136) #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN1 (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4137) #define BNX2_RPM_ACPI_PATTERN_LEN0_PATTERN_LEN0 (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4139) #define BNX2_RPM_ACPI_PATTERN_LEN1 0x00001a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4140) #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN7 (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4141) #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN6 (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4142) #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN5 (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4143) #define BNX2_RPM_ACPI_PATTERN_LEN1_PATTERN_LEN4 (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4145) #define BNX2_RPM_ACPI_PATTERN_CRC0 0x00001a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4146) #define BNX2_RPM_ACPI_PATTERN_CRC0_PATTERN_CRC0 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4148) #define BNX2_RPM_ACPI_PATTERN_CRC1 0x00001a1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4149) #define BNX2_RPM_ACPI_PATTERN_CRC1_PATTERN_CRC1 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4151) #define BNX2_RPM_ACPI_PATTERN_CRC2 0x00001a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4152) #define BNX2_RPM_ACPI_PATTERN_CRC2_PATTERN_CRC2 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4154) #define BNX2_RPM_ACPI_PATTERN_CRC3 0x00001a24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4155) #define BNX2_RPM_ACPI_PATTERN_CRC3_PATTERN_CRC3 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4157) #define BNX2_RPM_ACPI_PATTERN_CRC4 0x00001a28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4158) #define BNX2_RPM_ACPI_PATTERN_CRC4_PATTERN_CRC4 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4160) #define BNX2_RPM_ACPI_PATTERN_CRC5 0x00001a2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4161) #define BNX2_RPM_ACPI_PATTERN_CRC5_PATTERN_CRC5 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4163) #define BNX2_RPM_ACPI_PATTERN_CRC6 0x00001a30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4164) #define BNX2_RPM_ACPI_PATTERN_CRC6_PATTERN_CRC6 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4166) #define BNX2_RPM_ACPI_PATTERN_CRC7 0x00001a34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4167) #define BNX2_RPM_ACPI_PATTERN_CRC7_PATTERN_CRC7 (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4171) * rlup_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4172) * offset: 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4173) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4174) #define BNX2_RLUP_RSS_CONFIG 0x0000201c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4175) #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_XI (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4176) #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_OFF_XI (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4177) #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_ALL_XI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4178) #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_IP_ONLY_XI (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4179) #define BNX2_RLUP_RSS_CONFIG_IPV4_RSS_TYPE_RES_XI (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4180) #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_XI (0x3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4181) #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_OFF_XI (0L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4182) #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_ALL_XI (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4183) #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_IP_ONLY_XI (2L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4184) #define BNX2_RLUP_RSS_CONFIG_IPV6_RSS_TYPE_RES_XI (3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4186) #define BNX2_RLUP_RSS_COMMAND 0x00002048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4187) #define BNX2_RLUP_RSS_COMMAND_RSS_IND_TABLE_ADDR (0xfUL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4188) #define BNX2_RLUP_RSS_COMMAND_RSS_WRITE_MASK (0xffUL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4189) #define BNX2_RLUP_RSS_COMMAND_WRITE (1UL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4190) #define BNX2_RLUP_RSS_COMMAND_READ (1UL<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4191) #define BNX2_RLUP_RSS_COMMAND_HASH_MASK (0x7UL<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4193) #define BNX2_RLUP_RSS_DATA 0x0000204c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4196) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4197) * rbuf_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4198) * offset: 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4200) #define BNX2_RBUF_COMMAND 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4201) #define BNX2_RBUF_COMMAND_ENABLED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4202) #define BNX2_RBUF_COMMAND_FREE_INIT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4203) #define BNX2_RBUF_COMMAND_RAM_INIT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4204) #define BNX2_RBUF_COMMAND_PKT_OFFSET_OVFL (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4205) #define BNX2_RBUF_COMMAND_OVER_FREE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4206) #define BNX2_RBUF_COMMAND_ALLOC_REQ (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4207) #define BNX2_RBUF_COMMAND_EN_PRI_CHNGE_TE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4208) #define BNX2_RBUF_COMMAND_CU_ISOLATE_XI (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4209) #define BNX2_RBUF_COMMAND_EN_PRI_CHANGE_XI (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4210) #define BNX2_RBUF_COMMAND_GRC_ENDIAN_CONV_DIS_XI (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4212) #define BNX2_RBUF_STATUS1 0x00200004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4213) #define BNX2_RBUF_STATUS1_FREE_COUNT (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4215) #define BNX2_RBUF_STATUS2 0x00200008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4216) #define BNX2_RBUF_STATUS2_FREE_TAIL (0x1ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4217) #define BNX2_RBUF_STATUS2_FREE_HEAD (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4219) #define BNX2_RBUF_CONFIG 0x0020000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4220) #define BNX2_RBUF_CONFIG_XOFF_TRIP (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4221) #define BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4222) ((((mtu) - 1500) * 31 / 1000) + 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4223) #define BNX2_RBUF_CONFIG_XON_TRIP (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4224) #define BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4225) ((((mtu) - 1500) * 39 / 1000) + 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4226) #define BNX2_RBUF_CONFIG_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4227) (BNX2_RBUF_CONFIG_XOFF_TRIP_VAL(mtu) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4228) (BNX2_RBUF_CONFIG_XON_TRIP_VAL(mtu) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4230) #define BNX2_RBUF_FW_BUF_ALLOC 0x00200010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4231) #define BNX2_RBUF_FW_BUF_ALLOC_VALUE (0x1ffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4232) #define BNX2_RBUF_FW_BUF_ALLOC_TYPE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4233) #define BNX2_RBUF_FW_BUF_ALLOC_ALLOC_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4235) #define BNX2_RBUF_FW_BUF_FREE 0x00200014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4236) #define BNX2_RBUF_FW_BUF_FREE_COUNT (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4237) #define BNX2_RBUF_FW_BUF_FREE_TAIL (0x1ffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4238) #define BNX2_RBUF_FW_BUF_FREE_HEAD (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4239) #define BNX2_RBUF_FW_BUF_FREE_TYPE (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4240) #define BNX2_RBUF_FW_BUF_FREE_FREE_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4242) #define BNX2_RBUF_FW_BUF_SEL 0x00200018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4243) #define BNX2_RBUF_FW_BUF_SEL_COUNT (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4244) #define BNX2_RBUF_FW_BUF_SEL_TAIL (0x1ffL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4245) #define BNX2_RBUF_FW_BUF_SEL_HEAD (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4246) #define BNX2_RBUF_FW_BUF_SEL_SEL_REQ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4248) #define BNX2_RBUF_CONFIG2 0x0020001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4249) #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4250) #define BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4251) ((((mtu) - 1500) * 4 / 1000) + 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4252) #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4253) #define BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4254) ((((mtu) - 1500) * 2 / 100) + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4255) #define BNX2_RBUF_CONFIG2_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4256) (BNX2_RBUF_CONFIG2_MAC_DROP_TRIP_VAL(mtu) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4257) (BNX2_RBUF_CONFIG2_MAC_KEEP_TRIP_VAL(mtu) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4259) #define BNX2_RBUF_CONFIG3 0x00200020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4260) #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4261) #define BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4262) ((((mtu) - 1500) * 12 / 1000) + 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4263) #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4264) #define BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4265) ((((mtu) - 1500) * 2 / 100) + 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4266) #define BNX2_RBUF_CONFIG3_VAL(mtu) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4267) (BNX2_RBUF_CONFIG3_CU_DROP_TRIP_VAL(mtu) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4268) (BNX2_RBUF_CONFIG3_CU_KEEP_TRIP_VAL(mtu) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4270) #define BNX2_RBUF_PKT_DATA 0x00208000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4271) #define BNX2_RBUF_CLIST_DATA 0x00210000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4272) #define BNX2_RBUF_BUF_DATA 0x00220000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4275) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4276) * rv2p_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4277) * offset: 0x2800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4279) #define BNX2_RV2P_COMMAND 0x00002800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4280) #define BNX2_RV2P_COMMAND_ENABLED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4281) #define BNX2_RV2P_COMMAND_PROC1_INTRPT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4282) #define BNX2_RV2P_COMMAND_PROC2_INTRPT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4283) #define BNX2_RV2P_COMMAND_ABORT0 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4284) #define BNX2_RV2P_COMMAND_ABORT1 (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4285) #define BNX2_RV2P_COMMAND_ABORT2 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4286) #define BNX2_RV2P_COMMAND_ABORT3 (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4287) #define BNX2_RV2P_COMMAND_ABORT4 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4288) #define BNX2_RV2P_COMMAND_ABORT5 (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4289) #define BNX2_RV2P_COMMAND_PROC1_RESET (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4290) #define BNX2_RV2P_COMMAND_PROC2_RESET (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4291) #define BNX2_RV2P_COMMAND_CTXIF_RESET (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4293) #define BNX2_RV2P_STATUS 0x00002804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4294) #define BNX2_RV2P_STATUS_ALWAYS_0 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4295) #define BNX2_RV2P_STATUS_RV2P_GEN_STAT0_CNT (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4296) #define BNX2_RV2P_STATUS_RV2P_GEN_STAT1_CNT (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4297) #define BNX2_RV2P_STATUS_RV2P_GEN_STAT2_CNT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4298) #define BNX2_RV2P_STATUS_RV2P_GEN_STAT3_CNT (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4299) #define BNX2_RV2P_STATUS_RV2P_GEN_STAT4_CNT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4300) #define BNX2_RV2P_STATUS_RV2P_GEN_STAT5_CNT (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4302) #define BNX2_RV2P_CONFIG 0x00002808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4303) #define BNX2_RV2P_CONFIG_STALL_PROC1 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4304) #define BNX2_RV2P_CONFIG_STALL_PROC2 (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4305) #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT0 (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4306) #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT1 (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4307) #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT2 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4308) #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT3 (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4309) #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT4 (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4310) #define BNX2_RV2P_CONFIG_PROC1_STALL_ON_ABORT5 (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4311) #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT0 (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4312) #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT1 (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4313) #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT2 (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4314) #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT3 (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4315) #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT4 (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4316) #define BNX2_RV2P_CONFIG_PROC2_STALL_ON_ABORT5 (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4317) #define BNX2_RV2P_CONFIG_PAGE_SIZE (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4318) #define BNX2_RV2P_CONFIG_PAGE_SIZE_256 (0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4319) #define BNX2_RV2P_CONFIG_PAGE_SIZE_512 (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4320) #define BNX2_RV2P_CONFIG_PAGE_SIZE_1K (2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4321) #define BNX2_RV2P_CONFIG_PAGE_SIZE_2K (3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4322) #define BNX2_RV2P_CONFIG_PAGE_SIZE_4K (4L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4323) #define BNX2_RV2P_CONFIG_PAGE_SIZE_8K (5L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4324) #define BNX2_RV2P_CONFIG_PAGE_SIZE_16K (6L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4325) #define BNX2_RV2P_CONFIG_PAGE_SIZE_32K (7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4326) #define BNX2_RV2P_CONFIG_PAGE_SIZE_64K (8L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4327) #define BNX2_RV2P_CONFIG_PAGE_SIZE_128K (9L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4328) #define BNX2_RV2P_CONFIG_PAGE_SIZE_256K (10L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4329) #define BNX2_RV2P_CONFIG_PAGE_SIZE_512K (11L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4330) #define BNX2_RV2P_CONFIG_PAGE_SIZE_1M (12L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4332) #define BNX2_RV2P_GEN_BFR_ADDR_0 0x00002810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4333) #define BNX2_RV2P_GEN_BFR_ADDR_0_VALUE (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4335) #define BNX2_RV2P_GEN_BFR_ADDR_1 0x00002814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4336) #define BNX2_RV2P_GEN_BFR_ADDR_1_VALUE (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4338) #define BNX2_RV2P_GEN_BFR_ADDR_2 0x00002818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4339) #define BNX2_RV2P_GEN_BFR_ADDR_2_VALUE (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4341) #define BNX2_RV2P_GEN_BFR_ADDR_3 0x0000281c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4342) #define BNX2_RV2P_GEN_BFR_ADDR_3_VALUE (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4344) #define BNX2_RV2P_INSTR_HIGH 0x00002830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4345) #define BNX2_RV2P_INSTR_HIGH_HIGH (0x1fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4347) #define BNX2_RV2P_INSTR_LOW 0x00002834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4348) #define BNX2_RV2P_INSTR_LOW_LOW (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4350) #define BNX2_RV2P_PROC1_ADDR_CMD 0x00002838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4351) #define BNX2_RV2P_PROC1_ADDR_CMD_ADD (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4352) #define BNX2_RV2P_PROC1_ADDR_CMD_RDWR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4354) #define BNX2_RV2P_PROC2_ADDR_CMD 0x0000283c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4355) #define BNX2_RV2P_PROC2_ADDR_CMD_ADD (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4356) #define BNX2_RV2P_PROC2_ADDR_CMD_RDWR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4358) #define BNX2_RV2P_PROC1_GRC_DEBUG 0x00002840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4359) #define BNX2_RV2P_PROC2_GRC_DEBUG 0x00002844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4360) #define BNX2_RV2P_GRC_PROC_DEBUG 0x00002848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4361) #define BNX2_RV2P_DEBUG_VECT_PEEK 0x0000284c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4362) #define BNX2_RV2P_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4363) #define BNX2_RV2P_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4364) #define BNX2_RV2P_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4365) #define BNX2_RV2P_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4366) #define BNX2_RV2P_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4367) #define BNX2_RV2P_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4369) #define BNX2_RV2P_MPFE_PFE_CTL 0x00002afc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4370) #define BNX2_RV2P_MPFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4371) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4372) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4373) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4374) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4375) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4376) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4377) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4378) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4379) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4380) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4381) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4382) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4383) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4384) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4385) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4386) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4387) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4388) #define BNX2_RV2P_MPFE_PFE_CTL_PFE_COUNT (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4389) #define BNX2_RV2P_MPFE_PFE_CTL_OFFSET (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4391) #define BNX2_RV2P_RV2PPQ 0x00002b40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4392) #define BNX2_RV2P_PFTQ_CMD 0x00002b78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4393) #define BNX2_RV2P_PFTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4394) #define BNX2_RV2P_PFTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4395) #define BNX2_RV2P_PFTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4396) #define BNX2_RV2P_PFTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4397) #define BNX2_RV2P_PFTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4398) #define BNX2_RV2P_PFTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4399) #define BNX2_RV2P_PFTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4400) #define BNX2_RV2P_PFTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4401) #define BNX2_RV2P_PFTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4402) #define BNX2_RV2P_PFTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4403) #define BNX2_RV2P_PFTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4405) #define BNX2_RV2P_PFTQ_CTL 0x00002b7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4406) #define BNX2_RV2P_PFTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4407) #define BNX2_RV2P_PFTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4408) #define BNX2_RV2P_PFTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4409) #define BNX2_RV2P_PFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4410) #define BNX2_RV2P_PFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4412) #define BNX2_RV2P_RV2PTQ 0x00002b80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4413) #define BNX2_RV2P_TFTQ_CMD 0x00002bb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4414) #define BNX2_RV2P_TFTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4415) #define BNX2_RV2P_TFTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4416) #define BNX2_RV2P_TFTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4417) #define BNX2_RV2P_TFTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4418) #define BNX2_RV2P_TFTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4419) #define BNX2_RV2P_TFTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4420) #define BNX2_RV2P_TFTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4421) #define BNX2_RV2P_TFTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4422) #define BNX2_RV2P_TFTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4423) #define BNX2_RV2P_TFTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4424) #define BNX2_RV2P_TFTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4426) #define BNX2_RV2P_TFTQ_CTL 0x00002bbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4427) #define BNX2_RV2P_TFTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4428) #define BNX2_RV2P_TFTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4429) #define BNX2_RV2P_TFTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4430) #define BNX2_RV2P_TFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4431) #define BNX2_RV2P_TFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4433) #define BNX2_RV2P_RV2PMQ 0x00002bc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4434) #define BNX2_RV2P_MFTQ_CMD 0x00002bf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4435) #define BNX2_RV2P_MFTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4436) #define BNX2_RV2P_MFTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4437) #define BNX2_RV2P_MFTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4438) #define BNX2_RV2P_MFTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4439) #define BNX2_RV2P_MFTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4440) #define BNX2_RV2P_MFTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4441) #define BNX2_RV2P_MFTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4442) #define BNX2_RV2P_MFTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4443) #define BNX2_RV2P_MFTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4444) #define BNX2_RV2P_MFTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4445) #define BNX2_RV2P_MFTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4447) #define BNX2_RV2P_MFTQ_CTL 0x00002bfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4448) #define BNX2_RV2P_MFTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4449) #define BNX2_RV2P_MFTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4450) #define BNX2_RV2P_MFTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4451) #define BNX2_RV2P_MFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4452) #define BNX2_RV2P_MFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4457) * mq_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4458) * offset: 0x3c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4460) #define BNX2_MQ_COMMAND 0x00003c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4461) #define BNX2_MQ_COMMAND_ENABLED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4462) #define BNX2_MQ_COMMAND_INIT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4463) #define BNX2_MQ_COMMAND_OVERFLOW (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4464) #define BNX2_MQ_COMMAND_WR_ERROR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4465) #define BNX2_MQ_COMMAND_RD_ERROR (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4466) #define BNX2_MQ_COMMAND_IDB_CFG_ERROR (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4467) #define BNX2_MQ_COMMAND_IDB_OVERFLOW (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4468) #define BNX2_MQ_COMMAND_NO_BIN_ERROR (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4469) #define BNX2_MQ_COMMAND_NO_MAP_ERROR (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4471) #define BNX2_MQ_STATUS 0x00003c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4472) #define BNX2_MQ_STATUS_CTX_ACCESS_STAT (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4473) #define BNX2_MQ_STATUS_CTX_ACCESS64_STAT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4474) #define BNX2_MQ_STATUS_PCI_STALL_STAT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4475) #define BNX2_MQ_STATUS_IDB_OFLOW_STAT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4477) #define BNX2_MQ_CONFIG 0x00003c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4478) #define BNX2_MQ_CONFIG_TX_HIGH_PRI (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4479) #define BNX2_MQ_CONFIG_HALT_DIS (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4480) #define BNX2_MQ_CONFIG_BIN_MQ_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4481) #define BNX2_MQ_CONFIG_DIS_IDB_DROP (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4482) #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4483) #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_256 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4484) #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_512 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4485) #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_1K (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4486) #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_2K (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4487) #define BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE_4K (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4488) #define BNX2_MQ_CONFIG_MAX_DEPTH (0x7fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4489) #define BNX2_MQ_CONFIG_CUR_DEPTH (0x7fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4491) #define BNX2_MQ_ENQUEUE1 0x00003c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4492) #define BNX2_MQ_ENQUEUE1_OFFSET (0x3fL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4493) #define BNX2_MQ_ENQUEUE1_CID (0x3fffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4494) #define BNX2_MQ_ENQUEUE1_BYTE_MASK (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4495) #define BNX2_MQ_ENQUEUE1_KNL_MODE (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4497) #define BNX2_MQ_ENQUEUE2 0x00003c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4498) #define BNX2_MQ_BAD_WR_ADDR 0x00003c14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4499) #define BNX2_MQ_BAD_RD_ADDR 0x00003c18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4500) #define BNX2_MQ_KNL_BYP_WIND_START 0x00003c1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4501) #define BNX2_MQ_KNL_BYP_WIND_START_VALUE (0xfffffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4503) #define BNX2_MQ_KNL_WIND_END 0x00003c20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4504) #define BNX2_MQ_KNL_WIND_END_VALUE (0xffffffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4506) #define BNX2_MQ_KNL_WRITE_MASK1 0x00003c24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4507) #define BNX2_MQ_KNL_TX_MASK1 0x00003c28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4508) #define BNX2_MQ_KNL_CMD_MASK1 0x00003c2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4509) #define BNX2_MQ_KNL_COND_ENQUEUE_MASK1 0x00003c30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4510) #define BNX2_MQ_KNL_RX_V2P_MASK1 0x00003c34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4511) #define BNX2_MQ_KNL_WRITE_MASK2 0x00003c38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4512) #define BNX2_MQ_KNL_TX_MASK2 0x00003c3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4513) #define BNX2_MQ_KNL_CMD_MASK2 0x00003c40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4514) #define BNX2_MQ_KNL_COND_ENQUEUE_MASK2 0x00003c44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4515) #define BNX2_MQ_KNL_RX_V2P_MASK2 0x00003c48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4516) #define BNX2_MQ_KNL_BYP_WRITE_MASK1 0x00003c4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4517) #define BNX2_MQ_KNL_BYP_TX_MASK1 0x00003c50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4518) #define BNX2_MQ_KNL_BYP_CMD_MASK1 0x00003c54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4519) #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK1 0x00003c58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4520) #define BNX2_MQ_KNL_BYP_RX_V2P_MASK1 0x00003c5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4521) #define BNX2_MQ_KNL_BYP_WRITE_MASK2 0x00003c60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4522) #define BNX2_MQ_KNL_BYP_TX_MASK2 0x00003c64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4523) #define BNX2_MQ_KNL_BYP_CMD_MASK2 0x00003c68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4524) #define BNX2_MQ_KNL_BYP_COND_ENQUEUE_MASK2 0x00003c6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4525) #define BNX2_MQ_KNL_BYP_RX_V2P_MASK2 0x00003c70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4526) #define BNX2_MQ_MEM_WR_ADDR 0x00003c74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4527) #define BNX2_MQ_MEM_WR_ADDR_VALUE (0x3fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4529) #define BNX2_MQ_MEM_WR_DATA0 0x00003c78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4530) #define BNX2_MQ_MEM_WR_DATA0_VALUE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4532) #define BNX2_MQ_MEM_WR_DATA1 0x00003c7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4533) #define BNX2_MQ_MEM_WR_DATA1_VALUE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4535) #define BNX2_MQ_MEM_WR_DATA2 0x00003c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4536) #define BNX2_MQ_MEM_WR_DATA2_VALUE (0x3fffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4537) #define BNX2_MQ_MEM_WR_DATA2_VALUE_XI (0x7fffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4539) #define BNX2_MQ_MEM_RD_ADDR 0x00003c84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4540) #define BNX2_MQ_MEM_RD_ADDR_VALUE (0x3fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4542) #define BNX2_MQ_MEM_RD_DATA0 0x00003c88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4543) #define BNX2_MQ_MEM_RD_DATA0_VALUE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4545) #define BNX2_MQ_MEM_RD_DATA1 0x00003c8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4546) #define BNX2_MQ_MEM_RD_DATA1_VALUE (0xffffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4548) #define BNX2_MQ_MEM_RD_DATA2 0x00003c90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4549) #define BNX2_MQ_MEM_RD_DATA2_VALUE (0x3fffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4550) #define BNX2_MQ_MEM_RD_DATA2_VALUE_XI (0x7fffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4552) #define BNX2_MQ_MAP_L2_3 0x00003d2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4553) #define BNX2_MQ_MAP_L2_3_MQ_OFFSET (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4554) #define BNX2_MQ_MAP_L2_3_SZ (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4555) #define BNX2_MQ_MAP_L2_3_CTX_OFFSET (0x2ffL<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4556) #define BNX2_MQ_MAP_L2_3_BIN_OFFSET (0x7L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4557) #define BNX2_MQ_MAP_L2_3_ARM (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4558) #define BNX2_MQ_MAP_L2_3_ENA (0x1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4559) #define BNX2_MQ_MAP_L2_3_DEFAULT 0x82004646
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4561) #define BNX2_MQ_MAP_L2_5 0x00003d34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4562) #define BNX2_MQ_MAP_L2_5_ARM (0x3L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4565) * tsch_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4566) * offset: 0x4c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4568) #define BNX2_TSCH_TSS_CFG 0x00004c1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4569) #define BNX2_TSCH_TSS_CFG_TSS_START_CID (0x7ffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4570) #define BNX2_TSCH_TSS_CFG_NUM_OF_TSS_CON (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4574) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4575) * tbdr_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4576) * offset: 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4578) #define BNX2_TBDR_COMMAND 0x00005000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4579) #define BNX2_TBDR_COMMAND_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4580) #define BNX2_TBDR_COMMAND_SOFT_RST (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4581) #define BNX2_TBDR_COMMAND_MSTR_ABORT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4583) #define BNX2_TBDR_STATUS 0x00005004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4584) #define BNX2_TBDR_STATUS_DMA_WAIT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4585) #define BNX2_TBDR_STATUS_FTQ_WAIT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4586) #define BNX2_TBDR_STATUS_FIFO_OVERFLOW (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4587) #define BNX2_TBDR_STATUS_FIFO_UNDERFLOW (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4588) #define BNX2_TBDR_STATUS_SEARCHMISS_ERROR (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4589) #define BNX2_TBDR_STATUS_FTQ_ENTRY_CNT (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4590) #define BNX2_TBDR_STATUS_BURST_CNT (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4592) #define BNX2_TBDR_CONFIG 0x00005008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4593) #define BNX2_TBDR_CONFIG_MAX_BDS (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4594) #define BNX2_TBDR_CONFIG_SWAP_MODE (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4595) #define BNX2_TBDR_CONFIG_PRIORITY (1L<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4596) #define BNX2_TBDR_CONFIG_CACHE_NEXT_PAGE_PTRS (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4597) #define BNX2_TBDR_CONFIG_PAGE_SIZE (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4598) #define BNX2_TBDR_CONFIG_PAGE_SIZE_256 (0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4599) #define BNX2_TBDR_CONFIG_PAGE_SIZE_512 (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4600) #define BNX2_TBDR_CONFIG_PAGE_SIZE_1K (2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4601) #define BNX2_TBDR_CONFIG_PAGE_SIZE_2K (3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4602) #define BNX2_TBDR_CONFIG_PAGE_SIZE_4K (4L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4603) #define BNX2_TBDR_CONFIG_PAGE_SIZE_8K (5L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4604) #define BNX2_TBDR_CONFIG_PAGE_SIZE_16K (6L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4605) #define BNX2_TBDR_CONFIG_PAGE_SIZE_32K (7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4606) #define BNX2_TBDR_CONFIG_PAGE_SIZE_64K (8L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4607) #define BNX2_TBDR_CONFIG_PAGE_SIZE_128K (9L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4608) #define BNX2_TBDR_CONFIG_PAGE_SIZE_256K (10L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4609) #define BNX2_TBDR_CONFIG_PAGE_SIZE_512K (11L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4610) #define BNX2_TBDR_CONFIG_PAGE_SIZE_1M (12L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4612) #define BNX2_TBDR_DEBUG_VECT_PEEK 0x0000500c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4613) #define BNX2_TBDR_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4614) #define BNX2_TBDR_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4615) #define BNX2_TBDR_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4616) #define BNX2_TBDR_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4617) #define BNX2_TBDR_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4618) #define BNX2_TBDR_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4620) #define BNX2_TBDR_CKSUM_ERROR_STATUS 0x00005010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4621) #define BNX2_TBDR_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4622) #define BNX2_TBDR_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4624) #define BNX2_TBDR_TBDRQ 0x000053c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4625) #define BNX2_TBDR_FTQ_CMD 0x000053f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4626) #define BNX2_TBDR_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4627) #define BNX2_TBDR_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4628) #define BNX2_TBDR_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4629) #define BNX2_TBDR_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4630) #define BNX2_TBDR_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4631) #define BNX2_TBDR_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4632) #define BNX2_TBDR_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4633) #define BNX2_TBDR_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4634) #define BNX2_TBDR_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4635) #define BNX2_TBDR_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4636) #define BNX2_TBDR_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4638) #define BNX2_TBDR_FTQ_CTL 0x000053fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4639) #define BNX2_TBDR_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4640) #define BNX2_TBDR_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4641) #define BNX2_TBDR_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4642) #define BNX2_TBDR_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4643) #define BNX2_TBDR_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4647) * tbdc definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4648) * offset: 0x5400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4650) #define BNX2_TBDC_COMMAND 0x5400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4651) #define BNX2_TBDC_COMMAND_CMD_ENABLED (1UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4652) #define BNX2_TBDC_COMMAND_CMD_FLUSH (1UL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4653) #define BNX2_TBDC_COMMAND_CMD_SOFT_RST (1UL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4654) #define BNX2_TBDC_COMMAND_CMD_REG_ARB (1UL<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4655) #define BNX2_TBDC_COMMAND_WRCHK_RANGE_ERROR (1UL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4656) #define BNX2_TBDC_COMMAND_WRCHK_ALL_ONES_ERROR (1UL<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4657) #define BNX2_TBDC_COMMAND_WRCHK_ALL_ZEROS_ERROR (1UL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4658) #define BNX2_TBDC_COMMAND_WRCHK_ANY_ONES_ERROR (1UL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4659) #define BNX2_TBDC_COMMAND_WRCHK_ANY_ZEROS_ERROR (1UL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4661) #define BNX2_TBDC_STATUS 0x5404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4662) #define BNX2_TBDC_STATUS_FREE_CNT (0x3fUL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4664) #define BNX2_TBDC_BD_ADDR 0x5424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4666) #define BNX2_TBDC_BIDX 0x542c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4667) #define BNX2_TBDC_BDIDX_BDIDX (0xffffUL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4668) #define BNX2_TBDC_BDIDX_CMD (0xffUL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4670) #define BNX2_TBDC_CID 0x5430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4672) #define BNX2_TBDC_CAM_OPCODE 0x5434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4673) #define BNX2_TBDC_CAM_OPCODE_OPCODE (0x7UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4674) #define BNX2_TBDC_CAM_OPCODE_OPCODE_SEARCH (0UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4675) #define BNX2_TBDC_CAM_OPCODE_OPCODE_CACHE_WRITE (1UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4676) #define BNX2_TBDC_CAM_OPCODE_OPCODE_INVALIDATE (2UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4677) #define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_WRITE (4UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4678) #define BNX2_TBDC_CAM_OPCODE_OPCODE_CAM_READ (5UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4679) #define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_WRITE (6UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4680) #define BNX2_TBDC_CAM_OPCODE_OPCODE_RAM_READ (7UL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4681) #define BNX2_TBDC_CAM_OPCODE_SMASK_BDIDX (1UL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4682) #define BNX2_TBDC_CAM_OPCODE_SMASK_CID (1UL<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4683) #define BNX2_TBDC_CAM_OPCODE_SMASK_CMD (1UL<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4684) #define BNX2_TBDC_CAM_OPCODE_WMT_FAILED (1UL<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4685) #define BNX2_TBDC_CAM_OPCODE_CAM_VALIDS (0xffUL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4688) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4689) * tdma_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4690) * offset: 0x5c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4691) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4692) #define BNX2_TDMA_COMMAND 0x00005c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4693) #define BNX2_TDMA_COMMAND_ENABLED (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4694) #define BNX2_TDMA_COMMAND_MASTER_ABORT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4695) #define BNX2_TDMA_COMMAND_CS16_ERR (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4696) #define BNX2_TDMA_COMMAND_BAD_L2_LENGTH_ABORT (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4697) #define BNX2_TDMA_COMMAND_MASK_CS1 (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4698) #define BNX2_TDMA_COMMAND_MASK_CS2 (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4699) #define BNX2_TDMA_COMMAND_MASK_CS3 (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4700) #define BNX2_TDMA_COMMAND_MASK_CS4 (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4701) #define BNX2_TDMA_COMMAND_FORCE_ILOCK_CKERR (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4702) #define BNX2_TDMA_COMMAND_OFIFO_CLR (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4703) #define BNX2_TDMA_COMMAND_IFIFO_CLR (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4705) #define BNX2_TDMA_STATUS 0x00005c04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4706) #define BNX2_TDMA_STATUS_DMA_WAIT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4707) #define BNX2_TDMA_STATUS_PAYLOAD_WAIT (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4708) #define BNX2_TDMA_STATUS_PATCH_FTQ_WAIT (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4709) #define BNX2_TDMA_STATUS_LOCK_WAIT (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4710) #define BNX2_TDMA_STATUS_FTQ_ENTRY_CNT (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4711) #define BNX2_TDMA_STATUS_BURST_CNT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4712) #define BNX2_TDMA_STATUS_MAX_IFIFO_DEPTH (0x3fL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4713) #define BNX2_TDMA_STATUS_OFIFO_OVERFLOW (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4714) #define BNX2_TDMA_STATUS_IFIFO_OVERFLOW (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4716) #define BNX2_TDMA_CONFIG 0x00005c08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4717) #define BNX2_TDMA_CONFIG_ONE_DMA (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4718) #define BNX2_TDMA_CONFIG_ONE_RECORD (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4719) #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN (0x3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4720) #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_0 (0L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4721) #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_1 (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4722) #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_2 (2L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4723) #define BNX2_TDMA_CONFIG_NUM_DMA_CHAN_3 (3L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4724) #define BNX2_TDMA_CONFIG_LIMIT_SZ (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4725) #define BNX2_TDMA_CONFIG_LIMIT_SZ_64 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4726) #define BNX2_TDMA_CONFIG_LIMIT_SZ_128 (0x4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4727) #define BNX2_TDMA_CONFIG_LIMIT_SZ_256 (0x6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4728) #define BNX2_TDMA_CONFIG_LIMIT_SZ_512 (0x8L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4729) #define BNX2_TDMA_CONFIG_LINE_SZ (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4730) #define BNX2_TDMA_CONFIG_LINE_SZ_64 (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4731) #define BNX2_TDMA_CONFIG_LINE_SZ_128 (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4732) #define BNX2_TDMA_CONFIG_LINE_SZ_256 (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4733) #define BNX2_TDMA_CONFIG_LINE_SZ_512 (8L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4734) #define BNX2_TDMA_CONFIG_ALIGN_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4735) #define BNX2_TDMA_CONFIG_CHK_L2_BD (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4736) #define BNX2_TDMA_CONFIG_CMPL_ENTRY (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4737) #define BNX2_TDMA_CONFIG_OFIFO_CMP (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4738) #define BNX2_TDMA_CONFIG_OFIFO_CMP_3 (0L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4739) #define BNX2_TDMA_CONFIG_OFIFO_CMP_2 (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4740) #define BNX2_TDMA_CONFIG_FIFO_CMP (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4741) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_XI (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4742) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_0_XI (0L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4743) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_4_XI (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4744) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_8_XI (2L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4745) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_16_XI (3L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4746) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_32_XI (4L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4747) #define BNX2_TDMA_CONFIG_IFIFO_DEPTH_64_XI (5L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4748) #define BNX2_TDMA_CONFIG_FIFO_CMP_EN_XI (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4749) #define BNX2_TDMA_CONFIG_BYTES_OST_XI (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4750) #define BNX2_TDMA_CONFIG_BYTES_OST_512_XI (0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4751) #define BNX2_TDMA_CONFIG_BYTES_OST_1024_XI (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4752) #define BNX2_TDMA_CONFIG_BYTES_OST_2048_XI (2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4753) #define BNX2_TDMA_CONFIG_BYTES_OST_4096_XI (3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4754) #define BNX2_TDMA_CONFIG_BYTES_OST_8192_XI (4L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4755) #define BNX2_TDMA_CONFIG_BYTES_OST_16384_XI (5L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4756) #define BNX2_TDMA_CONFIG_HC_BYPASS_XI (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4757) #define BNX2_TDMA_CONFIG_LCL_MRRS_XI (0x7L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4758) #define BNX2_TDMA_CONFIG_LCL_MRRS_128_XI (0L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4759) #define BNX2_TDMA_CONFIG_LCL_MRRS_256_XI (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4760) #define BNX2_TDMA_CONFIG_LCL_MRRS_512_XI (2L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4761) #define BNX2_TDMA_CONFIG_LCL_MRRS_1024_XI (3L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4762) #define BNX2_TDMA_CONFIG_LCL_MRRS_2048_XI (4L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4763) #define BNX2_TDMA_CONFIG_LCL_MRRS_4096_XI (5L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4764) #define BNX2_TDMA_CONFIG_LCL_MRRS_EN_XI (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4766) #define BNX2_TDMA_PAYLOAD_PROD 0x00005c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4767) #define BNX2_TDMA_PAYLOAD_PROD_VALUE (0x1fffL<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4769) #define BNX2_TDMA_DBG_WATCHDOG 0x00005c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4770) #define BNX2_TDMA_DBG_TRIGGER 0x00005c14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4771) #define BNX2_TDMA_DMAD_FSM 0x00005c80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4772) #define BNX2_TDMA_DMAD_FSM_BD_INVLD (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4773) #define BNX2_TDMA_DMAD_FSM_PUSH (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4774) #define BNX2_TDMA_DMAD_FSM_ARB_TBDC (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4775) #define BNX2_TDMA_DMAD_FSM_ARB_CTX (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4776) #define BNX2_TDMA_DMAD_FSM_DR_INTF (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4777) #define BNX2_TDMA_DMAD_FSM_DMAD (0x7L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4778) #define BNX2_TDMA_DMAD_FSM_BD (0xfL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4780) #define BNX2_TDMA_DMAD_STATUS 0x00005c84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4781) #define BNX2_TDMA_DMAD_STATUS_RHOLD_PUSH_ENTRY (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4782) #define BNX2_TDMA_DMAD_STATUS_RHOLD_DMAD_ENTRY (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4783) #define BNX2_TDMA_DMAD_STATUS_RHOLD_BD_ENTRY (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4784) #define BNX2_TDMA_DMAD_STATUS_IFTQ_ENUM (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4786) #define BNX2_TDMA_DR_INTF_FSM 0x00005c88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4787) #define BNX2_TDMA_DR_INTF_FSM_L2_COMP (0x3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4788) #define BNX2_TDMA_DR_INTF_FSM_TPATQ (0x7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4789) #define BNX2_TDMA_DR_INTF_FSM_TPBUF (0x3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4790) #define BNX2_TDMA_DR_INTF_FSM_DR_BUF (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4791) #define BNX2_TDMA_DR_INTF_FSM_DMAD (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4793) #define BNX2_TDMA_DR_INTF_STATUS 0x00005c8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4794) #define BNX2_TDMA_DR_INTF_STATUS_HOLE_PHASE (0x7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4795) #define BNX2_TDMA_DR_INTF_STATUS_DATA_AVAIL (0x3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4796) #define BNX2_TDMA_DR_INTF_STATUS_SHIFT_ADDR (0x7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4797) #define BNX2_TDMA_DR_INTF_STATUS_NXT_PNTR (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4798) #define BNX2_TDMA_DR_INTF_STATUS_BYTE_COUNT (0x7L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4800) #define BNX2_TDMA_PUSH_FSM 0x00005c90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4801) #define BNX2_TDMA_BD_IF_DEBUG 0x00005c94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4802) #define BNX2_TDMA_DMAD_IF_DEBUG 0x00005c98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4803) #define BNX2_TDMA_CTX_IF_DEBUG 0x00005c9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4804) #define BNX2_TDMA_TPBUF_IF_DEBUG 0x00005ca0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4805) #define BNX2_TDMA_DR_IF_DEBUG 0x00005ca4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4806) #define BNX2_TDMA_TPATQ_IF_DEBUG 0x00005ca8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4807) #define BNX2_TDMA_TDMA_ILOCK_CKSUM 0x00005cac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4808) #define BNX2_TDMA_TDMA_ILOCK_CKSUM_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4809) #define BNX2_TDMA_TDMA_ILOCK_CKSUM_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4811) #define BNX2_TDMA_TDMA_PCIE_CKSUM 0x00005cb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4812) #define BNX2_TDMA_TDMA_PCIE_CKSUM_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4813) #define BNX2_TDMA_TDMA_PCIE_CKSUM_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4815) #define BNX2_TDMA_TDMAQ 0x00005fc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4816) #define BNX2_TDMA_FTQ_CMD 0x00005ff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4817) #define BNX2_TDMA_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4818) #define BNX2_TDMA_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4819) #define BNX2_TDMA_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4820) #define BNX2_TDMA_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4821) #define BNX2_TDMA_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4822) #define BNX2_TDMA_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4823) #define BNX2_TDMA_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4824) #define BNX2_TDMA_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4825) #define BNX2_TDMA_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4826) #define BNX2_TDMA_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4827) #define BNX2_TDMA_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4829) #define BNX2_TDMA_FTQ_CTL 0x00005ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4830) #define BNX2_TDMA_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4831) #define BNX2_TDMA_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4832) #define BNX2_TDMA_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4833) #define BNX2_TDMA_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4834) #define BNX2_TDMA_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4838) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4839) * hc_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4840) * offset: 0x6800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4842) #define BNX2_HC_COMMAND 0x00006800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4843) #define BNX2_HC_COMMAND_ENABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4844) #define BNX2_HC_COMMAND_SKIP_ABORT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4845) #define BNX2_HC_COMMAND_COAL_NOW (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4846) #define BNX2_HC_COMMAND_COAL_NOW_WO_INT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4847) #define BNX2_HC_COMMAND_STATS_NOW (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4848) #define BNX2_HC_COMMAND_FORCE_INT (0x3L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4849) #define BNX2_HC_COMMAND_FORCE_INT_NULL (0L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4850) #define BNX2_HC_COMMAND_FORCE_INT_HIGH (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4851) #define BNX2_HC_COMMAND_FORCE_INT_LOW (2L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4852) #define BNX2_HC_COMMAND_FORCE_INT_FREE (3L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4853) #define BNX2_HC_COMMAND_CLR_STAT_NOW (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4854) #define BNX2_HC_COMMAND_MAIN_PWR_INT (1L<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4855) #define BNX2_HC_COMMAND_COAL_ON_NEXT_EVENT (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4857) #define BNX2_HC_STATUS 0x00006804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4858) #define BNX2_HC_STATUS_MASTER_ABORT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4859) #define BNX2_HC_STATUS_PARITY_ERROR_STATE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4860) #define BNX2_HC_STATUS_PCI_CLK_CNT_STAT (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4861) #define BNX2_HC_STATUS_CORE_CLK_CNT_STAT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4862) #define BNX2_HC_STATUS_NUM_STATUS_BLOCKS_STAT (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4863) #define BNX2_HC_STATUS_NUM_INT_GEN_STAT (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4864) #define BNX2_HC_STATUS_NUM_INT_MBOX_WR_STAT (1L<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4865) #define BNX2_HC_STATUS_CORE_CLKS_TO_HW_INTACK_STAT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4866) #define BNX2_HC_STATUS_CORE_CLKS_TO_SW_INTACK_STAT (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4867) #define BNX2_HC_STATUS_CORE_CLKS_DURING_SW_INTACK_STAT (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4869) #define BNX2_HC_CONFIG 0x00006808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4870) #define BNX2_HC_CONFIG_COLLECT_STATS (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4871) #define BNX2_HC_CONFIG_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4872) #define BNX2_HC_CONFIG_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4873) #define BNX2_HC_CONFIG_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4874) #define BNX2_HC_CONFIG_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4875) #define BNX2_HC_CONFIG_STATISTIC_PRIORITY (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4876) #define BNX2_HC_CONFIG_STATUS_PRIORITY (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4877) #define BNX2_HC_CONFIG_STAT_MEM_ADDR (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4878) #define BNX2_HC_CONFIG_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4879) #define BNX2_HC_CONFIG_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4880) #define BNX2_HC_CONFIG_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4881) #define BNX2_HC_CONFIG_SET_MASK_AT_RD (1L<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4882) #define BNX2_HC_CONFIG_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4883) #define BNX2_HC_CONFIG_SB_ADDR_INC (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4884) #define BNX2_HC_CONFIG_SB_ADDR_INC_64B (0L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4885) #define BNX2_HC_CONFIG_SB_ADDR_INC_128B (1L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4886) #define BNX2_HC_CONFIG_SB_ADDR_INC_256B (2L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4887) #define BNX2_HC_CONFIG_SB_ADDR_INC_512B (3L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4888) #define BNX2_HC_CONFIG_SB_ADDR_INC_1024B (4L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4889) #define BNX2_HC_CONFIG_SB_ADDR_INC_2048B (5L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4890) #define BNX2_HC_CONFIG_SB_ADDR_INC_4096B (6L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4891) #define BNX2_HC_CONFIG_SB_ADDR_INC_8192B (7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4892) #define BNX2_HC_CONFIG_GEN_STAT_AVG_INTR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4893) #define BNX2_HC_CONFIG_UNMASK_ALL (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4894) #define BNX2_HC_CONFIG_TX_SEL (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4896) #define BNX2_HC_ATTN_BITS_ENABLE 0x0000680c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4897) #define BNX2_HC_STATUS_ADDR_L 0x00006810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4898) #define BNX2_HC_STATUS_ADDR_H 0x00006814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4899) #define BNX2_HC_STATISTICS_ADDR_L 0x00006818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4900) #define BNX2_HC_STATISTICS_ADDR_H 0x0000681c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4901) #define BNX2_HC_TX_QUICK_CONS_TRIP 0x00006820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4902) #define BNX2_HC_TX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4903) #define BNX2_HC_TX_QUICK_CONS_TRIP_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4905) #define BNX2_HC_COMP_PROD_TRIP 0x00006824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4906) #define BNX2_HC_COMP_PROD_TRIP_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4907) #define BNX2_HC_COMP_PROD_TRIP_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4909) #define BNX2_HC_RX_QUICK_CONS_TRIP 0x00006828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4910) #define BNX2_HC_RX_QUICK_CONS_TRIP_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4911) #define BNX2_HC_RX_QUICK_CONS_TRIP_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4913) #define BNX2_HC_RX_TICKS 0x0000682c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4914) #define BNX2_HC_RX_TICKS_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4915) #define BNX2_HC_RX_TICKS_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4917) #define BNX2_HC_TX_TICKS 0x00006830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4918) #define BNX2_HC_TX_TICKS_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4919) #define BNX2_HC_TX_TICKS_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4921) #define BNX2_HC_COM_TICKS 0x00006834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4922) #define BNX2_HC_COM_TICKS_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4923) #define BNX2_HC_COM_TICKS_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4925) #define BNX2_HC_CMD_TICKS 0x00006838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4926) #define BNX2_HC_CMD_TICKS_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4927) #define BNX2_HC_CMD_TICKS_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4929) #define BNX2_HC_PERIODIC_TICKS 0x0000683c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4930) #define BNX2_HC_PERIODIC_TICKS_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4931) #define BNX2_HC_PERIODIC_TICKS_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4933) #define BNX2_HC_STAT_COLLECT_TICKS 0x00006840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4934) #define BNX2_HC_STAT_COLLECT_TICKS_HC_STAT_COLL_TICKS (0xffL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4936) #define BNX2_HC_STATS_TICKS 0x00006844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4937) #define BNX2_HC_STATS_TICKS_HC_STAT_TICKS (0xffffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4939) #define BNX2_HC_STATS_INTERRUPT_STATUS 0x00006848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4940) #define BNX2_HC_STATS_INTERRUPT_STATUS_SB_STATUS (0x1ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4941) #define BNX2_HC_STATS_INTERRUPT_STATUS_INT_STATUS (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4943) #define BNX2_HC_STAT_MEM_DATA 0x0000684c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4944) #define BNX2_HC_STAT_GEN_SEL_0 0x00006850
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4945) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0 (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4946) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT0 (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4947) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT1 (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4948) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT2 (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4949) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT3 (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4950) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT4 (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4951) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT5 (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4952) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT6 (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4953) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT7 (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4954) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT8 (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4955) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT9 (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4956) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT10 (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4957) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXP_STAT11 (11L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4958) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT0 (12L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4959) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT1 (13L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4960) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT2 (14L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4961) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT3 (15L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4962) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT4 (16L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4963) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT5 (17L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4964) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT6 (18L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4965) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXP_STAT7 (19L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4966) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT0 (20L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4967) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT1 (21L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4968) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT2 (22L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4969) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT3 (23L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4970) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT4 (24L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4971) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT5 (25L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4972) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT6 (26L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4973) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT7 (27L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4974) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT8 (28L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4975) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT9 (29L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4976) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT10 (30L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4977) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COM_STAT11 (31L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4978) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT0 (32L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4979) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT1 (33L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4980) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT2 (34L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4981) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPAT_STAT3 (35L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4982) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT0 (36L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4983) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT1 (37L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4984) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT2 (38L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4985) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT3 (39L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4986) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT4 (40L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4987) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT5 (41L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4988) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT6 (42L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4989) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CP_STAT7 (43L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4990) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT0 (44L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4991) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT1 (45L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4992) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT2 (46L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4993) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT3 (47L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4994) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT4 (48L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4995) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT5 (49L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4996) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT6 (50L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4997) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MCP_STAT7 (51L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4998) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_PCI_CLK_CNT (52L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4999) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CORE_CLK_CNT (53L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5000) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS (54L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5001) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN (55L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5002) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR (56L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5003) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK (59L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5004) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK (60L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5005) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK (61L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5006) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_CMD_CNT (62L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5007) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCH_SLOT_CNT (63L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5008) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_CMD_CNT (64L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5009) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSCH_SLOT_CNT (65L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5010) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT (66L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5011) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT (67L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5012) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT (68L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5013) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT (69L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5014) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT (70L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5015) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT (71L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5016) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT (72L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5017) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT (73L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5018) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT (74L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5019) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT (75L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5020) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT (76L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5021) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT (77L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5022) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT (78L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5023) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT (79L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5024) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT (80L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5025) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT (81L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5026) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT (82L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5027) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT (83L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5028) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT (84L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5029) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_TRANSFERS_CNT (85L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5030) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_READ_DELAY_PCI_CLKS_CNT (86L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5031) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_TRANSFERS_CNT (87L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5032) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_DELAY_PCI_CLKS_CNT (88L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5033) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_READ_RETRY_AFTER_DATA_CNT (89L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5034) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_TRANSFERS_CNT (90L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5035) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_WRITE_DELAY_PCI_CLKS_CNT (91L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5036) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_TRANSFERS_CNT (92L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5037) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_DELAY_PCI_CLKS_CNT (93L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5038) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_DMAE_BIG_WRITE_RETRY_AFTER_DATA_CNT (94L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5039) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_WR_CNT64 (95L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5040) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_RD_CNT64 (96L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5041) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_ACC_STALL_CLKS (97L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5042) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_LOCK_STALL_CLKS (98L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5043) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS_STAT (99L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5044) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_CTX_ACCESS64_STAT (100L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5045) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MBQ_PCI_STALL_STAT (101L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5046) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_FTQ_ENTRY_CNT (102L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5047) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDR_BURST_CNT (103L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5048) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_FTQ_ENTRY_CNT (104L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5049) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMA_BURST_CNT (105L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5050) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_FTQ_ENTRY_CNT (106L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5051) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMA_BURST_CNT (107L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5052) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUP_MATCH_CNT (108L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5053) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_POLL_PASS_CNT (109L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5054) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR1_CNT (110L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5055) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR2_CNT (111L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5056) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR3_CNT (112L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5057) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR4_CNT (113L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5058) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_TMR_TMR5_CNT (114L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5059) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT0 (115L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5060) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT1 (116L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5061) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT2 (117L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5062) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT3 (118L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5063) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT4 (119L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5064) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2P_STAT5 (120L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5065) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC1_MISS (121L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5066) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_PROC2_MISS (122L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5067) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RBDC_BURST_CNT (127L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5068) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1 (0x7fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5069) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2 (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5070) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3 (0x7fL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5071) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5072) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UMP_RX_FRAME_DROP_XI (52L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5073) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S0_XI (57L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5074) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S1_XI (58L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5075) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S2_XI (85L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5076) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S3_XI (86L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5077) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S4_XI (87L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5078) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S5_XI (88L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5079) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S6_XI (89L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5080) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S7_XI (90L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5081) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S8_XI (91L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5082) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S9_XI (92L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5083) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_UNUSED_S10_XI (93L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5084) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_MQ_IDB_OFLOW_XI (94L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5085) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_RD_CNT_XI (123L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5086) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_BLK_WR_CNT_XI (124L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5087) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_HITS_XI (125L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5088) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_CTX_MISSES_XI (126L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5089) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC1_XI (128L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5090) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC1_XI (129L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5091) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC1_XI (130L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5092) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC1_XI (131L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5093) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC1_XI (132L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5094) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC1_XI (133L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5095) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC2_XI (134L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5096) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC2_XI (135L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5097) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC2_XI (136L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5098) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC2_XI (137L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5099) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC2_XI (138L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5100) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC2_XI (139L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5101) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC3_XI (140L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5102) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC3_XI (141L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5103) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC3_XI (142L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5104) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC3_XI (143L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5105) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC3_XI (144L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5106) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC3_XI (145L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5107) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC4_XI (146L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5108) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC4_XI (147L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5109) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC4_XI (148L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5110) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC4_XI (149L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5111) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC4_XI (150L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5112) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC4_XI (151L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5113) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC5_XI (152L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5114) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC5_XI (153L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5115) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC5_XI (154L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5116) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC5_XI (155L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5117) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC5_XI (156L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5118) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC5_XI (157L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5119) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC6_XI (158L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5120) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC6_XI (159L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5121) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC6_XI (160L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5122) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC6_XI (161L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5123) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC6_XI (162L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5124) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC6_XI (163L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5125) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC7_XI (164L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5126) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC7_XI (165L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5127) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC7_XI (166L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5128) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC7_XI (167L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5129) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC7_XI (168L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5130) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC7_XI (169L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5131) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_STATUS_BLOCKS_VEC8_XI (170L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5132) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_GEN_VEC8_XI (171L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5133) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_NUM_INT_MBOX_WR_VEC8_XI (172L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5134) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_HW_INTACK_VEC8_XI (173L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5135) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_TO_SW_INTACK_VEC8_XI (174L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5136) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_HC_CORE_CLKS_DURING_SW_INTACK_VEC8_XI (175L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5137) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_CMD_CNT_XI (176L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5138) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCS_SLOT_CNT_XI (177L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5139) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI (178L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5140) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_1_XI (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5141) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_2_XI (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5142) #define BNX2_HC_STAT_GEN_SEL_0_GEN_SEL_3_XI (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5144) #define BNX2_HC_STAT_GEN_SEL_1 0x00006854
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5145) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4 (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5146) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5 (0x7fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5147) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6 (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5148) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7 (0x7fL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5149) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_4_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5150) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_5_XI (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5151) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_6_XI (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5152) #define BNX2_HC_STAT_GEN_SEL_1_GEN_SEL_7_XI (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5154) #define BNX2_HC_STAT_GEN_SEL_2 0x00006858
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5155) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8 (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5156) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9 (0x7fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5157) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10 (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5158) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11 (0x7fL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5159) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_8_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5160) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_9_XI (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5161) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_10_XI (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5162) #define BNX2_HC_STAT_GEN_SEL_2_GEN_SEL_11_XI (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5164) #define BNX2_HC_STAT_GEN_SEL_3 0x0000685c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5165) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12 (0x7fL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5166) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13 (0x7fL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5167) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14 (0x7fL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5168) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15 (0x7fL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5169) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_12_XI (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5170) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_13_XI (0xffL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5171) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_14_XI (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5172) #define BNX2_HC_STAT_GEN_SEL_3_GEN_SEL_15_XI (0xffL<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5174) #define BNX2_HC_STAT_GEN_STAT0 0x00006888
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5175) #define BNX2_HC_STAT_GEN_STAT1 0x0000688c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5176) #define BNX2_HC_STAT_GEN_STAT2 0x00006890
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5177) #define BNX2_HC_STAT_GEN_STAT3 0x00006894
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5178) #define BNX2_HC_STAT_GEN_STAT4 0x00006898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5179) #define BNX2_HC_STAT_GEN_STAT5 0x0000689c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5180) #define BNX2_HC_STAT_GEN_STAT6 0x000068a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5181) #define BNX2_HC_STAT_GEN_STAT7 0x000068a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5182) #define BNX2_HC_STAT_GEN_STAT8 0x000068a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5183) #define BNX2_HC_STAT_GEN_STAT9 0x000068ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5184) #define BNX2_HC_STAT_GEN_STAT10 0x000068b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5185) #define BNX2_HC_STAT_GEN_STAT11 0x000068b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5186) #define BNX2_HC_STAT_GEN_STAT12 0x000068b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5187) #define BNX2_HC_STAT_GEN_STAT13 0x000068bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5188) #define BNX2_HC_STAT_GEN_STAT14 0x000068c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5189) #define BNX2_HC_STAT_GEN_STAT15 0x000068c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5190) #define BNX2_HC_STAT_GEN_STAT_AC0 0x000068c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5191) #define BNX2_HC_STAT_GEN_STAT_AC1 0x000068cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5192) #define BNX2_HC_STAT_GEN_STAT_AC2 0x000068d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5193) #define BNX2_HC_STAT_GEN_STAT_AC3 0x000068d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5194) #define BNX2_HC_STAT_GEN_STAT_AC4 0x000068d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5195) #define BNX2_HC_STAT_GEN_STAT_AC5 0x000068dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5196) #define BNX2_HC_STAT_GEN_STAT_AC6 0x000068e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5197) #define BNX2_HC_STAT_GEN_STAT_AC7 0x000068e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5198) #define BNX2_HC_STAT_GEN_STAT_AC8 0x000068e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5199) #define BNX2_HC_STAT_GEN_STAT_AC9 0x000068ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5200) #define BNX2_HC_STAT_GEN_STAT_AC10 0x000068f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5201) #define BNX2_HC_STAT_GEN_STAT_AC11 0x000068f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5202) #define BNX2_HC_STAT_GEN_STAT_AC12 0x000068f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5203) #define BNX2_HC_STAT_GEN_STAT_AC13 0x000068fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5204) #define BNX2_HC_STAT_GEN_STAT_AC14 0x00006900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5205) #define BNX2_HC_STAT_GEN_STAT_AC15 0x00006904
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5206) #define BNX2_HC_STAT_GEN_STAT_AC 0x000068c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5207) #define BNX2_HC_VIS 0x00006908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5208) #define BNX2_HC_VIS_STAT_BUILD_STATE (0xfL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5209) #define BNX2_HC_VIS_STAT_BUILD_STATE_IDLE (0L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5210) #define BNX2_HC_VIS_STAT_BUILD_STATE_START (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5211) #define BNX2_HC_VIS_STAT_BUILD_STATE_REQUEST (2L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5212) #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE64 (3L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5213) #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE32 (4L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5214) #define BNX2_HC_VIS_STAT_BUILD_STATE_UPDATE_DONE (5L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5215) #define BNX2_HC_VIS_STAT_BUILD_STATE_DMA (6L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5216) #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_CONTROL (7L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5217) #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_LOW (8L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5218) #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_HIGH (9L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5219) #define BNX2_HC_VIS_STAT_BUILD_STATE_MSI_DATA (10L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5220) #define BNX2_HC_VIS_DMA_STAT_STATE (0xfL<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5221) #define BNX2_HC_VIS_DMA_STAT_STATE_IDLE (0L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5222) #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_PARAM (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5223) #define BNX2_HC_VIS_DMA_STAT_STATE_STATUS_DMA (2L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5224) #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP (3L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5225) #define BNX2_HC_VIS_DMA_STAT_STATE_COMP (4L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5226) #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_PARAM (5L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5227) #define BNX2_HC_VIS_DMA_STAT_STATE_STATISTIC_DMA (6L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5228) #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_1 (7L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5229) #define BNX2_HC_VIS_DMA_STAT_STATE_WRITE_COMP_2 (8L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5230) #define BNX2_HC_VIS_DMA_STAT_STATE_WAIT (9L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5231) #define BNX2_HC_VIS_DMA_STAT_STATE_ABORT (15L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5232) #define BNX2_HC_VIS_DMA_MSI_STATE (0x7L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5233) #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE (0x3L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5234) #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_IDLE (0L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5235) #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_COUNT (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5236) #define BNX2_HC_VIS_STATISTIC_DMA_EN_STATE_START (2L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5238) #define BNX2_HC_VIS_1 0x0000690c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5239) #define BNX2_HC_VIS_1_HW_INTACK_STATE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5240) #define BNX2_HC_VIS_1_HW_INTACK_STATE_IDLE (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5241) #define BNX2_HC_VIS_1_HW_INTACK_STATE_COUNT (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5242) #define BNX2_HC_VIS_1_SW_INTACK_STATE (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5243) #define BNX2_HC_VIS_1_SW_INTACK_STATE_IDLE (0L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5244) #define BNX2_HC_VIS_1_SW_INTACK_STATE_COUNT (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5245) #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5246) #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_IDLE (0L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5247) #define BNX2_HC_VIS_1_DURING_SW_INTACK_STATE_COUNT (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5248) #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5249) #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_IDLE (0L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5250) #define BNX2_HC_VIS_1_MAILBOX_COUNT_STATE_COUNT (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5251) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE (0xfL<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5252) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_IDLE (0L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5253) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_DMA (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5254) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_UPDATE (2L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5255) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_ASSIGN (3L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5256) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_WAIT (4L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5257) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_UPDATE (5L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5258) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_ASSIGN (6L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5259) #define BNX2_HC_VIS_1_RAM_RD_ARB_STATE_REG_WAIT (7L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5260) #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE (0x3L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5261) #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_NORMAL (0L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5262) #define BNX2_HC_VIS_1_RAM_WR_ARB_STATE_CLEAR (1L<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5263) #define BNX2_HC_VIS_1_INT_GEN_STATE (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5264) #define BNX2_HC_VIS_1_INT_GEN_STATE_DLE (0L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5265) #define BNX2_HC_VIS_1_INT_GEN_STATE_NTERRUPT (1L<<23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5266) #define BNX2_HC_VIS_1_STAT_CHAN_ID (0x7L<<24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5267) #define BNX2_HC_VIS_1_INT_B (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5269) #define BNX2_HC_DEBUG_VECT_PEEK 0x00006910
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5270) #define BNX2_HC_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5271) #define BNX2_HC_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5272) #define BNX2_HC_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5273) #define BNX2_HC_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5274) #define BNX2_HC_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5275) #define BNX2_HC_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5277) #define BNX2_HC_COALESCE_NOW 0x00006914
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5278) #define BNX2_HC_COALESCE_NOW_COAL_NOW (0x1ffL<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5279) #define BNX2_HC_COALESCE_NOW_COAL_NOW_WO_INT (0x1ffL<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5280) #define BNX2_HC_COALESCE_NOW_COAL_ON_NXT_EVENT (0x1ffL<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5282) #define BNX2_HC_MSIX_BIT_VECTOR 0x00006918
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5283) #define BNX2_HC_MSIX_BIT_VECTOR_VAL (0x1ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5285) #define BNX2_HC_SB_CONFIG_1 0x00006a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5286) #define BNX2_HC_SB_CONFIG_1_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5287) #define BNX2_HC_SB_CONFIG_1_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5288) #define BNX2_HC_SB_CONFIG_1_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5289) #define BNX2_HC_SB_CONFIG_1_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5290) #define BNX2_HC_SB_CONFIG_1_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5291) #define BNX2_HC_SB_CONFIG_1_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5292) #define BNX2_HC_SB_CONFIG_1_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5293) #define BNX2_HC_SB_CONFIG_1_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5295) #define BNX2_HC_TX_QUICK_CONS_TRIP_1 0x00006a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5296) #define BNX2_HC_TX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5297) #define BNX2_HC_TX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5299) #define BNX2_HC_COMP_PROD_TRIP_1 0x00006a08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5300) #define BNX2_HC_COMP_PROD_TRIP_1_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5301) #define BNX2_HC_COMP_PROD_TRIP_1_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5303) #define BNX2_HC_RX_QUICK_CONS_TRIP_1 0x00006a0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5304) #define BNX2_HC_RX_QUICK_CONS_TRIP_1_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5305) #define BNX2_HC_RX_QUICK_CONS_TRIP_1_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5307) #define BNX2_HC_RX_TICKS_1 0x00006a10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5308) #define BNX2_HC_RX_TICKS_1_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5309) #define BNX2_HC_RX_TICKS_1_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5311) #define BNX2_HC_TX_TICKS_1 0x00006a14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5312) #define BNX2_HC_TX_TICKS_1_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5313) #define BNX2_HC_TX_TICKS_1_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5315) #define BNX2_HC_COM_TICKS_1 0x00006a18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5316) #define BNX2_HC_COM_TICKS_1_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5317) #define BNX2_HC_COM_TICKS_1_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5319) #define BNX2_HC_CMD_TICKS_1 0x00006a1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5320) #define BNX2_HC_CMD_TICKS_1_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5321) #define BNX2_HC_CMD_TICKS_1_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5323) #define BNX2_HC_PERIODIC_TICKS_1 0x00006a20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5324) #define BNX2_HC_PERIODIC_TICKS_1_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5325) #define BNX2_HC_PERIODIC_TICKS_1_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5327) #define BNX2_HC_SB_CONFIG_2 0x00006a24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5328) #define BNX2_HC_SB_CONFIG_2_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5329) #define BNX2_HC_SB_CONFIG_2_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5330) #define BNX2_HC_SB_CONFIG_2_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5331) #define BNX2_HC_SB_CONFIG_2_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5332) #define BNX2_HC_SB_CONFIG_2_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5333) #define BNX2_HC_SB_CONFIG_2_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5334) #define BNX2_HC_SB_CONFIG_2_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5335) #define BNX2_HC_SB_CONFIG_2_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5337) #define BNX2_HC_TX_QUICK_CONS_TRIP_2 0x00006a28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5338) #define BNX2_HC_TX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5339) #define BNX2_HC_TX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5341) #define BNX2_HC_COMP_PROD_TRIP_2 0x00006a2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5342) #define BNX2_HC_COMP_PROD_TRIP_2_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5343) #define BNX2_HC_COMP_PROD_TRIP_2_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5345) #define BNX2_HC_RX_QUICK_CONS_TRIP_2 0x00006a30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5346) #define BNX2_HC_RX_QUICK_CONS_TRIP_2_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5347) #define BNX2_HC_RX_QUICK_CONS_TRIP_2_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5349) #define BNX2_HC_RX_TICKS_2 0x00006a34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5350) #define BNX2_HC_RX_TICKS_2_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5351) #define BNX2_HC_RX_TICKS_2_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5353) #define BNX2_HC_TX_TICKS_2 0x00006a38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5354) #define BNX2_HC_TX_TICKS_2_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5355) #define BNX2_HC_TX_TICKS_2_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5357) #define BNX2_HC_COM_TICKS_2 0x00006a3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5358) #define BNX2_HC_COM_TICKS_2_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5359) #define BNX2_HC_COM_TICKS_2_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5361) #define BNX2_HC_CMD_TICKS_2 0x00006a40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5362) #define BNX2_HC_CMD_TICKS_2_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5363) #define BNX2_HC_CMD_TICKS_2_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5365) #define BNX2_HC_PERIODIC_TICKS_2 0x00006a44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5366) #define BNX2_HC_PERIODIC_TICKS_2_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5367) #define BNX2_HC_PERIODIC_TICKS_2_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5369) #define BNX2_HC_SB_CONFIG_3 0x00006a48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5370) #define BNX2_HC_SB_CONFIG_3_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5371) #define BNX2_HC_SB_CONFIG_3_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5372) #define BNX2_HC_SB_CONFIG_3_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5373) #define BNX2_HC_SB_CONFIG_3_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5374) #define BNX2_HC_SB_CONFIG_3_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5375) #define BNX2_HC_SB_CONFIG_3_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5376) #define BNX2_HC_SB_CONFIG_3_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5377) #define BNX2_HC_SB_CONFIG_3_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5379) #define BNX2_HC_TX_QUICK_CONS_TRIP_3 0x00006a4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5380) #define BNX2_HC_TX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5381) #define BNX2_HC_TX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5383) #define BNX2_HC_COMP_PROD_TRIP_3 0x00006a50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5384) #define BNX2_HC_COMP_PROD_TRIP_3_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5385) #define BNX2_HC_COMP_PROD_TRIP_3_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5387) #define BNX2_HC_RX_QUICK_CONS_TRIP_3 0x00006a54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5388) #define BNX2_HC_RX_QUICK_CONS_TRIP_3_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5389) #define BNX2_HC_RX_QUICK_CONS_TRIP_3_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5391) #define BNX2_HC_RX_TICKS_3 0x00006a58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5392) #define BNX2_HC_RX_TICKS_3_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5393) #define BNX2_HC_RX_TICKS_3_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5395) #define BNX2_HC_TX_TICKS_3 0x00006a5c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5396) #define BNX2_HC_TX_TICKS_3_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5397) #define BNX2_HC_TX_TICKS_3_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5399) #define BNX2_HC_COM_TICKS_3 0x00006a60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5400) #define BNX2_HC_COM_TICKS_3_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5401) #define BNX2_HC_COM_TICKS_3_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5403) #define BNX2_HC_CMD_TICKS_3 0x00006a64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5404) #define BNX2_HC_CMD_TICKS_3_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5405) #define BNX2_HC_CMD_TICKS_3_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5407) #define BNX2_HC_PERIODIC_TICKS_3 0x00006a68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5408) #define BNX2_HC_PERIODIC_TICKS_3_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5409) #define BNX2_HC_PERIODIC_TICKS_3_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5411) #define BNX2_HC_SB_CONFIG_4 0x00006a6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5412) #define BNX2_HC_SB_CONFIG_4_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5413) #define BNX2_HC_SB_CONFIG_4_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5414) #define BNX2_HC_SB_CONFIG_4_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5415) #define BNX2_HC_SB_CONFIG_4_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5416) #define BNX2_HC_SB_CONFIG_4_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5417) #define BNX2_HC_SB_CONFIG_4_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5418) #define BNX2_HC_SB_CONFIG_4_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5419) #define BNX2_HC_SB_CONFIG_4_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5421) #define BNX2_HC_TX_QUICK_CONS_TRIP_4 0x00006a70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5422) #define BNX2_HC_TX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5423) #define BNX2_HC_TX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5425) #define BNX2_HC_COMP_PROD_TRIP_4 0x00006a74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5426) #define BNX2_HC_COMP_PROD_TRIP_4_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5427) #define BNX2_HC_COMP_PROD_TRIP_4_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5429) #define BNX2_HC_RX_QUICK_CONS_TRIP_4 0x00006a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5430) #define BNX2_HC_RX_QUICK_CONS_TRIP_4_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5431) #define BNX2_HC_RX_QUICK_CONS_TRIP_4_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5433) #define BNX2_HC_RX_TICKS_4 0x00006a7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5434) #define BNX2_HC_RX_TICKS_4_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5435) #define BNX2_HC_RX_TICKS_4_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5437) #define BNX2_HC_TX_TICKS_4 0x00006a80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5438) #define BNX2_HC_TX_TICKS_4_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5439) #define BNX2_HC_TX_TICKS_4_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5441) #define BNX2_HC_COM_TICKS_4 0x00006a84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5442) #define BNX2_HC_COM_TICKS_4_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5443) #define BNX2_HC_COM_TICKS_4_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5445) #define BNX2_HC_CMD_TICKS_4 0x00006a88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5446) #define BNX2_HC_CMD_TICKS_4_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5447) #define BNX2_HC_CMD_TICKS_4_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5449) #define BNX2_HC_PERIODIC_TICKS_4 0x00006a8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5450) #define BNX2_HC_PERIODIC_TICKS_4_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5451) #define BNX2_HC_PERIODIC_TICKS_4_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5453) #define BNX2_HC_SB_CONFIG_5 0x00006a90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5454) #define BNX2_HC_SB_CONFIG_5_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5455) #define BNX2_HC_SB_CONFIG_5_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5456) #define BNX2_HC_SB_CONFIG_5_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5457) #define BNX2_HC_SB_CONFIG_5_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5458) #define BNX2_HC_SB_CONFIG_5_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5459) #define BNX2_HC_SB_CONFIG_5_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5460) #define BNX2_HC_SB_CONFIG_5_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5461) #define BNX2_HC_SB_CONFIG_5_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5463) #define BNX2_HC_TX_QUICK_CONS_TRIP_5 0x00006a94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5464) #define BNX2_HC_TX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5465) #define BNX2_HC_TX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5467) #define BNX2_HC_COMP_PROD_TRIP_5 0x00006a98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5468) #define BNX2_HC_COMP_PROD_TRIP_5_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5469) #define BNX2_HC_COMP_PROD_TRIP_5_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5471) #define BNX2_HC_RX_QUICK_CONS_TRIP_5 0x00006a9c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5472) #define BNX2_HC_RX_QUICK_CONS_TRIP_5_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5473) #define BNX2_HC_RX_QUICK_CONS_TRIP_5_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5475) #define BNX2_HC_RX_TICKS_5 0x00006aa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5476) #define BNX2_HC_RX_TICKS_5_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5477) #define BNX2_HC_RX_TICKS_5_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5479) #define BNX2_HC_TX_TICKS_5 0x00006aa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5480) #define BNX2_HC_TX_TICKS_5_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5481) #define BNX2_HC_TX_TICKS_5_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5483) #define BNX2_HC_COM_TICKS_5 0x00006aa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5484) #define BNX2_HC_COM_TICKS_5_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5485) #define BNX2_HC_COM_TICKS_5_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5487) #define BNX2_HC_CMD_TICKS_5 0x00006aac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5488) #define BNX2_HC_CMD_TICKS_5_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5489) #define BNX2_HC_CMD_TICKS_5_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5491) #define BNX2_HC_PERIODIC_TICKS_5 0x00006ab0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5492) #define BNX2_HC_PERIODIC_TICKS_5_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5493) #define BNX2_HC_PERIODIC_TICKS_5_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5495) #define BNX2_HC_SB_CONFIG_6 0x00006ab4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5496) #define BNX2_HC_SB_CONFIG_6_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5497) #define BNX2_HC_SB_CONFIG_6_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5498) #define BNX2_HC_SB_CONFIG_6_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5499) #define BNX2_HC_SB_CONFIG_6_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5500) #define BNX2_HC_SB_CONFIG_6_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5501) #define BNX2_HC_SB_CONFIG_6_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5502) #define BNX2_HC_SB_CONFIG_6_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5503) #define BNX2_HC_SB_CONFIG_6_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5505) #define BNX2_HC_TX_QUICK_CONS_TRIP_6 0x00006ab8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5506) #define BNX2_HC_TX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5507) #define BNX2_HC_TX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5509) #define BNX2_HC_COMP_PROD_TRIP_6 0x00006abc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5510) #define BNX2_HC_COMP_PROD_TRIP_6_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5511) #define BNX2_HC_COMP_PROD_TRIP_6_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5513) #define BNX2_HC_RX_QUICK_CONS_TRIP_6 0x00006ac0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5514) #define BNX2_HC_RX_QUICK_CONS_TRIP_6_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5515) #define BNX2_HC_RX_QUICK_CONS_TRIP_6_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5517) #define BNX2_HC_RX_TICKS_6 0x00006ac4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5518) #define BNX2_HC_RX_TICKS_6_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5519) #define BNX2_HC_RX_TICKS_6_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5521) #define BNX2_HC_TX_TICKS_6 0x00006ac8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5522) #define BNX2_HC_TX_TICKS_6_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5523) #define BNX2_HC_TX_TICKS_6_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5525) #define BNX2_HC_COM_TICKS_6 0x00006acc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5526) #define BNX2_HC_COM_TICKS_6_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5527) #define BNX2_HC_COM_TICKS_6_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5529) #define BNX2_HC_CMD_TICKS_6 0x00006ad0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5530) #define BNX2_HC_CMD_TICKS_6_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5531) #define BNX2_HC_CMD_TICKS_6_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5533) #define BNX2_HC_PERIODIC_TICKS_6 0x00006ad4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5534) #define BNX2_HC_PERIODIC_TICKS_6_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5535) #define BNX2_HC_PERIODIC_TICKS_6_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5537) #define BNX2_HC_SB_CONFIG_7 0x00006ad8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5538) #define BNX2_HC_SB_CONFIG_7_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5539) #define BNX2_HC_SB_CONFIG_7_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5540) #define BNX2_HC_SB_CONFIG_7_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5541) #define BNX2_HC_SB_CONFIG_7_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5542) #define BNX2_HC_SB_CONFIG_7_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5543) #define BNX2_HC_SB_CONFIG_7_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5544) #define BNX2_HC_SB_CONFIG_7_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5545) #define BNX2_HC_SB_CONFIG_7_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5547) #define BNX2_HC_TX_QUICK_CONS_TRIP_7 0x00006adc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5548) #define BNX2_HC_TX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5549) #define BNX2_HC_TX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5551) #define BNX2_HC_COMP_PROD_TRIP_7 0x00006ae0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5552) #define BNX2_HC_COMP_PROD_TRIP_7_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5553) #define BNX2_HC_COMP_PROD_TRIP_7_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5555) #define BNX2_HC_RX_QUICK_CONS_TRIP_7 0x00006ae4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5556) #define BNX2_HC_RX_QUICK_CONS_TRIP_7_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5557) #define BNX2_HC_RX_QUICK_CONS_TRIP_7_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5559) #define BNX2_HC_RX_TICKS_7 0x00006ae8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5560) #define BNX2_HC_RX_TICKS_7_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5561) #define BNX2_HC_RX_TICKS_7_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5563) #define BNX2_HC_TX_TICKS_7 0x00006aec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5564) #define BNX2_HC_TX_TICKS_7_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5565) #define BNX2_HC_TX_TICKS_7_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5567) #define BNX2_HC_COM_TICKS_7 0x00006af0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5568) #define BNX2_HC_COM_TICKS_7_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5569) #define BNX2_HC_COM_TICKS_7_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5571) #define BNX2_HC_CMD_TICKS_7 0x00006af4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5572) #define BNX2_HC_CMD_TICKS_7_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5573) #define BNX2_HC_CMD_TICKS_7_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5575) #define BNX2_HC_PERIODIC_TICKS_7 0x00006af8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5576) #define BNX2_HC_PERIODIC_TICKS_7_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5577) #define BNX2_HC_PERIODIC_TICKS_7_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5579) #define BNX2_HC_SB_CONFIG_8 0x00006afc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5580) #define BNX2_HC_SB_CONFIG_8_RX_TMR_MODE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5581) #define BNX2_HC_SB_CONFIG_8_TX_TMR_MODE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5582) #define BNX2_HC_SB_CONFIG_8_COM_TMR_MODE (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5583) #define BNX2_HC_SB_CONFIG_8_CMD_TMR_MODE (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5584) #define BNX2_HC_SB_CONFIG_8_PER_MODE (1L<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5585) #define BNX2_HC_SB_CONFIG_8_ONE_SHOT (1L<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5586) #define BNX2_HC_SB_CONFIG_8_USE_INT_PARAM (1L<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5587) #define BNX2_HC_SB_CONFIG_8_PER_COLLECT_LIMIT (0xfL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5589) #define BNX2_HC_TX_QUICK_CONS_TRIP_8 0x00006b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5590) #define BNX2_HC_TX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5591) #define BNX2_HC_TX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5593) #define BNX2_HC_COMP_PROD_TRIP_8 0x00006b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5594) #define BNX2_HC_COMP_PROD_TRIP_8_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5595) #define BNX2_HC_COMP_PROD_TRIP_8_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5597) #define BNX2_HC_RX_QUICK_CONS_TRIP_8 0x00006b08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5598) #define BNX2_HC_RX_QUICK_CONS_TRIP_8_VALUE (0xffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5599) #define BNX2_HC_RX_QUICK_CONS_TRIP_8_INT (0xffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5601) #define BNX2_HC_RX_TICKS_8 0x00006b0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5602) #define BNX2_HC_RX_TICKS_8_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5603) #define BNX2_HC_RX_TICKS_8_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5605) #define BNX2_HC_TX_TICKS_8 0x00006b10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5606) #define BNX2_HC_TX_TICKS_8_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5607) #define BNX2_HC_TX_TICKS_8_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5609) #define BNX2_HC_COM_TICKS_8 0x00006b14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5610) #define BNX2_HC_COM_TICKS_8_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5611) #define BNX2_HC_COM_TICKS_8_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5613) #define BNX2_HC_CMD_TICKS_8 0x00006b18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5614) #define BNX2_HC_CMD_TICKS_8_VALUE (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5615) #define BNX2_HC_CMD_TICKS_8_INT (0x3ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5617) #define BNX2_HC_PERIODIC_TICKS_8 0x00006b1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5618) #define BNX2_HC_PERIODIC_TICKS_8_HC_PERIODIC_TICKS (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5619) #define BNX2_HC_PERIODIC_TICKS_8_HC_INT_PERIODIC_TICKS (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5621) #define BNX2_HC_SB_CONFIG_SIZE (BNX2_HC_SB_CONFIG_2 - BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5622) #define BNX2_HC_COMP_PROD_TRIP_OFF (BNX2_HC_COMP_PROD_TRIP_1 - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5623) BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5624) #define BNX2_HC_COM_TICKS_OFF (BNX2_HC_COM_TICKS_1 - BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5625) #define BNX2_HC_CMD_TICKS_OFF (BNX2_HC_CMD_TICKS_1 - BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5626) #define BNX2_HC_TX_QUICK_CONS_TRIP_OFF (BNX2_HC_TX_QUICK_CONS_TRIP_1 - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5627) BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5628) #define BNX2_HC_TX_TICKS_OFF (BNX2_HC_TX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5629) #define BNX2_HC_RX_QUICK_CONS_TRIP_OFF (BNX2_HC_RX_QUICK_CONS_TRIP_1 - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5630) BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5631) #define BNX2_HC_RX_TICKS_OFF (BNX2_HC_RX_TICKS_1 - BNX2_HC_SB_CONFIG_1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5634) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5635) * txp_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5636) * offset: 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5638) #define BNX2_TXP_CPU_MODE 0x00045000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5639) #define BNX2_TXP_CPU_MODE_LOCAL_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5640) #define BNX2_TXP_CPU_MODE_STEP_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5641) #define BNX2_TXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5642) #define BNX2_TXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5643) #define BNX2_TXP_CPU_MODE_MSG_BIT1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5644) #define BNX2_TXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5645) #define BNX2_TXP_CPU_MODE_SOFT_HALT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5646) #define BNX2_TXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5647) #define BNX2_TXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5648) #define BNX2_TXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5649) #define BNX2_TXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5651) #define BNX2_TXP_CPU_STATE 0x00045004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5652) #define BNX2_TXP_CPU_STATE_BREAKPOINT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5653) #define BNX2_TXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5654) #define BNX2_TXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5655) #define BNX2_TXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5656) #define BNX2_TXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5657) #define BNX2_TXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5658) #define BNX2_TXP_CPU_STATE_ALIGN_HALTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5659) #define BNX2_TXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5660) #define BNX2_TXP_CPU_STATE_SOFT_HALTED (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5661) #define BNX2_TXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5662) #define BNX2_TXP_CPU_STATE_INTERRUPT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5663) #define BNX2_TXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5664) #define BNX2_TXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5665) #define BNX2_TXP_CPU_STATE_BLOCKED_READ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5667) #define BNX2_TXP_CPU_EVENT_MASK 0x00045008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5668) #define BNX2_TXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5669) #define BNX2_TXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5670) #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5671) #define BNX2_TXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5672) #define BNX2_TXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5673) #define BNX2_TXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5674) #define BNX2_TXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5675) #define BNX2_TXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5676) #define BNX2_TXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5677) #define BNX2_TXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5678) #define BNX2_TXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5680) #define BNX2_TXP_CPU_PROGRAM_COUNTER 0x0004501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5681) #define BNX2_TXP_CPU_INSTRUCTION 0x00045020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5682) #define BNX2_TXP_CPU_DATA_ACCESS 0x00045024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5683) #define BNX2_TXP_CPU_INTERRUPT_ENABLE 0x00045028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5684) #define BNX2_TXP_CPU_INTERRUPT_VECTOR 0x0004502c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5685) #define BNX2_TXP_CPU_INTERRUPT_SAVED_PC 0x00045030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5686) #define BNX2_TXP_CPU_HW_BREAKPOINT 0x00045034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5687) #define BNX2_TXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5688) #define BNX2_TXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5690) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK 0x00045038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5691) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5692) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5693) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5694) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5695) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5696) #define BNX2_TXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5698) #define BNX2_TXP_CPU_LAST_BRANCH_ADDR 0x00045048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5699) #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5700) #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5701) #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5702) #define BNX2_TXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5704) #define BNX2_TXP_CPU_REG_FILE 0x00045200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5705) #define BNX2_TXP_TXPQ 0x000453c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5706) #define BNX2_TXP_FTQ_CMD 0x000453f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5707) #define BNX2_TXP_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5708) #define BNX2_TXP_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5709) #define BNX2_TXP_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5710) #define BNX2_TXP_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5711) #define BNX2_TXP_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5712) #define BNX2_TXP_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5713) #define BNX2_TXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5714) #define BNX2_TXP_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5715) #define BNX2_TXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5716) #define BNX2_TXP_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5717) #define BNX2_TXP_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5719) #define BNX2_TXP_FTQ_CTL 0x000453fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5720) #define BNX2_TXP_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5721) #define BNX2_TXP_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5722) #define BNX2_TXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5723) #define BNX2_TXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5724) #define BNX2_TXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5726) #define BNX2_TXP_SCRATCH 0x00060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5729) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5730) * tpat_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5731) * offset: 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5732) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5733) #define BNX2_TPAT_CPU_MODE 0x00085000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5734) #define BNX2_TPAT_CPU_MODE_LOCAL_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5735) #define BNX2_TPAT_CPU_MODE_STEP_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5736) #define BNX2_TPAT_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5737) #define BNX2_TPAT_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5738) #define BNX2_TPAT_CPU_MODE_MSG_BIT1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5739) #define BNX2_TPAT_CPU_MODE_INTERRUPT_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5740) #define BNX2_TPAT_CPU_MODE_SOFT_HALT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5741) #define BNX2_TPAT_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5742) #define BNX2_TPAT_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5743) #define BNX2_TPAT_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5744) #define BNX2_TPAT_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5746) #define BNX2_TPAT_CPU_STATE 0x00085004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5747) #define BNX2_TPAT_CPU_STATE_BREAKPOINT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5748) #define BNX2_TPAT_CPU_STATE_BAD_INST_HALTED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5749) #define BNX2_TPAT_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5750) #define BNX2_TPAT_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5751) #define BNX2_TPAT_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5752) #define BNX2_TPAT_CPU_STATE_BAD_PC_HALTED (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5753) #define BNX2_TPAT_CPU_STATE_ALIGN_HALTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5754) #define BNX2_TPAT_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5755) #define BNX2_TPAT_CPU_STATE_SOFT_HALTED (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5756) #define BNX2_TPAT_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5757) #define BNX2_TPAT_CPU_STATE_INTERRUPT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5758) #define BNX2_TPAT_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5759) #define BNX2_TPAT_CPU_STATE_INST_FETCH_STALL (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5760) #define BNX2_TPAT_CPU_STATE_BLOCKED_READ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5762) #define BNX2_TPAT_CPU_EVENT_MASK 0x00085008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5763) #define BNX2_TPAT_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5764) #define BNX2_TPAT_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5765) #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5766) #define BNX2_TPAT_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5767) #define BNX2_TPAT_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5768) #define BNX2_TPAT_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5769) #define BNX2_TPAT_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5770) #define BNX2_TPAT_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5771) #define BNX2_TPAT_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5772) #define BNX2_TPAT_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5773) #define BNX2_TPAT_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5775) #define BNX2_TPAT_CPU_PROGRAM_COUNTER 0x0008501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5776) #define BNX2_TPAT_CPU_INSTRUCTION 0x00085020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5777) #define BNX2_TPAT_CPU_DATA_ACCESS 0x00085024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5778) #define BNX2_TPAT_CPU_INTERRUPT_ENABLE 0x00085028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5779) #define BNX2_TPAT_CPU_INTERRUPT_VECTOR 0x0008502c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5780) #define BNX2_TPAT_CPU_INTERRUPT_SAVED_PC 0x00085030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5781) #define BNX2_TPAT_CPU_HW_BREAKPOINT 0x00085034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5782) #define BNX2_TPAT_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5783) #define BNX2_TPAT_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5785) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK 0x00085038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5786) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5787) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5788) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5789) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5790) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5791) #define BNX2_TPAT_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5793) #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR 0x00085048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5794) #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5795) #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5796) #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5797) #define BNX2_TPAT_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5799) #define BNX2_TPAT_CPU_REG_FILE 0x00085200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5800) #define BNX2_TPAT_TPATQ 0x000853c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5801) #define BNX2_TPAT_FTQ_CMD 0x000853f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5802) #define BNX2_TPAT_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5803) #define BNX2_TPAT_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5804) #define BNX2_TPAT_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5805) #define BNX2_TPAT_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5806) #define BNX2_TPAT_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5807) #define BNX2_TPAT_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5808) #define BNX2_TPAT_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5809) #define BNX2_TPAT_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5810) #define BNX2_TPAT_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5811) #define BNX2_TPAT_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5812) #define BNX2_TPAT_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5814) #define BNX2_TPAT_FTQ_CTL 0x000853fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5815) #define BNX2_TPAT_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5816) #define BNX2_TPAT_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5817) #define BNX2_TPAT_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5818) #define BNX2_TPAT_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5819) #define BNX2_TPAT_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5821) #define BNX2_TPAT_SCRATCH 0x000a0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5824) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5825) * rxp_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5826) * offset: 0xc0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5827) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5828) #define BNX2_RXP_CPU_MODE 0x000c5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5829) #define BNX2_RXP_CPU_MODE_LOCAL_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5830) #define BNX2_RXP_CPU_MODE_STEP_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5831) #define BNX2_RXP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5832) #define BNX2_RXP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5833) #define BNX2_RXP_CPU_MODE_MSG_BIT1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5834) #define BNX2_RXP_CPU_MODE_INTERRUPT_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5835) #define BNX2_RXP_CPU_MODE_SOFT_HALT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5836) #define BNX2_RXP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5837) #define BNX2_RXP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5838) #define BNX2_RXP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5839) #define BNX2_RXP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5841) #define BNX2_RXP_CPU_STATE 0x000c5004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5842) #define BNX2_RXP_CPU_STATE_BREAKPOINT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5843) #define BNX2_RXP_CPU_STATE_BAD_INST_HALTED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5844) #define BNX2_RXP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5845) #define BNX2_RXP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5846) #define BNX2_RXP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5847) #define BNX2_RXP_CPU_STATE_BAD_PC_HALTED (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5848) #define BNX2_RXP_CPU_STATE_ALIGN_HALTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5849) #define BNX2_RXP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5850) #define BNX2_RXP_CPU_STATE_SOFT_HALTED (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5851) #define BNX2_RXP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5852) #define BNX2_RXP_CPU_STATE_INTERRUPT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5853) #define BNX2_RXP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5854) #define BNX2_RXP_CPU_STATE_INST_FETCH_STALL (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5855) #define BNX2_RXP_CPU_STATE_BLOCKED_READ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5857) #define BNX2_RXP_CPU_EVENT_MASK 0x000c5008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5858) #define BNX2_RXP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5859) #define BNX2_RXP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5860) #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5861) #define BNX2_RXP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5862) #define BNX2_RXP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5863) #define BNX2_RXP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5864) #define BNX2_RXP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5865) #define BNX2_RXP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5866) #define BNX2_RXP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5867) #define BNX2_RXP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5868) #define BNX2_RXP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5870) #define BNX2_RXP_CPU_PROGRAM_COUNTER 0x000c501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5871) #define BNX2_RXP_CPU_INSTRUCTION 0x000c5020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5872) #define BNX2_RXP_CPU_DATA_ACCESS 0x000c5024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5873) #define BNX2_RXP_CPU_INTERRUPT_ENABLE 0x000c5028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5874) #define BNX2_RXP_CPU_INTERRUPT_VECTOR 0x000c502c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5875) #define BNX2_RXP_CPU_INTERRUPT_SAVED_PC 0x000c5030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5876) #define BNX2_RXP_CPU_HW_BREAKPOINT 0x000c5034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5877) #define BNX2_RXP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5878) #define BNX2_RXP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5880) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK 0x000c5038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5881) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5882) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5883) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5884) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5885) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5886) #define BNX2_RXP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5888) #define BNX2_RXP_CPU_LAST_BRANCH_ADDR 0x000c5048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5889) #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5890) #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5891) #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5892) #define BNX2_RXP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5894) #define BNX2_RXP_CPU_REG_FILE 0x000c5200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5895) #define BNX2_RXP_PFE_PFE_CTL 0x000c537c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5896) #define BNX2_RXP_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5897) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5898) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5899) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5900) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5901) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5902) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5903) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5904) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5905) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5906) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5907) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5908) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5909) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5910) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5911) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5912) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5913) #define BNX2_RXP_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5914) #define BNX2_RXP_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5915) #define BNX2_RXP_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5917) #define BNX2_RXP_RXPCQ 0x000c5380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5918) #define BNX2_RXP_CFTQ_CMD 0x000c53b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5919) #define BNX2_RXP_CFTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5920) #define BNX2_RXP_CFTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5921) #define BNX2_RXP_CFTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5922) #define BNX2_RXP_CFTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5923) #define BNX2_RXP_CFTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5924) #define BNX2_RXP_CFTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5925) #define BNX2_RXP_CFTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5926) #define BNX2_RXP_CFTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5927) #define BNX2_RXP_CFTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5928) #define BNX2_RXP_CFTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5929) #define BNX2_RXP_CFTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5931) #define BNX2_RXP_CFTQ_CTL 0x000c53bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5932) #define BNX2_RXP_CFTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5933) #define BNX2_RXP_CFTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5934) #define BNX2_RXP_CFTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5935) #define BNX2_RXP_CFTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5936) #define BNX2_RXP_CFTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5938) #define BNX2_RXP_RXPQ 0x000c53c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5939) #define BNX2_RXP_FTQ_CMD 0x000c53f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5940) #define BNX2_RXP_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5941) #define BNX2_RXP_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5942) #define BNX2_RXP_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5943) #define BNX2_RXP_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5944) #define BNX2_RXP_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5945) #define BNX2_RXP_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5946) #define BNX2_RXP_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5947) #define BNX2_RXP_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5948) #define BNX2_RXP_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5949) #define BNX2_RXP_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5950) #define BNX2_RXP_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5952) #define BNX2_RXP_FTQ_CTL 0x000c53fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5953) #define BNX2_RXP_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5954) #define BNX2_RXP_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5955) #define BNX2_RXP_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5956) #define BNX2_RXP_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5957) #define BNX2_RXP_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5959) #define BNX2_RXP_SCRATCH 0x000e0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5960) #define BNX2_RXP_SCRATCH_RXP_FLOOD 0x000e0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5961) #define BNX2_RXP_SCRATCH_RSS_TBL_SZ 0x000e0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5962) #define BNX2_RXP_SCRATCH_RSS_TBL 0x000e003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5963) #define BNX2_RXP_SCRATCH_RSS_TBL_MAX_ENTRIES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5966) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5967) * com_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5968) * offset: 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5970) #define BNX2_COM_CKSUM_ERROR_STATUS 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5971) #define BNX2_COM_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5972) #define BNX2_COM_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5974) #define BNX2_COM_CPU_MODE 0x00105000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5975) #define BNX2_COM_CPU_MODE_LOCAL_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5976) #define BNX2_COM_CPU_MODE_STEP_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5977) #define BNX2_COM_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5978) #define BNX2_COM_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5979) #define BNX2_COM_CPU_MODE_MSG_BIT1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5980) #define BNX2_COM_CPU_MODE_INTERRUPT_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5981) #define BNX2_COM_CPU_MODE_SOFT_HALT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5982) #define BNX2_COM_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5983) #define BNX2_COM_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5984) #define BNX2_COM_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5985) #define BNX2_COM_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5987) #define BNX2_COM_CPU_STATE 0x00105004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5988) #define BNX2_COM_CPU_STATE_BREAKPOINT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5989) #define BNX2_COM_CPU_STATE_BAD_INST_HALTED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5990) #define BNX2_COM_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5991) #define BNX2_COM_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5992) #define BNX2_COM_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5993) #define BNX2_COM_CPU_STATE_BAD_PC_HALTED (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5994) #define BNX2_COM_CPU_STATE_ALIGN_HALTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5995) #define BNX2_COM_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5996) #define BNX2_COM_CPU_STATE_SOFT_HALTED (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5997) #define BNX2_COM_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5998) #define BNX2_COM_CPU_STATE_INTERRUPT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5999) #define BNX2_COM_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6000) #define BNX2_COM_CPU_STATE_INST_FETCH_STALL (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6001) #define BNX2_COM_CPU_STATE_BLOCKED_READ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6003) #define BNX2_COM_CPU_EVENT_MASK 0x00105008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6004) #define BNX2_COM_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6005) #define BNX2_COM_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6006) #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6007) #define BNX2_COM_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6008) #define BNX2_COM_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6009) #define BNX2_COM_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6010) #define BNX2_COM_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6011) #define BNX2_COM_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6012) #define BNX2_COM_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6013) #define BNX2_COM_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6014) #define BNX2_COM_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6016) #define BNX2_COM_CPU_PROGRAM_COUNTER 0x0010501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6017) #define BNX2_COM_CPU_INSTRUCTION 0x00105020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6018) #define BNX2_COM_CPU_DATA_ACCESS 0x00105024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6019) #define BNX2_COM_CPU_INTERRUPT_ENABLE 0x00105028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6020) #define BNX2_COM_CPU_INTERRUPT_VECTOR 0x0010502c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6021) #define BNX2_COM_CPU_INTERRUPT_SAVED_PC 0x00105030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6022) #define BNX2_COM_CPU_HW_BREAKPOINT 0x00105034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6023) #define BNX2_COM_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6024) #define BNX2_COM_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6026) #define BNX2_COM_CPU_DEBUG_VECT_PEEK 0x00105038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6027) #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6028) #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6029) #define BNX2_COM_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6030) #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6031) #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6032) #define BNX2_COM_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6034) #define BNX2_COM_CPU_LAST_BRANCH_ADDR 0x00105048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6035) #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6036) #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6037) #define BNX2_COM_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6038) #define BNX2_COM_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6040) #define BNX2_COM_CPU_REG_FILE 0x00105200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6041) #define BNX2_COM_COMTQ_PFE_PFE_CTL 0x001052bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6042) #define BNX2_COM_COMTQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6043) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6044) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6045) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6046) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6047) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6048) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6049) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6050) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6051) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6052) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6053) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6054) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6055) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6056) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6057) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6058) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6059) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6060) #define BNX2_COM_COMTQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6061) #define BNX2_COM_COMTQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6063) #define BNX2_COM_COMXQ 0x00105340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6064) #define BNX2_COM_COMXQ_FTQ_CMD 0x00105378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6065) #define BNX2_COM_COMXQ_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6066) #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6067) #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6068) #define BNX2_COM_COMXQ_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6069) #define BNX2_COM_COMXQ_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6070) #define BNX2_COM_COMXQ_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6071) #define BNX2_COM_COMXQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6072) #define BNX2_COM_COMXQ_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6073) #define BNX2_COM_COMXQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6074) #define BNX2_COM_COMXQ_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6075) #define BNX2_COM_COMXQ_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6077) #define BNX2_COM_COMXQ_FTQ_CTL 0x0010537c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6078) #define BNX2_COM_COMXQ_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6079) #define BNX2_COM_COMXQ_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6080) #define BNX2_COM_COMXQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6081) #define BNX2_COM_COMXQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6082) #define BNX2_COM_COMXQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6084) #define BNX2_COM_COMTQ 0x00105380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6085) #define BNX2_COM_COMTQ_FTQ_CMD 0x001053b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6086) #define BNX2_COM_COMTQ_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6087) #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6088) #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6089) #define BNX2_COM_COMTQ_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6090) #define BNX2_COM_COMTQ_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6091) #define BNX2_COM_COMTQ_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6092) #define BNX2_COM_COMTQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6093) #define BNX2_COM_COMTQ_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6094) #define BNX2_COM_COMTQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6095) #define BNX2_COM_COMTQ_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6096) #define BNX2_COM_COMTQ_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6098) #define BNX2_COM_COMTQ_FTQ_CTL 0x001053bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6099) #define BNX2_COM_COMTQ_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6100) #define BNX2_COM_COMTQ_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6101) #define BNX2_COM_COMTQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6102) #define BNX2_COM_COMTQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6103) #define BNX2_COM_COMTQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6105) #define BNX2_COM_COMQ 0x001053c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6106) #define BNX2_COM_COMQ_FTQ_CMD 0x001053f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6107) #define BNX2_COM_COMQ_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6108) #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6109) #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6110) #define BNX2_COM_COMQ_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6111) #define BNX2_COM_COMQ_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6112) #define BNX2_COM_COMQ_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6113) #define BNX2_COM_COMQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6114) #define BNX2_COM_COMQ_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6115) #define BNX2_COM_COMQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6116) #define BNX2_COM_COMQ_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6117) #define BNX2_COM_COMQ_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6119) #define BNX2_COM_COMQ_FTQ_CTL 0x001053fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6120) #define BNX2_COM_COMQ_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6121) #define BNX2_COM_COMQ_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6122) #define BNX2_COM_COMQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6123) #define BNX2_COM_COMQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6124) #define BNX2_COM_COMQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6126) #define BNX2_COM_SCRATCH 0x00120000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6128) #define BNX2_FW_RX_LOW_LATENCY 0x00120058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6129) #define BNX2_FW_RX_DROP_COUNT 0x00120084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6133) * cp_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6134) * offset: 0x180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6136) #define BNX2_CP_CKSUM_ERROR_STATUS 0x00180000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6137) #define BNX2_CP_CKSUM_ERROR_STATUS_CALCULATED (0xffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6138) #define BNX2_CP_CKSUM_ERROR_STATUS_EXPECTED (0xffffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6140) #define BNX2_CP_CPU_MODE 0x00185000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6141) #define BNX2_CP_CPU_MODE_LOCAL_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6142) #define BNX2_CP_CPU_MODE_STEP_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6143) #define BNX2_CP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6144) #define BNX2_CP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6145) #define BNX2_CP_CPU_MODE_MSG_BIT1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6146) #define BNX2_CP_CPU_MODE_INTERRUPT_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6147) #define BNX2_CP_CPU_MODE_SOFT_HALT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6148) #define BNX2_CP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6149) #define BNX2_CP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6150) #define BNX2_CP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6151) #define BNX2_CP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6153) #define BNX2_CP_CPU_STATE 0x00185004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6154) #define BNX2_CP_CPU_STATE_BREAKPOINT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6155) #define BNX2_CP_CPU_STATE_BAD_INST_HALTED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6156) #define BNX2_CP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6157) #define BNX2_CP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6158) #define BNX2_CP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6159) #define BNX2_CP_CPU_STATE_BAD_PC_HALTED (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6160) #define BNX2_CP_CPU_STATE_ALIGN_HALTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6161) #define BNX2_CP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6162) #define BNX2_CP_CPU_STATE_SOFT_HALTED (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6163) #define BNX2_CP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6164) #define BNX2_CP_CPU_STATE_INTERRUPT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6165) #define BNX2_CP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6166) #define BNX2_CP_CPU_STATE_INST_FETCH_STALL (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6167) #define BNX2_CP_CPU_STATE_BLOCKED_READ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6169) #define BNX2_CP_CPU_EVENT_MASK 0x00185008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6170) #define BNX2_CP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6171) #define BNX2_CP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6172) #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6173) #define BNX2_CP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6174) #define BNX2_CP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6175) #define BNX2_CP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6176) #define BNX2_CP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6177) #define BNX2_CP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6178) #define BNX2_CP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6179) #define BNX2_CP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6180) #define BNX2_CP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6182) #define BNX2_CP_CPU_PROGRAM_COUNTER 0x0018501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6183) #define BNX2_CP_CPU_INSTRUCTION 0x00185020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6184) #define BNX2_CP_CPU_DATA_ACCESS 0x00185024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6185) #define BNX2_CP_CPU_INTERRUPT_ENABLE 0x00185028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6186) #define BNX2_CP_CPU_INTERRUPT_VECTOR 0x0018502c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6187) #define BNX2_CP_CPU_INTERRUPT_SAVED_PC 0x00185030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6188) #define BNX2_CP_CPU_HW_BREAKPOINT 0x00185034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6189) #define BNX2_CP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6190) #define BNX2_CP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6192) #define BNX2_CP_CPU_DEBUG_VECT_PEEK 0x00185038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6193) #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6194) #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6195) #define BNX2_CP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6196) #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6197) #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6198) #define BNX2_CP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6200) #define BNX2_CP_CPU_LAST_BRANCH_ADDR 0x00185048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6201) #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6202) #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6203) #define BNX2_CP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6204) #define BNX2_CP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6206) #define BNX2_CP_CPU_REG_FILE 0x00185200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6207) #define BNX2_CP_CPQ_PFE_PFE_CTL 0x001853bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6208) #define BNX2_CP_CPQ_PFE_PFE_CTL_INC_USAGE_CNT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6209) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE (0xfL<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6210) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_0 (0L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6211) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_1 (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6212) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_2 (2L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6213) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_3 (3L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6214) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_4 (4L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6215) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_5 (5L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6216) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_6 (6L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6217) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_7 (7L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6218) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_8 (8L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6219) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_9 (9L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6220) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_10 (10L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6221) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_11 (11L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6222) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_12 (12L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6223) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_13 (13L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6224) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_14 (14L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6225) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_SIZE_15 (15L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6226) #define BNX2_CP_CPQ_PFE_PFE_CTL_PFE_COUNT (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6227) #define BNX2_CP_CPQ_PFE_PFE_CTL_OFFSET (0x1ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6229) #define BNX2_CP_CPQ 0x001853c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6230) #define BNX2_CP_CPQ_FTQ_CMD 0x001853f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6231) #define BNX2_CP_CPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6232) #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6233) #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6234) #define BNX2_CP_CPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6235) #define BNX2_CP_CPQ_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6236) #define BNX2_CP_CPQ_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6237) #define BNX2_CP_CPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6238) #define BNX2_CP_CPQ_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6239) #define BNX2_CP_CPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6240) #define BNX2_CP_CPQ_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6241) #define BNX2_CP_CPQ_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6243) #define BNX2_CP_CPQ_FTQ_CTL 0x001853fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6244) #define BNX2_CP_CPQ_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6245) #define BNX2_CP_CPQ_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6246) #define BNX2_CP_CPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6247) #define BNX2_CP_CPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6248) #define BNX2_CP_CPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6250) #define BNX2_CP_SCRATCH 0x001a0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6252) #define BNX2_FW_MAX_ISCSI_CONN 0x001a0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6256) * mcp_reg definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6257) * offset: 0x140000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6258) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6259) #define BNX2_MCP_MCP_CONTROL 0x00140080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6260) #define BNX2_MCP_MCP_CONTROL_SMBUS_SEL (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6261) #define BNX2_MCP_MCP_CONTROL_MCP_ISOLATE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6263) #define BNX2_MCP_MCP_ATTENTION_STATUS 0x00140084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6264) #define BNX2_MCP_MCP_ATTENTION_STATUS_DRV_DOORBELL (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6265) #define BNX2_MCP_MCP_ATTENTION_STATUS_WATCHDOG_TIMEOUT (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6266) #define BNX2_MCP_MCP_ATTENTION_STATUS_CPU_EVENT (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6268) #define BNX2_MCP_MCP_HEARTBEAT_CONTROL 0x00140088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6269) #define BNX2_MCP_MCP_HEARTBEAT_CONTROL_MCP_HEARTBEAT_ENABLE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6271) #define BNX2_MCP_MCP_HEARTBEAT_STATUS 0x0014008c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6272) #define BNX2_MCP_MCP_HEARTBEAT_STATUS_MCP_HEARTBEAT_PERIOD (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6273) #define BNX2_MCP_MCP_HEARTBEAT_STATUS_VALID (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6275) #define BNX2_MCP_MCP_HEARTBEAT 0x00140090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6276) #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_COUNT (0x3fffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6277) #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_INC (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6278) #define BNX2_MCP_MCP_HEARTBEAT_MCP_HEARTBEAT_RESET (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6280) #define BNX2_MCP_WATCHDOG_RESET 0x00140094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6281) #define BNX2_MCP_WATCHDOG_RESET_WATCHDOG_RESET (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6283) #define BNX2_MCP_WATCHDOG_CONTROL 0x00140098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6284) #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_TIMEOUT (0xfffffffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6285) #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ATTN (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6286) #define BNX2_MCP_WATCHDOG_CONTROL_MCP_RST_ENABLE (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6287) #define BNX2_MCP_WATCHDOG_CONTROL_WATCHDOG_ENABLE (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6289) #define BNX2_MCP_ACCESS_LOCK 0x0014009c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6290) #define BNX2_MCP_ACCESS_LOCK_LOCK (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6292) #define BNX2_MCP_TOE_ID 0x001400a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6293) #define BNX2_MCP_TOE_ID_FUNCTION_ID (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6295) #define BNX2_MCP_MAILBOX_CFG 0x001400a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6296) #define BNX2_MCP_MAILBOX_CFG_MAILBOX_OFFSET (0x3fffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6297) #define BNX2_MCP_MAILBOX_CFG_MAILBOX_SIZE (0xfffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6299) #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC 0x001400a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6300) #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_OFFSET (0x3fffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6301) #define BNX2_MCP_MAILBOX_CFG_OTHER_FUNC_MAILBOX_SIZE (0xfffL<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6303) #define BNX2_MCP_MCP_DOORBELL 0x001400ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6304) #define BNX2_MCP_MCP_DOORBELL_MCP_DOORBELL (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6306) #define BNX2_MCP_DRIVER_DOORBELL 0x001400b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6307) #define BNX2_MCP_DRIVER_DOORBELL_DRIVER_DOORBELL (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6309) #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC 0x001400b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6310) #define BNX2_MCP_DRIVER_DOORBELL_OTHER_FUNC_DRIVER_DOORBELL (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6312) #define BNX2_MCP_CPU_MODE 0x00145000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6313) #define BNX2_MCP_CPU_MODE_LOCAL_RST (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6314) #define BNX2_MCP_CPU_MODE_STEP_ENA (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6315) #define BNX2_MCP_CPU_MODE_PAGE_0_DATA_ENA (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6316) #define BNX2_MCP_CPU_MODE_PAGE_0_INST_ENA (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6317) #define BNX2_MCP_CPU_MODE_MSG_BIT1 (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6318) #define BNX2_MCP_CPU_MODE_INTERRUPT_ENA (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6319) #define BNX2_MCP_CPU_MODE_SOFT_HALT (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6320) #define BNX2_MCP_CPU_MODE_BAD_DATA_HALT_ENA (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6321) #define BNX2_MCP_CPU_MODE_BAD_INST_HALT_ENA (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6322) #define BNX2_MCP_CPU_MODE_FIO_ABORT_HALT_ENA (1L<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6323) #define BNX2_MCP_CPU_MODE_SPAD_UNDERFLOW_HALT_ENA (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6325) #define BNX2_MCP_CPU_STATE 0x00145004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6326) #define BNX2_MCP_CPU_STATE_BREAKPOINT (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6327) #define BNX2_MCP_CPU_STATE_BAD_INST_HALTED (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6328) #define BNX2_MCP_CPU_STATE_PAGE_0_DATA_HALTED (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6329) #define BNX2_MCP_CPU_STATE_PAGE_0_INST_HALTED (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6330) #define BNX2_MCP_CPU_STATE_BAD_DATA_ADDR_HALTED (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6331) #define BNX2_MCP_CPU_STATE_BAD_PC_HALTED (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6332) #define BNX2_MCP_CPU_STATE_ALIGN_HALTED (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6333) #define BNX2_MCP_CPU_STATE_FIO_ABORT_HALTED (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6334) #define BNX2_MCP_CPU_STATE_SOFT_HALTED (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6335) #define BNX2_MCP_CPU_STATE_SPAD_UNDERFLOW (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6336) #define BNX2_MCP_CPU_STATE_INTERRUPT (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6337) #define BNX2_MCP_CPU_STATE_DATA_ACCESS_STALL (1L<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6338) #define BNX2_MCP_CPU_STATE_INST_FETCH_STALL (1L<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6339) #define BNX2_MCP_CPU_STATE_BLOCKED_READ (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6341) #define BNX2_MCP_CPU_EVENT_MASK 0x00145008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6342) #define BNX2_MCP_CPU_EVENT_MASK_BREAKPOINT_MASK (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6343) #define BNX2_MCP_CPU_EVENT_MASK_BAD_INST_HALTED_MASK (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6344) #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_DATA_HALTED_MASK (1L<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6345) #define BNX2_MCP_CPU_EVENT_MASK_PAGE_0_INST_HALTED_MASK (1L<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6346) #define BNX2_MCP_CPU_EVENT_MASK_BAD_DATA_ADDR_HALTED_MASK (1L<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6347) #define BNX2_MCP_CPU_EVENT_MASK_BAD_PC_HALTED_MASK (1L<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6348) #define BNX2_MCP_CPU_EVENT_MASK_ALIGN_HALTED_MASK (1L<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6349) #define BNX2_MCP_CPU_EVENT_MASK_FIO_ABORT_MASK (1L<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6350) #define BNX2_MCP_CPU_EVENT_MASK_SOFT_HALTED_MASK (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6351) #define BNX2_MCP_CPU_EVENT_MASK_SPAD_UNDERFLOW_MASK (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6352) #define BNX2_MCP_CPU_EVENT_MASK_INTERRUPT_MASK (1L<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6354) #define BNX2_MCP_CPU_PROGRAM_COUNTER 0x0014501c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6355) #define BNX2_MCP_CPU_INSTRUCTION 0x00145020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6356) #define BNX2_MCP_CPU_DATA_ACCESS 0x00145024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6357) #define BNX2_MCP_CPU_INTERRUPT_ENABLE 0x00145028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6358) #define BNX2_MCP_CPU_INTERRUPT_VECTOR 0x0014502c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6359) #define BNX2_MCP_CPU_INTERRUPT_SAVED_PC 0x00145030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6360) #define BNX2_MCP_CPU_HW_BREAKPOINT 0x00145034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6361) #define BNX2_MCP_CPU_HW_BREAKPOINT_DISABLE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6362) #define BNX2_MCP_CPU_HW_BREAKPOINT_ADDRESS (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6364) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK 0x00145038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6365) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_VALUE (0x7ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6366) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_PEEK_EN (1L<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6367) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_1_SEL (0xfL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6368) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_VALUE (0x7ffL<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6369) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_PEEK_EN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6370) #define BNX2_MCP_CPU_DEBUG_VECT_PEEK_2_SEL (0xfL<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6372) #define BNX2_MCP_CPU_LAST_BRANCH_ADDR 0x00145048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6373) #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6374) #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_JUMP (0L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6375) #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_TYPE_BRANCH (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6376) #define BNX2_MCP_CPU_LAST_BRANCH_ADDR_LBA (0x3fffffffL<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6378) #define BNX2_MCP_CPU_REG_FILE 0x00145200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6379) #define BNX2_MCP_MCPQ 0x001453c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6380) #define BNX2_MCP_MCPQ_FTQ_CMD 0x001453f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6381) #define BNX2_MCP_MCPQ_FTQ_CMD_OFFSET (0x3ffL<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6382) #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6383) #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_0 (0L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6384) #define BNX2_MCP_MCPQ_FTQ_CMD_WR_TOP_1 (1L<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6385) #define BNX2_MCP_MCPQ_FTQ_CMD_SFT_RESET (1L<<25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6386) #define BNX2_MCP_MCPQ_FTQ_CMD_RD_DATA (1L<<26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6387) #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_INTERVEN (1L<<27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6388) #define BNX2_MCP_MCPQ_FTQ_CMD_ADD_DATA (1L<<28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6389) #define BNX2_MCP_MCPQ_FTQ_CMD_INTERVENE_CLR (1L<<29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6390) #define BNX2_MCP_MCPQ_FTQ_CMD_POP (1L<<30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6391) #define BNX2_MCP_MCPQ_FTQ_CMD_BUSY (1L<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6393) #define BNX2_MCP_MCPQ_FTQ_CTL 0x001453fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6394) #define BNX2_MCP_MCPQ_FTQ_CTL_INTERVENE (1L<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6395) #define BNX2_MCP_MCPQ_FTQ_CTL_OVERFLOW (1L<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6396) #define BNX2_MCP_MCPQ_FTQ_CTL_FORCE_INTERVENE (1L<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6397) #define BNX2_MCP_MCPQ_FTQ_CTL_MAX_DEPTH (0x3ffL<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6398) #define BNX2_MCP_MCPQ_FTQ_CTL_CUR_DEPTH (0x3ffL<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6400) #define BNX2_MCP_ROM 0x00150000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6401) #define BNX2_MCP_SCRATCH 0x00160000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6402) #define BNX2_MCP_STATE_P1 0x0016f9c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6403) #define BNX2_MCP_STATE_P0 0x0016fdc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6404) #define BNX2_MCP_STATE_P1_5708 0x001699c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6405) #define BNX2_MCP_STATE_P0_5708 0x00169dc8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6407) #define BNX2_SHM_HDR_SIGNATURE BNX2_MCP_SCRATCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6408) #define BNX2_SHM_HDR_SIGNATURE_SIG_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6409) #define BNX2_SHM_HDR_SIGNATURE_SIG 0x53530000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6410) #define BNX2_SHM_HDR_SIGNATURE_VER_MASK 0x000000ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6411) #define BNX2_SHM_HDR_SIGNATURE_VER_ONE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6413) #define BNX2_SHM_HDR_ADDR_0 BNX2_MCP_SCRATCH + 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6414) #define BNX2_SHM_HDR_ADDR_1 BNX2_MCP_SCRATCH + 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6417) #define NUM_MC_HASH_REGISTERS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6420) /* PHY_ID1: bits 31-16; PHY_ID2: bits 15-0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6421) #define PHY_BCM5706_PHY_ID 0x00206160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6423) #define PHY_ID(id) ((id) & 0xfffffff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6424) #define PHY_REV_ID(id) ((id) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6426) /* 5708 Serdes PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6428) #define BCM5708S_BMCR_FORCE_2500 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6430) #define BCM5708S_UP1 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6432) #define BCM5708S_UP1_2G5 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6434) #define BCM5708S_BLK_ADDR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6436) #define BCM5708S_BLK_ADDR_DIG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6437) #define BCM5708S_BLK_ADDR_DIG3 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6438) #define BCM5708S_BLK_ADDR_TX_MISC 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6440) /* Digital Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6441) #define BCM5708S_1000X_CTL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6443) #define BCM5708S_1000X_CTL1_FIBER_MODE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6444) #define BCM5708S_1000X_CTL1_AUTODET_EN 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6446) #define BCM5708S_1000X_CTL2 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6448) #define BCM5708S_1000X_CTL2_PLLEL_DET_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6450) #define BCM5708S_1000X_STAT1 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6452) #define BCM5708S_1000X_STAT1_SGMII 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6453) #define BCM5708S_1000X_STAT1_LINK 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6454) #define BCM5708S_1000X_STAT1_FD 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6455) #define BCM5708S_1000X_STAT1_SPEED_MASK 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6456) #define BCM5708S_1000X_STAT1_SPEED_10 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6457) #define BCM5708S_1000X_STAT1_SPEED_100 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6458) #define BCM5708S_1000X_STAT1_SPEED_1G 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6459) #define BCM5708S_1000X_STAT1_SPEED_2G5 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6460) #define BCM5708S_1000X_STAT1_TX_PAUSE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6461) #define BCM5708S_1000X_STAT1_RX_PAUSE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6463) /* Digital3 Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6464) #define BCM5708S_DIG_3_0 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6466) #define BCM5708S_DIG_3_0_USE_IEEE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6468) /* Tx/Misc Block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6469) #define BCM5708S_TX_ACTL1 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6471) #define BCM5708S_TX_ACTL1_DRIVER_VCM 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6473) #define BCM5708S_TX_ACTL3 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6475) #define MII_BNX2_EXT_STATUS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6476) #define EXT_STATUS_MDIX (1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6478) #define MII_BNX2_AUX_CTL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6479) #define AUX_CTL_MISC_CTL 0x7007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6480) #define AUX_CTL_MISC_CTL_WIRESPEED (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6481) #define AUX_CTL_MISC_CTL_AUTOMDIX (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6482) #define AUX_CTL_MISC_CTL_WR (1 << 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6484) #define MII_BNX2_DSP_RW_PORT 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6485) #define MII_BNX2_DSP_ADDRESS 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6486) #define MII_BNX2_DSP_EXPAND_REG 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6487) #define MII_EXPAND_REG1 (MII_BNX2_DSP_EXPAND_REG | 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6488) #define MII_EXPAND_REG1_RUDI_C 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6489) #define MII_EXPAND_SERDES_CTL (MII_BNX2_DSP_EXPAND_REG | 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6491) #define MII_BNX2_MISC_SHADOW 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6492) #define MISC_SHDW_AN_DBG 0x6800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6493) #define MISC_SHDW_AN_DBG_NOSYNC 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6494) #define MISC_SHDW_AN_DBG_RUDI_INVALID 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6495) #define MISC_SHDW_MODE_CTL 0x7c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6496) #define MISC_SHDW_MODE_CTL_SIG_DET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6498) #define MII_BNX2_BLK_ADDR 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6499) #define MII_BNX2_BLK_ADDR_IEEE0 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6500) #define MII_BNX2_BLK_ADDR_GP_STATUS 0x8120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6501) #define MII_BNX2_GP_TOP_AN_STATUS1 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6502) #define MII_BNX2_GP_TOP_AN_SPEED_MSK 0x3f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6503) #define MII_BNX2_GP_TOP_AN_SPEED_10 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6504) #define MII_BNX2_GP_TOP_AN_SPEED_100 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6505) #define MII_BNX2_GP_TOP_AN_SPEED_1G 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6506) #define MII_BNX2_GP_TOP_AN_SPEED_2_5G 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6507) #define MII_BNX2_GP_TOP_AN_SPEED_1GKV 0x0d00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6508) #define MII_BNX2_GP_TOP_AN_FD 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6509) #define MII_BNX2_BLK_ADDR_SERDES_DIG 0x8300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6510) #define MII_BNX2_SERDES_DIG_1000XCTL1 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6511) #define MII_BNX2_SD_1000XCTL1_FIBER 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6512) #define MII_BNX2_SD_1000XCTL1_AUTODET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6513) #define MII_BNX2_SERDES_DIG_MISC1 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6514) #define MII_BNX2_SD_MISC1_FORCE_MSK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6515) #define MII_BNX2_SD_MISC1_FORCE_2_5G 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6516) #define MII_BNX2_SD_MISC1_FORCE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6517) #define MII_BNX2_BLK_ADDR_OVER1G 0x8320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6518) #define MII_BNX2_OVER1G_UP1 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6519) #define MII_BNX2_BLK_ADDR_BAM_NXTPG 0x8350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6520) #define MII_BNX2_BAM_NXTPG_CTL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6521) #define MII_BNX2_NXTPG_CTL_BAM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6522) #define MII_BNX2_NXTPG_CTL_T2 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6523) #define MII_BNX2_BLK_ADDR_CL73_USERB0 0x8370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6524) #define MII_BNX2_CL73_BAM_CTL1 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6525) #define MII_BNX2_CL73_BAM_EN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6526) #define MII_BNX2_CL73_BAM_STA_MGR_EN 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6527) #define MII_BNX2_CL73_BAM_NP_AFT_BP_EN 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6528) #define MII_BNX2_BLK_ADDR_AER 0xffd0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6529) #define MII_BNX2_AER_AER 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6530) #define MII_BNX2_AER_AER_AN_MMD 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6531) #define MII_BNX2_BLK_ADDR_COMBO_IEEEB0 0xffe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6533) #define MIN_ETHERNET_PACKET_SIZE (ETH_ZLEN - ETH_HLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6534) #define MAX_ETHERNET_PACKET_SIZE ETH_DATA_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6535) #define MAX_ETHERNET_JUMBO_PACKET_SIZE 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6537) #define BNX2_RX_COPY_THRESH 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6539) #define BNX2_MISC_ENABLE_DEFAULT 0x17ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6541) #define BNX2_START_UNICAST_ADDRESS_INDEX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6542) #define BNX2_END_UNICAST_ADDRESS_INDEX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6543) #define BNX2_MAX_UNICAST_ADDRESSES (BNX2_END_UNICAST_ADDRESS_INDEX - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6544) BNX2_START_UNICAST_ADDRESS_INDEX + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6546) #define DMA_READ_CHANS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6547) #define DMA_WRITE_CHANS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6549) /* Use CPU native page size up to 16K for the ring sizes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6550) #if (PAGE_SHIFT > 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6551) #define BNX2_PAGE_BITS 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6552) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6553) #define BNX2_PAGE_BITS PAGE_SHIFT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6554) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6555) #define BNX2_PAGE_SIZE (1 << BNX2_PAGE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6557) #define BNX2_TX_DESC_CNT (BNX2_PAGE_SIZE / sizeof(struct bnx2_tx_bd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6558) #define BNX2_MAX_TX_DESC_CNT (BNX2_TX_DESC_CNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6560) #define BNX2_MAX_RX_RINGS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6561) #define BNX2_MAX_RX_PG_RINGS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6562) #define BNX2_RX_DESC_CNT (BNX2_PAGE_SIZE / sizeof(struct bnx2_rx_bd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6563) #define BNX2_MAX_RX_DESC_CNT (BNX2_RX_DESC_CNT - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6564) #define BNX2_MAX_TOTAL_RX_DESC_CNT (BNX2_MAX_RX_DESC_CNT * BNX2_MAX_RX_RINGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6565) #define BNX2_MAX_TOTAL_RX_PG_DESC_CNT \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6566) (BNX2_MAX_RX_DESC_CNT * BNX2_MAX_RX_PG_RINGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6568) #define BNX2_NEXT_TX_BD(x) (((x) & (BNX2_MAX_TX_DESC_CNT - 1)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6569) (BNX2_MAX_TX_DESC_CNT - 1)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6570) (x) + 2 : (x) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6572) #define BNX2_TX_RING_IDX(x) ((x) & BNX2_MAX_TX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6574) #define BNX2_NEXT_RX_BD(x) (((x) & (BNX2_MAX_RX_DESC_CNT - 1)) == \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6575) (BNX2_MAX_RX_DESC_CNT - 1)) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6576) (x) + 2 : (x) + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6578) #define BNX2_RX_RING_IDX(x) ((x) & bp->rx_max_ring_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6579) #define BNX2_RX_PG_RING_IDX(x) ((x) & bp->rx_max_pg_ring_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6581) #define BNX2_RX_RING(x) (((x) & ~BNX2_MAX_RX_DESC_CNT) >> (BNX2_PAGE_BITS - 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6582) #define BNX2_RX_IDX(x) ((x) & BNX2_MAX_RX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6584) /* Context size. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6585) #define CTX_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6586) #define CTX_SIZE (1 << CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6587) #define CTX_MASK (CTX_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6588) #define GET_CID_ADDR(_cid) ((_cid) << CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6589) #define GET_CID(_cid_addr) ((_cid_addr) >> CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6591) #define PHY_CTX_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6592) #define PHY_CTX_SIZE (1 << PHY_CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6593) #define PHY_CTX_MASK (PHY_CTX_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6594) #define GET_PCID_ADDR(_pcid) ((_pcid) << PHY_CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6595) #define GET_PCID(_pcid_addr) ((_pcid_addr) >> PHY_CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6597) #define MB_KERNEL_CTX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6598) #define MB_KERNEL_CTX_SIZE (1 << MB_KERNEL_CTX_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6599) #define MB_KERNEL_CTX_MASK (MB_KERNEL_CTX_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6600) #define MB_GET_CID_ADDR(_cid) (0x10000 + ((_cid) << MB_KERNEL_CTX_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6602) #define MAX_CID_CNT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6603) #define MAX_CID_ADDR (GET_CID_ADDR(MAX_CID_CNT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6604) #define INVALID_CID_ADDR 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6606) #define TX_CID 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6607) #define TX_TSS_CID 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6608) #define RX_CID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6609) #define RX_RSS_CID 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6610) #define RX_MAX_RSS_RINGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6611) #define RX_MAX_RINGS (RX_MAX_RSS_RINGS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6612) #define TX_MAX_TSS_RINGS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6613) #define TX_MAX_RINGS (TX_MAX_TSS_RINGS + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6615) #define MB_TX_CID_ADDR MB_GET_CID_ADDR(TX_CID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6616) #define MB_RX_CID_ADDR MB_GET_CID_ADDR(RX_CID)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6619) * This driver uses new build_skb() API :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6620) * RX ring buffer contains pointer to kmalloc() data only,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6621) * skb are built only after Hardware filled the frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6622) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6623) struct bnx2_sw_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6624) u8 *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6625) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6626) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6628) /* Its faster to compute this from data than storing it in sw_bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6629) * (less cache misses)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6630) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6631) static inline struct l2_fhdr *get_l2_fhdr(u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6633) return (struct l2_fhdr *)(PTR_ALIGN(data, BNX2_RX_ALIGN) + NET_SKB_PAD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6637) struct bnx2_sw_pg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6638) struct page *page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6639) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6640) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6642) struct bnx2_sw_tx_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6643) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6644) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6645) unsigned short is_gso;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6646) unsigned short nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6649) #define SW_RXBD_RING_SIZE (sizeof(struct bnx2_sw_bd) * BNX2_RX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6650) #define SW_RXPG_RING_SIZE (sizeof(struct bnx2_sw_pg) * BNX2_RX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6651) #define RXBD_RING_SIZE (sizeof(struct bnx2_rx_bd) * BNX2_RX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6652) #define SW_TXBD_RING_SIZE (sizeof(struct bnx2_sw_tx_bd) * BNX2_TX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6653) #define TXBD_RING_SIZE (sizeof(struct bnx2_tx_bd) * BNX2_TX_DESC_CNT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6655) /* Buffered flash (Atmel: AT45DB011B) specific information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6656) #define SEEPROM_PAGE_BITS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6657) #define SEEPROM_PHY_PAGE_SIZE (1 << SEEPROM_PAGE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6658) #define SEEPROM_BYTE_ADDR_MASK (SEEPROM_PHY_PAGE_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6659) #define SEEPROM_PAGE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6660) #define SEEPROM_TOTAL_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6662) #define BUFFERED_FLASH_PAGE_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6663) #define BUFFERED_FLASH_PHY_PAGE_SIZE (1 << BUFFERED_FLASH_PAGE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6664) #define BUFFERED_FLASH_BYTE_ADDR_MASK (BUFFERED_FLASH_PHY_PAGE_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6665) #define BUFFERED_FLASH_PAGE_SIZE 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6666) #define BUFFERED_FLASH_TOTAL_SIZE 0x21000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6668) #define SAIFUN_FLASH_PAGE_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6669) #define SAIFUN_FLASH_PHY_PAGE_SIZE (1 << SAIFUN_FLASH_PAGE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6670) #define SAIFUN_FLASH_BYTE_ADDR_MASK (SAIFUN_FLASH_PHY_PAGE_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6671) #define SAIFUN_FLASH_PAGE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6672) #define SAIFUN_FLASH_BASE_TOTAL_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6674) #define ST_MICRO_FLASH_PAGE_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6675) #define ST_MICRO_FLASH_PHY_PAGE_SIZE (1 << ST_MICRO_FLASH_PAGE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6676) #define ST_MICRO_FLASH_BYTE_ADDR_MASK (ST_MICRO_FLASH_PHY_PAGE_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6677) #define ST_MICRO_FLASH_PAGE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6678) #define ST_MICRO_FLASH_BASE_TOTAL_SIZE 65536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6680) #define BCM5709_FLASH_PAGE_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6681) #define BCM5709_FLASH_PHY_PAGE_SIZE (1 << BCM5709_FLASH_PAGE_BITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6682) #define BCM5709_FLASH_BYTE_ADDR_MASK (BCM5709_FLASH_PHY_PAGE_SIZE-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6683) #define BCM5709_FLASH_PAGE_SIZE 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6685) #define NVRAM_TIMEOUT_COUNT 30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6688) #define FLASH_STRAP_MASK (BNX2_NVM_CFG1_FLASH_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6689) BNX2_NVM_CFG1_BUFFER_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6690) BNX2_NVM_CFG1_PROTECT_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6691) BNX2_NVM_CFG1_FLASH_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6693) #define FLASH_BACKUP_STRAP_MASK (0xf << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6695) struct flash_spec {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6696) u32 strapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6697) u32 config1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6698) u32 config2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6699) u32 config3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6700) u32 write1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6701) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6702) #define BNX2_NV_BUFFERED 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6703) #define BNX2_NV_TRANSLATE 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6704) #define BNX2_NV_WREN 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6705) u32 page_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6706) u32 page_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6707) u32 addr_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6708) u32 total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6709) u8 *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6712) #define BNX2_MAX_MSIX_HW_VEC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6713) #define BNX2_MAX_MSIX_VEC 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6714) #ifdef BCM_CNIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6715) #define BNX2_MIN_MSIX_VEC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6716) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6717) #define BNX2_MIN_MSIX_VEC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6718) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6721) struct bnx2_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6722) irq_handler_t handler;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6723) unsigned int vector;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6724) u8 requested;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6725) char name[IFNAMSIZ + 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6728) struct bnx2_tx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6729) u32 tx_prod_bseq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6730) u16 tx_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6731) u32 tx_bidx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6732) u32 tx_bseq_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6734) struct bnx2_tx_bd *tx_desc_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6735) struct bnx2_sw_tx_bd *tx_buf_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6737) u16 tx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6738) u16 hw_tx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6740) dma_addr_t tx_desc_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6743) struct bnx2_rx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6744) u32 rx_prod_bseq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6745) u16 rx_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6746) u16 rx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6748) u32 rx_bidx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6749) u32 rx_bseq_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6750) u32 rx_pg_bidx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6752) u16 rx_pg_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6753) u16 rx_pg_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6755) struct bnx2_sw_bd *rx_buf_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6756) struct bnx2_rx_bd *rx_desc_ring[BNX2_MAX_RX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6757) struct bnx2_sw_pg *rx_pg_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6758) struct bnx2_rx_bd *rx_pg_desc_ring[BNX2_MAX_RX_PG_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6760) dma_addr_t rx_desc_mapping[BNX2_MAX_RX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6761) dma_addr_t rx_pg_desc_mapping[BNX2_MAX_RX_PG_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6762) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6764) struct bnx2_napi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6765) struct napi_struct napi ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6766) struct bnx2 *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6767) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6768) struct status_block *msi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6769) struct status_block_msix *msix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6770) } status_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6771) u16 *hw_tx_cons_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6772) u16 *hw_rx_cons_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6773) u32 last_status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6774) u32 int_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6776) #ifdef BCM_CNIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6777) u32 cnic_tag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6778) int cnic_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6779) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6781) struct bnx2_rx_ring_info rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6782) struct bnx2_tx_ring_info tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6783) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6785) struct bnx2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6786) /* Fields used in the tx and intr/napi performance paths are grouped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6787) /* together in the beginning of the structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6788) void __iomem *regview;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6790) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6791) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6793) atomic_t intr_sem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6795) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6796) #define BNX2_FLAG_PCIX 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6797) #define BNX2_FLAG_PCI_32BIT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6798) #define BNX2_FLAG_MSIX_CAP 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6799) #define BNX2_FLAG_NO_WOL 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6800) #define BNX2_FLAG_USING_MSI 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6801) #define BNX2_FLAG_ASF_ENABLE 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6802) #define BNX2_FLAG_MSI_CAP 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6803) #define BNX2_FLAG_ONE_SHOT_MSI 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6804) #define BNX2_FLAG_PCIE 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6805) #define BNX2_FLAG_USING_MSIX 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6806) #define BNX2_FLAG_USING_MSI_OR_MSIX (BNX2_FLAG_USING_MSI | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6807) BNX2_FLAG_USING_MSIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6808) #define BNX2_FLAG_JUMBO_BROKEN 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6809) #define BNX2_FLAG_CAN_KEEP_VLAN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6810) #define BNX2_FLAG_BROKEN_STATS 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6811) #define BNX2_FLAG_AER_ENABLED 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6813) struct bnx2_napi bnx2_napi[BNX2_MAX_MSIX_VEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6815) u32 rx_buf_use_size; /* useable size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6816) u32 rx_buf_size; /* with alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6817) u32 rx_copy_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6818) u32 rx_jumbo_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6819) u32 rx_max_ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6820) u32 rx_max_pg_ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6822) /* TX constants */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6823) int tx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6824) u32 tx_wake_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6826) #ifdef BCM_CNIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6827) struct cnic_ops __rcu *cnic_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6828) void *cnic_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6829) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6831) /* End of fields used in the performance code paths. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6833) unsigned int current_interval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6834) #define BNX2_TIMER_INTERVAL HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6835) #define BNX2_SERDES_AN_TIMEOUT (HZ / 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6836) #define BNX2_SERDES_FORCED_TIMEOUT (HZ / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6838) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6839) struct work_struct reset_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6841) /* Used to synchronize phy accesses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6842) spinlock_t phy_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6843) spinlock_t indirect_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6845) u32 phy_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6846) #define BNX2_PHY_FLAG_SERDES 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6847) #define BNX2_PHY_FLAG_CRC_FIX 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6848) #define BNX2_PHY_FLAG_PARALLEL_DETECT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6849) #define BNX2_PHY_FLAG_2_5G_CAPABLE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6850) #define BNX2_PHY_FLAG_INT_MODE_MASK 0x00000300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6851) #define BNX2_PHY_FLAG_INT_MODE_AUTO_POLLING 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6852) #define BNX2_PHY_FLAG_INT_MODE_LINK_READY 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6853) #define BNX2_PHY_FLAG_DIS_EARLY_DAC 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6854) #define BNX2_PHY_FLAG_REMOTE_PHY_CAP 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6855) #define BNX2_PHY_FLAG_FORCED_DOWN 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6856) #define BNX2_PHY_FLAG_NO_PARALLEL 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6857) #define BNX2_PHY_FLAG_MDIX 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6859) u32 mii_bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6860) u32 mii_bmsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6861) u32 mii_bmsr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6862) u32 mii_adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6863) u32 mii_lpa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6864) u32 mii_up1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6866) u32 chip_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6867) /* chip num:16-31, rev:12-15, metal:4-11, bond_id:0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6868) #define BNX2_CHIP(bp) (((bp)->chip_id) & 0xffff0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6869) #define BNX2_CHIP_5706 0x57060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6870) #define BNX2_CHIP_5708 0x57080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6871) #define BNX2_CHIP_5709 0x57090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6873) #define BNX2_CHIP_REV(bp) (((bp)->chip_id) & 0x0000f000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6874) #define BNX2_CHIP_REV_Ax 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6875) #define BNX2_CHIP_REV_Bx 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6876) #define BNX2_CHIP_REV_Cx 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6878) #define BNX2_CHIP_METAL(bp) (((bp)->chip_id) & 0x00000ff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6879) #define BNX2_CHIP_BOND(bp) (((bp)->chip_id) & 0x0000000f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6881) #define BNX2_CHIP_ID(bp) (((bp)->chip_id) & 0xfffffff0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6882) #define BNX2_CHIP_ID_5706_A0 0x57060000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6883) #define BNX2_CHIP_ID_5706_A1 0x57060010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6884) #define BNX2_CHIP_ID_5706_A2 0x57060020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6885) #define BNX2_CHIP_ID_5708_A0 0x57080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6886) #define BNX2_CHIP_ID_5708_B0 0x57081000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6887) #define BNX2_CHIP_ID_5708_B1 0x57081010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6888) #define BNX2_CHIP_ID_5709_A0 0x57090000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6889) #define BNX2_CHIP_ID_5709_A1 0x57090010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6891) /* A serdes chip will have the first bit of the bond id set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6892) #define BNX2_CHIP_BOND_SERDES_BIT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6894) u32 phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6895) u32 phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6897) u16 bus_speed_mhz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6898) u8 wol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6900) u8 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6902) u16 fw_wr_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6903) u16 fw_drv_pulse_wr_seq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6904) u32 fw_last_msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6906) int rx_max_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6907) int rx_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6909) int rx_max_pg_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6910) int rx_pg_ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6912) u16 tx_quick_cons_trip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6913) u16 tx_quick_cons_trip_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6914) u16 rx_quick_cons_trip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6915) u16 rx_quick_cons_trip_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6916) u16 comp_prod_trip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6917) u16 comp_prod_trip_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6918) u16 tx_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6919) u16 tx_ticks_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6920) u16 com_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6921) u16 com_ticks_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6922) u16 cmd_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6923) u16 cmd_ticks_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6924) u16 rx_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6925) u16 rx_ticks_int;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6927) u32 stats_ticks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6929) dma_addr_t status_blk_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6931) void *status_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6932) struct statistics_block *stats_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6933) struct statistics_block *temp_stats_blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6934) dma_addr_t stats_blk_mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6936) int ctx_pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6937) void *ctx_blk[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6938) dma_addr_t ctx_blk_mapping[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6940) u32 hc_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6941) u32 rx_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6943) u16 req_line_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6944) u8 req_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6946) u8 phy_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6947) u8 link_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6949) u16 line_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6950) u8 duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6951) u8 flow_ctrl; /* actual flow ctrl settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6952) /* may be different from */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6953) /* req_flow_ctrl if autoneg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6954) u32 advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6956) u8 req_flow_ctrl; /* flow ctrl advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6957) /* settings or forced */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6958) /* settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6959) u8 autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6960) #define AUTONEG_SPEED 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6961) #define AUTONEG_FLOW_CTRL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6963) u8 loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6964) #define MAC_LOOPBACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6965) #define PHY_LOOPBACK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6967) u8 serdes_an_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6969) u8 mac_addr[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6971) u32 shmem_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6973) char fw_version[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6975) int pm_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6976) int pcix_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6978) const struct flash_spec *flash_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6979) u32 flash_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6981) int status_stats_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6983) struct bnx2_irq irq_tbl[BNX2_MAX_MSIX_VEC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6984) int irq_nvecs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6986) u8 func;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6988) u8 num_tx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6989) u8 num_rx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6991) int num_req_tx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6992) int num_req_rx_rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6994) u32 leds_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6995) u32 idle_chk_status_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6997) #ifdef BCM_CNIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6998) struct mutex cnic_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6999) struct cnic_eth_dev cnic_eth_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7000) struct cnic_eth_dev *(*cnic_probe)(struct net_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7001) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7003) const struct firmware *mips_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7004) const struct firmware *rv2p_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7005) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7007) #define BNX2_RD(bp, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7008) readl(bp->regview + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7010) #define BNX2_WR(bp, offset, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7011) writel(val, bp->regview + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7013) #define BNX2_WR16(bp, offset, val) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7014) writew(val, bp->regview + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7016) struct cpu_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7017) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7018) u32 mode_value_halt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7019) u32 mode_value_sstep;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7021) u32 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7022) u32 state_value_clear;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7024) u32 gpr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7025) u32 evmask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7026) u32 pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7027) u32 inst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7028) u32 bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7030) u32 spad_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7032) u32 mips_view_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7033) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7035) struct bnx2_fw_file_section {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7036) __be32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7037) __be32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7038) __be32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7039) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7041) struct bnx2_mips_fw_file_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7042) __be32 start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7043) struct bnx2_fw_file_section text;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7044) struct bnx2_fw_file_section data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7045) struct bnx2_fw_file_section rodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7048) struct bnx2_rv2p_fw_file_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7049) struct bnx2_fw_file_section rv2p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7050) __be32 fixup[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7051) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7053) struct bnx2_mips_fw_file {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7054) struct bnx2_mips_fw_file_entry com;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7055) struct bnx2_mips_fw_file_entry cp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7056) struct bnx2_mips_fw_file_entry rxp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7057) struct bnx2_mips_fw_file_entry tpat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7058) struct bnx2_mips_fw_file_entry txp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7059) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7061) struct bnx2_rv2p_fw_file {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7062) struct bnx2_rv2p_fw_file_entry proc1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7063) struct bnx2_rv2p_fw_file_entry proc2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7066) #define RV2P_P1_FIXUP_PAGE_SIZE_IDX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7067) #define RV2P_BD_PAGE_SIZE_MSK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7068) #define RV2P_BD_PAGE_SIZE ((BNX2_PAGE_SIZE / 16) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7070) #define RV2P_PROC1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7071) #define RV2P_PROC2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7074) /* This value (in milliseconds) determines the frequency of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7075) * issuing the PULSE message code. The firmware monitors this periodic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7076) * pulse to determine when to switch to an OS-absent mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7077) #define BNX2_DRV_PULSE_PERIOD_MS 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7079) /* This value (in milliseconds) determines how long the driver should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7080) * wait for an acknowledgement from the firmware before timing out. Once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7081) * the firmware has timed out, the driver will assume there is no firmware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7082) * running and there won't be any firmware-driver synchronization during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7083) * driver reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7084) #define BNX2_FW_ACK_TIME_OUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7087) #define BNX2_DRV_RESET_SIGNATURE 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7088) #define BNX2_DRV_RESET_SIGNATURE_MAGIC 0x4841564b /* HAVK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7089) //#define DRV_RESET_SIGNATURE_MAGIC 0x47495352 /* RSIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7091) #define BNX2_DRV_MB 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7092) #define BNX2_DRV_MSG_CODE 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7093) #define BNX2_DRV_MSG_CODE_RESET 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7094) #define BNX2_DRV_MSG_CODE_UNLOAD 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7095) #define BNX2_DRV_MSG_CODE_SHUTDOWN 0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7096) #define BNX2_DRV_MSG_CODE_SUSPEND_WOL 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7097) #define BNX2_DRV_MSG_CODE_FW_TIMEOUT 0x05000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7098) #define BNX2_DRV_MSG_CODE_PULSE 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7099) #define BNX2_DRV_MSG_CODE_DIAG 0x07000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7100) #define BNX2_DRV_MSG_CODE_SUSPEND_NO_WOL 0x09000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7101) #define BNX2_DRV_MSG_CODE_UNLOAD_LNK_DN 0x0b000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7102) #define BNX2_DRV_MSG_CODE_KEEP_VLAN_UPDATE 0x0d000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7103) #define BNX2_DRV_MSG_CODE_CMD_SET_LINK 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7105) #define BNX2_DRV_MSG_DATA 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7106) #define BNX2_DRV_MSG_DATA_WAIT0 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7107) #define BNX2_DRV_MSG_DATA_WAIT1 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7108) #define BNX2_DRV_MSG_DATA_WAIT2 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7109) #define BNX2_DRV_MSG_DATA_WAIT3 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7111) #define BNX2_DRV_MSG_SEQ 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7113) #define BNX2_FW_MB 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7114) #define BNX2_FW_MSG_ACK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7115) #define BNX2_FW_MSG_STATUS_MASK 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7116) #define BNX2_FW_MSG_STATUS_OK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7117) #define BNX2_FW_MSG_STATUS_FAILURE 0x00ff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7119) #define BNX2_LINK_STATUS 0x0000000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7120) #define BNX2_LINK_STATUS_INIT_VALUE 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7121) #define BNX2_LINK_STATUS_LINK_UP 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7122) #define BNX2_LINK_STATUS_LINK_DOWN 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7123) #define BNX2_LINK_STATUS_SPEED_MASK 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7124) #define BNX2_LINK_STATUS_AN_INCOMPLETE (0<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7125) #define BNX2_LINK_STATUS_10HALF (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7126) #define BNX2_LINK_STATUS_10FULL (2<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7127) #define BNX2_LINK_STATUS_100HALF (3<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7128) #define BNX2_LINK_STATUS_100BASE_T4 (4<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7129) #define BNX2_LINK_STATUS_100FULL (5<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7130) #define BNX2_LINK_STATUS_1000HALF (6<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7131) #define BNX2_LINK_STATUS_1000FULL (7<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7132) #define BNX2_LINK_STATUS_2500HALF (8<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7133) #define BNX2_LINK_STATUS_2500FULL (9<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7134) #define BNX2_LINK_STATUS_AN_ENABLED (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7135) #define BNX2_LINK_STATUS_AN_COMPLETE (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7136) #define BNX2_LINK_STATUS_PARALLEL_DET (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7137) #define BNX2_LINK_STATUS_RESERVED (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7138) #define BNX2_LINK_STATUS_PARTNER_AD_1000FULL (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7139) #define BNX2_LINK_STATUS_PARTNER_AD_1000HALF (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7140) #define BNX2_LINK_STATUS_PARTNER_AD_100BT4 (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7141) #define BNX2_LINK_STATUS_PARTNER_AD_100FULL (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7142) #define BNX2_LINK_STATUS_PARTNER_AD_100HALF (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7143) #define BNX2_LINK_STATUS_PARTNER_AD_10FULL (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7144) #define BNX2_LINK_STATUS_PARTNER_AD_10HALF (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7145) #define BNX2_LINK_STATUS_TX_FC_ENABLED (1<<16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7146) #define BNX2_LINK_STATUS_RX_FC_ENABLED (1<<17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7147) #define BNX2_LINK_STATUS_PARTNER_SYM_PAUSE_CAP (1<<18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7148) #define BNX2_LINK_STATUS_PARTNER_ASYM_PAUSE_CAP (1<<19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7149) #define BNX2_LINK_STATUS_SERDES_LINK (1<<20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7150) #define BNX2_LINK_STATUS_PARTNER_AD_2500FULL (1<<21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7151) #define BNX2_LINK_STATUS_PARTNER_AD_2500HALF (1<<22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7152) #define BNX2_LINK_STATUS_HEART_BEAT_EXPIRED (1<<31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7154) #define BNX2_DRV_PULSE_MB 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7155) #define BNX2_DRV_PULSE_SEQ_MASK 0x00007fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7157) /* Indicate to the firmware not to go into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7158) * OS absent when it is not getting driver pulse.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7159) * This is used for debugging. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7160) #define BNX2_DRV_MSG_DATA_PULSE_CODE_ALWAYS_ALIVE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7162) #define BNX2_DRV_MB_ARG0 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7163) #define BNX2_NETLINK_SET_LINK_SPEED_10HALF (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7164) #define BNX2_NETLINK_SET_LINK_SPEED_10FULL (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7165) #define BNX2_NETLINK_SET_LINK_SPEED_10 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7166) (BNX2_NETLINK_SET_LINK_SPEED_10HALF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7167) BNX2_NETLINK_SET_LINK_SPEED_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7168) #define BNX2_NETLINK_SET_LINK_SPEED_100HALF (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7169) #define BNX2_NETLINK_SET_LINK_SPEED_100FULL (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7170) #define BNX2_NETLINK_SET_LINK_SPEED_100 \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7171) (BNX2_NETLINK_SET_LINK_SPEED_100HALF | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7172) BNX2_NETLINK_SET_LINK_SPEED_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7173) #define BNX2_NETLINK_SET_LINK_SPEED_1GHALF (1<<4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7174) #define BNX2_NETLINK_SET_LINK_SPEED_1GFULL (1<<5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7175) #define BNX2_NETLINK_SET_LINK_SPEED_2G5HALF (1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7176) #define BNX2_NETLINK_SET_LINK_SPEED_2G5FULL (1<<7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7177) #define BNX2_NETLINK_SET_LINK_SPEED_10GHALF (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7178) #define BNX2_NETLINK_SET_LINK_SPEED_10GFULL (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7179) #define BNX2_NETLINK_SET_LINK_ENABLE_AUTONEG (1<<10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7180) #define BNX2_NETLINK_SET_LINK_PHY_APP_REMOTE (1<<11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7181) #define BNX2_NETLINK_SET_LINK_FC_SYM_PAUSE (1<<12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7182) #define BNX2_NETLINK_SET_LINK_FC_ASYM_PAUSE (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7183) #define BNX2_NETLINK_SET_LINK_ETH_AT_WIRESPEED (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7184) #define BNX2_NETLINK_SET_LINK_PHY_RESET (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7186) #define BNX2_DEV_INFO_SIGNATURE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7187) #define BNX2_DEV_INFO_SIGNATURE_MAGIC 0x44564900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7188) #define BNX2_DEV_INFO_SIGNATURE_MAGIC_MASK 0xffffff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7189) #define BNX2_DEV_INFO_FEATURE_CFG_VALID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7190) #define BNX2_DEV_INFO_SECONDARY_PORT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7191) #define BNX2_DEV_INFO_DRV_ALWAYS_ALIVE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7193) #define BNX2_SHARED_HW_CFG_PART_NUM 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7195) #define BNX2_SHARED_HW_CFG_POWER_DISSIPATED 0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7196) #define BNX2_SHARED_HW_CFG_POWER_STATE_D3_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7197) #define BNX2_SHARED_HW_CFG_POWER_STATE_D2_MASK 0xff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7198) #define BNX2_SHARED_HW_CFG_POWER_STATE_D1_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7199) #define BNX2_SHARED_HW_CFG_POWER_STATE_D0_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7201) #define BNX2_SHARED_HW_CFG POWER_CONSUMED 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7202) #define BNX2_SHARED_HW_CFG_CONFIG 0x0000003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7203) #define BNX2_SHARED_HW_CFG_DESIGN_NIC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7204) #define BNX2_SHARED_HW_CFG_DESIGN_LOM 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7205) #define BNX2_SHARED_HW_CFG_PHY_COPPER 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7206) #define BNX2_SHARED_HW_CFG_PHY_FIBER 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7207) #define BNX2_SHARED_HW_CFG_PHY_2_5G 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7208) #define BNX2_SHARED_HW_CFG_PHY_BACKPLANE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7209) #define BNX2_SHARED_HW_CFG_LED_MODE_SHIFT_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7210) #define BNX2_SHARED_HW_CFG_LED_MODE_MASK 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7211) #define BNX2_SHARED_HW_CFG_LED_MODE_MAC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7212) #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY1 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7213) #define BNX2_SHARED_HW_CFG_LED_MODE_GPHY2 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7214) #define BNX2_SHARED_HW_CFG_GIG_LINK_ON_VAUX 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7216) #define BNX2_SHARED_HW_CFG_CONFIG2 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7217) #define BNX2_SHARED_HW_CFG2_NVM_SIZE_MASK 0x00fff000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7219) #define BNX2_DEV_INFO_BC_REV 0x0000004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7221) #define BNX2_PORT_HW_CFG_MAC_UPPER 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7222) #define BNX2_PORT_HW_CFG_UPPERMAC_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7224) #define BNX2_PORT_HW_CFG_MAC_LOWER 0x00000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7225) #define BNX2_PORT_HW_CFG_CONFIG 0x00000058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7226) #define BNX2_PORT_HW_CFG_CFG_TXCTL3_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7227) #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_MASK 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7228) #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_AN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7229) #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_1G 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7230) #define BNX2_PORT_HW_CFG_CFG_DFLT_LINK_2_5G 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7232) #define BNX2_PORT_HW_CFG_IMD_MAC_A_UPPER 0x00000068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7233) #define BNX2_PORT_HW_CFG_IMD_MAC_A_LOWER 0x0000006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7234) #define BNX2_PORT_HW_CFG_IMD_MAC_B_UPPER 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7235) #define BNX2_PORT_HW_CFG_IMD_MAC_B_LOWER 0x00000074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7236) #define BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER 0x00000078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7237) #define BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER 0x0000007c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7239) #define BNX2_DEV_INFO_PER_PORT_HW_CONFIG2 0x000000b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7241) #define BNX2_DEV_INFO_FORMAT_REV 0x000000c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7242) #define BNX2_DEV_INFO_FORMAT_REV_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7243) #define BNX2_DEV_INFO_FORMAT_REV_ID ('A' << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7245) #define BNX2_SHARED_FEATURE 0x000000c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7246) #define BNX2_SHARED_FEATURE_MASK 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7248) #define BNX2_PORT_FEATURE 0x000000d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7249) #define BNX2_PORT2_FEATURE 0x00000014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7250) #define BNX2_PORT_FEATURE_WOL_ENABLED 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7251) #define BNX2_PORT_FEATURE_MBA_ENABLED 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7252) #define BNX2_PORT_FEATURE_ASF_ENABLED 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7253) #define BNX2_PORT_FEATURE_IMD_ENABLED 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7254) #define BNX2_PORT_FEATURE_BAR1_SIZE_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7255) #define BNX2_PORT_FEATURE_BAR1_SIZE_DISABLED 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7256) #define BNX2_PORT_FEATURE_BAR1_SIZE_64K 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7257) #define BNX2_PORT_FEATURE_BAR1_SIZE_128K 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7258) #define BNX2_PORT_FEATURE_BAR1_SIZE_256K 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7259) #define BNX2_PORT_FEATURE_BAR1_SIZE_512K 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7260) #define BNX2_PORT_FEATURE_BAR1_SIZE_1M 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7261) #define BNX2_PORT_FEATURE_BAR1_SIZE_2M 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7262) #define BNX2_PORT_FEATURE_BAR1_SIZE_4M 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7263) #define BNX2_PORT_FEATURE_BAR1_SIZE_8M 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7264) #define BNX2_PORT_FEATURE_BAR1_SIZE_16M 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7265) #define BNX2_PORT_FEATURE_BAR1_SIZE_32M 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7266) #define BNX2_PORT_FEATURE_BAR1_SIZE_64M 0xb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7267) #define BNX2_PORT_FEATURE_BAR1_SIZE_128M 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7268) #define BNX2_PORT_FEATURE_BAR1_SIZE_256M 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7269) #define BNX2_PORT_FEATURE_BAR1_SIZE_512M 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7270) #define BNX2_PORT_FEATURE_BAR1_SIZE_1G 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7272) #define BNX2_PORT_FEATURE_WOL 0xdc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7273) #define BNX2_PORT2_FEATURE_WOL 0x150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7274) #define BNX2_PORT_FEATURE_WOL_DEFAULT_SHIFT_BITS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7275) #define BNX2_PORT_FEATURE_WOL_DEFAULT_MASK 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7276) #define BNX2_PORT_FEATURE_WOL_DEFAULT_DISABLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7277) #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7278) #define BNX2_PORT_FEATURE_WOL_DEFAULT_ACPI 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7279) #define BNX2_PORT_FEATURE_WOL_DEFAULT_MAGIC_AND_ACPI 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7280) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7281) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_AUTONEG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7282) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10HALF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7283) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_10FULL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7284) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100HALF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7285) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_100FULL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7286) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000HALF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7287) #define BNX2_PORT_FEATURE_WOL_LINK_SPEED_1000FULL 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7288) #define BNX2_PORT_FEATURE_WOL_AUTONEG_ADVERTISE_1000 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7289) #define BNX2_PORT_FEATURE_WOL_RESERVED_PAUSE_CAP 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7290) #define BNX2_PORT_FEATURE_WOL_RESERVED_ASYM_PAUSE_CAP 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7292) #define BNX2_PORT_FEATURE_MBA 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7293) #define BNX2_PORT2_FEATURE_MBA 0x154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7294) #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT_BITS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7295) #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7296) #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7297) #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7298) #define BNX2_PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7299) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_SHIFT_BITS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7300) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7301) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_AUTONEG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7302) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10HALF 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7303) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_10FULL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7304) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100HALF 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7305) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_100FULL 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7306) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000HALF 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7307) #define BNX2_PORT_FEATURE_MBA_LINK_SPEED_1000FULL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7308) #define BNX2_PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7309) #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7310) #define BNX2_PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7311) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT_BITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7312) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0xff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7313) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7314) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1K 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7315) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7316) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7317) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7318) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7319) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7320) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7321) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7322) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7323) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0xa00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7324) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0xb00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7325) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0xc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7326) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0xd00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7327) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7328) #define BNX2_PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0xf00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7329) #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT_BITS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7330) #define BNX2_PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7331) #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT_BITS 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7332) #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7333) #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7334) #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7335) #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7336) #define BNX2_PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7338) #define BNX2_PORT_FEATURE_IMD 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7339) #define BNX2_PORT2_FEATURE_IMD 0x158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7340) #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_DEFAULT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7341) #define BNX2_PORT_FEATURE_IMD_LINK_OVERRIDE_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7343) #define BNX2_PORT_FEATURE_VLAN 0xe8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7344) #define BNX2_PORT2_FEATURE_VLAN 0x15c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7345) #define BNX2_PORT_FEATURE_MBA_VLAN_TAG_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7346) #define BNX2_PORT_FEATURE_MBA_VLAN_ENABLE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7348) #define BNX2_MFW_VER_PTR 0x00000014c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7350) #define BNX2_BC_STATE_RESET_TYPE 0x000001c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7351) #define BNX2_BC_STATE_RESET_TYPE_SIG 0x00005254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7352) #define BNX2_BC_STATE_RESET_TYPE_SIG_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7353) #define BNX2_BC_STATE_RESET_TYPE_NONE (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7354) 0x00010000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7355) #define BNX2_BC_STATE_RESET_TYPE_PCI (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7356) 0x00020000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7357) #define BNX2_BC_STATE_RESET_TYPE_VAUX (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7358) 0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7359) #define BNX2_BC_STATE_RESET_TYPE_DRV_MASK DRV_MSG_CODE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7360) #define BNX2_BC_STATE_RESET_TYPE_DRV_RESET (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7361) DRV_MSG_CODE_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7362) #define BNX2_BC_STATE_RESET_TYPE_DRV_UNLOAD (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7363) DRV_MSG_CODE_UNLOAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7364) #define BNX2_BC_STATE_RESET_TYPE_DRV_SHUTDOWN (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7365) DRV_MSG_CODE_SHUTDOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7366) #define BNX2_BC_STATE_RESET_TYPE_DRV_WOL (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7367) DRV_MSG_CODE_WOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7368) #define BNX2_BC_STATE_RESET_TYPE_DRV_DIAG (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7369) DRV_MSG_CODE_DIAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7370) #define BNX2_BC_STATE_RESET_TYPE_VALUE(msg) (BNX2_BC_STATE_RESET_TYPE_SIG | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7371) (msg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7373) #define BNX2_BC_RESET_TYPE 0x000001c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7375) #define BNX2_BC_STATE 0x000001c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7376) #define BNX2_BC_STATE_ERR_MASK 0x0000ff00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7377) #define BNX2_BC_STATE_SIGN 0x42530000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7378) #define BNX2_BC_STATE_SIGN_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7379) #define BNX2_BC_STATE_BC1_START (BNX2_BC_STATE_SIGN | 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7380) #define BNX2_BC_STATE_GET_NVM_CFG1 (BNX2_BC_STATE_SIGN | 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7381) #define BNX2_BC_STATE_PROG_BAR (BNX2_BC_STATE_SIGN | 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7382) #define BNX2_BC_STATE_INIT_VID (BNX2_BC_STATE_SIGN | 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7383) #define BNX2_BC_STATE_GET_NVM_CFG2 (BNX2_BC_STATE_SIGN | 0x5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7384) #define BNX2_BC_STATE_APPLY_WKARND (BNX2_BC_STATE_SIGN | 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7385) #define BNX2_BC_STATE_LOAD_BC2 (BNX2_BC_STATE_SIGN | 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7386) #define BNX2_BC_STATE_GOING_BC2 (BNX2_BC_STATE_SIGN | 0x8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7387) #define BNX2_BC_STATE_GOING_DIAG (BNX2_BC_STATE_SIGN | 0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7388) #define BNX2_BC_STATE_RT_FINAL_INIT (BNX2_BC_STATE_SIGN | 0x81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7389) #define BNX2_BC_STATE_RT_WKARND (BNX2_BC_STATE_SIGN | 0x82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7390) #define BNX2_BC_STATE_RT_DRV_PULSE (BNX2_BC_STATE_SIGN | 0x83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7391) #define BNX2_BC_STATE_RT_FIOEVTS (BNX2_BC_STATE_SIGN | 0x84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7392) #define BNX2_BC_STATE_RT_DRV_CMD (BNX2_BC_STATE_SIGN | 0x85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7393) #define BNX2_BC_STATE_RT_LOW_POWER (BNX2_BC_STATE_SIGN | 0x86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7394) #define BNX2_BC_STATE_RT_SET_WOL (BNX2_BC_STATE_SIGN | 0x87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7395) #define BNX2_BC_STATE_RT_OTHER_FW (BNX2_BC_STATE_SIGN | 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7396) #define BNX2_BC_STATE_RT_GOING_D3 (BNX2_BC_STATE_SIGN | 0x89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7397) #define BNX2_BC_STATE_ERR_BAD_VERSION (BNX2_BC_STATE_SIGN | 0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7398) #define BNX2_BC_STATE_ERR_BAD_BC2_CRC (BNX2_BC_STATE_SIGN | 0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7399) #define BNX2_BC_STATE_ERR_BC1_LOOP (BNX2_BC_STATE_SIGN | 0x0300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7400) #define BNX2_BC_STATE_ERR_UNKNOWN_CMD (BNX2_BC_STATE_SIGN | 0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7401) #define BNX2_BC_STATE_ERR_DRV_DEAD (BNX2_BC_STATE_SIGN | 0x0500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7402) #define BNX2_BC_STATE_ERR_NO_RXP (BNX2_BC_STATE_SIGN | 0x0600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7403) #define BNX2_BC_STATE_ERR_TOO_MANY_RBUF (BNX2_BC_STATE_SIGN | 0x0700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7405) #define BNX2_BC_STATE_CONDITION 0x000001c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7406) #define BNX2_CONDITION_MFW_RUN_UNKNOWN 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7407) #define BNX2_CONDITION_MFW_RUN_IPMI 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7408) #define BNX2_CONDITION_MFW_RUN_UMP 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7409) #define BNX2_CONDITION_MFW_RUN_NCSI 0x00006000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7410) #define BNX2_CONDITION_MFW_RUN_NONE 0x0000e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7411) #define BNX2_CONDITION_MFW_RUN_MASK 0x0000e000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7412) #define BNX2_CONDITION_PM_STATE_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7413) #define BNX2_CONDITION_PM_STATE_FULL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7414) #define BNX2_CONDITION_PM_STATE_PREP 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7415) #define BNX2_CONDITION_PM_STATE_UNPREP 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7417) #define BNX2_BC_STATE_DEBUG_CMD 0x1dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7418) #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE 0x42440000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7419) #define BNX2_BC_STATE_BC_DBG_CMD_SIGNATURE_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7420) #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_CNT_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7421) #define BNX2_BC_STATE_BC_DBG_CMD_LOOP_INFINITE 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7423) #define BNX2_FW_EVT_CODE_MB 0x354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7424) #define BNX2_FW_EVT_CODE_SW_TIMER_EXPIRATION_EVENT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7425) #define BNX2_FW_EVT_CODE_LINK_EVENT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7427) #define BNX2_DRV_ACK_CAP_MB 0x364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7428) #define BNX2_DRV_ACK_CAP_SIGNATURE 0x35450000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7429) #define BNX2_CAPABILITY_SIGNATURE_MASK 0xFFFF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7431) #define BNX2_FW_CAP_MB 0x368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7432) #define BNX2_FW_CAP_SIGNATURE 0xaa550000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7433) #define BNX2_FW_ACK_DRV_SIGNATURE 0x52500000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7434) #define BNX2_FW_CAP_SIGNATURE_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7435) #define BNX2_FW_CAP_REMOTE_PHY_CAPABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7436) #define BNX2_FW_CAP_REMOTE_PHY_PRESENT 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7437) #define BNX2_FW_CAP_MFW_CAN_KEEP_VLAN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7438) #define BNX2_FW_CAP_BC_CAN_KEEP_VLAN 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7439) #define BNX2_FW_CAP_CAN_KEEP_VLAN (BNX2_FW_CAP_BC_CAN_KEEP_VLAN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7440) BNX2_FW_CAP_MFW_CAN_KEEP_VLAN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7442) #define BNX2_RPHY_SIGNATURE 0x36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7443) #define BNX2_RPHY_LOAD_SIGNATURE 0x5a5a5a5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7445) #define BNX2_RPHY_FLAGS 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7446) #define BNX2_RPHY_SERDES_LINK 0x374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7447) #define BNX2_RPHY_COPPER_LINK 0x378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7449) #define BNX2_ISCSI_INITIATOR 0x3dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7450) #define BNX2_ISCSI_INITIATOR_EN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7452) #define BNX2_ISCSI_MAX_CONN 0x3e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7453) #define BNX2_ISCSI_MAX_CONN_MASK 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7454) #define BNX2_ISCSI_MAX_CONN_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7456) #define HOST_VIEW_SHMEM_BASE 0x167c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7458) #define DP_SHMEM_LINE(bp, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7459) netdev_err(bp->dev, "DEBUG: %08x: %08x %08x %08x %08x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7460) offset, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7461) bnx2_shmem_rd(bp, offset), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7462) bnx2_shmem_rd(bp, offset + 4), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7463) bnx2_shmem_rd(bp, offset + 8), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7464) bnx2_shmem_rd(bp, offset + 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7466) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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