^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _BGMAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _BGMAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define BGMAC_DEV_CTL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define BGMAC_DC_TSM 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define BGMAC_DC_CFCO 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define BGMAC_DC_RLSS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define BGMAC_DC_MROR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define BGMAC_DC_FCM_MASK 0x00000060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define BGMAC_DC_FCM_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define BGMAC_DC_NAE 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define BGMAC_DC_TF 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define BGMAC_DC_RDS_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define BGMAC_DC_RDS_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define BGMAC_DC_TDS_MASK 0x000c0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define BGMAC_DC_TDS_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define BGMAC_DEV_STATUS 0x004 /* Configuration of the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define BGMAC_DS_RBF 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define BGMAC_DS_RDF 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define BGMAC_DS_RIF 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define BGMAC_DS_TBF 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define BGMAC_DS_TDF 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define BGMAC_DS_TIF 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define BGMAC_DS_PO 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define BGMAC_DS_MM_MASK 0x00000300 /* Mode of the interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define BGMAC_DS_MM_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define BGMAC_BIST_STATUS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define BGMAC_INT_STATUS 0x020 /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define BGMAC_IS_MRO 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BGMAC_IS_MTO 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define BGMAC_IS_TFD 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define BGMAC_IS_LS 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define BGMAC_IS_MDIO 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BGMAC_IS_MR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BGMAC_IS_MT 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define BGMAC_IS_TO 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define BGMAC_IS_DESC_ERR 0x00000400 /* Descriptor error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define BGMAC_IS_DATA_ERR 0x00000800 /* Data error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define BGMAC_IS_DESC_PROT_ERR 0x00001000 /* Descriptor protocol error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define BGMAC_IS_RX_DESC_UNDERF 0x00002000 /* Receive descriptor underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define BGMAC_IS_RX_F_OVERF 0x00004000 /* Receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define BGMAC_IS_TX_F_UNDERF 0x00008000 /* Transmit FIFO underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define BGMAC_IS_RX 0x00010000 /* Interrupt for RX queue 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define BGMAC_IS_TX0 0x01000000 /* Interrupt for TX queue 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define BGMAC_IS_TX1 0x02000000 /* Interrupt for TX queue 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define BGMAC_IS_TX2 0x04000000 /* Interrupt for TX queue 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define BGMAC_IS_TX3 0x08000000 /* Interrupt for TX queue 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define BGMAC_IS_TX_MASK 0x0f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define BGMAC_IS_INTMASK 0x0f01fcff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define BGMAC_IS_ERRMASK 0x0000fc00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define BGMAC_INT_MASK 0x024 /* Interrupt mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define BGMAC_GP_TIMER 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define BGMAC_INT_RECV_LAZY 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define BGMAC_IRL_TO_MASK 0x00ffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define BGMAC_IRL_FC_MASK 0xff000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define BGMAC_IRL_FC_SHIFT 24 /* Shift the number of interrupts triggered per received frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define BGMAC_FLOW_CTL_THRESH 0x104 /* Flow control thresholds */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define BGMAC_WRRTHRESH 0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define BGMAC_GMAC_IDLE_CNT_THRESH 0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define BGMAC_PHY_ACCESS 0x180 /* PHY access address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define BGMAC_PA_DATA_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define BGMAC_PA_ADDR_MASK 0x001f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define BGMAC_PA_ADDR_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define BGMAC_PA_REG_MASK 0x1f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define BGMAC_PA_REG_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define BGMAC_PA_WRITE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define BGMAC_PA_START 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define BGMAC_PHY_CNTL 0x188 /* PHY control address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define BGMAC_PC_EPA_MASK 0x0000001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define BGMAC_PC_MCT_MASK 0x007f0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define BGMAC_PC_MCT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BGMAC_PC_MTE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define BGMAC_TXQ_CTL 0x18c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BGMAC_TXQ_CTL_DBT_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BGMAC_TXQ_CTL_DBT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define BGMAC_RXQ_CTL 0x190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define BGMAC_RXQ_CTL_DBT_MASK 0x00000fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BGMAC_RXQ_CTL_DBT_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BGMAC_RXQ_CTL_PTE 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BGMAC_RXQ_CTL_MDP_MASK 0x3f000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BGMAC_RXQ_CTL_MDP_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BGMAC_GPIO_SELECT 0x194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BGMAC_GPIO_OUTPUT_EN 0x198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* For 0x1e0 see BCMA_CLKCTLST. Below are BGMAC specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define BGMAC_BCMA_CLKCTLST_MISC_PLL_ST 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define BGMAC_HW_WAR 0x1e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define BGMAC_PWR_CTL 0x1e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define BGMAC_DMA_BASE0 0x200 /* Tx and Rx controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BGMAC_DMA_BASE1 0x240 /* Tx controller only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BGMAC_DMA_BASE2 0x280 /* Tx controller only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BGMAC_DMA_BASE3 0x2C0 /* Tx controller only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BGMAC_TX_GOOD_OCTETS 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BGMAC_TX_GOOD_OCTETS_HIGH 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BGMAC_TX_GOOD_PKTS 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BGMAC_TX_OCTETS 0x30c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BGMAC_TX_OCTETS_HIGH 0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BGMAC_TX_PKTS 0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BGMAC_TX_BROADCAST_PKTS 0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BGMAC_TX_MULTICAST_PKTS 0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BGMAC_TX_LEN_64 0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define BGMAC_TX_LEN_65_TO_127 0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define BGMAC_TX_LEN_128_TO_255 0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BGMAC_TX_LEN_256_TO_511 0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BGMAC_TX_LEN_512_TO_1023 0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BGMAC_TX_LEN_1024_TO_1522 0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BGMAC_TX_LEN_1523_TO_2047 0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BGMAC_TX_LEN_2048_TO_4095 0x33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BGMAC_TX_LEN_4096_TO_8191 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BGMAC_TX_LEN_8192_TO_MAX 0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define BGMAC_TX_JABBER_PKTS 0x348 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define BGMAC_TX_OVERSIZE_PKTS 0x34c /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BGMAC_TX_FRAGMENT_PKTS 0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BGMAC_TX_UNDERRUNS 0x354 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BGMAC_TX_TOTAL_COLS 0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define BGMAC_TX_SINGLE_COLS 0x35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BGMAC_TX_MULTIPLE_COLS 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BGMAC_TX_EXCESSIVE_COLS 0x364 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BGMAC_TX_LATE_COLS 0x368 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BGMAC_TX_DEFERED 0x36c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define BGMAC_TX_CARRIER_LOST 0x370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define BGMAC_TX_PAUSE_PKTS 0x374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BGMAC_TX_UNI_PKTS 0x378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BGMAC_TX_Q0_PKTS 0x37c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BGMAC_TX_Q0_OCTETS 0x380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BGMAC_TX_Q0_OCTETS_HIGH 0x384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BGMAC_TX_Q1_PKTS 0x388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BGMAC_TX_Q1_OCTETS 0x38c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BGMAC_TX_Q1_OCTETS_HIGH 0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BGMAC_TX_Q2_PKTS 0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BGMAC_TX_Q2_OCTETS 0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BGMAC_TX_Q2_OCTETS_HIGH 0x39c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BGMAC_TX_Q3_PKTS 0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BGMAC_TX_Q3_OCTETS 0x3a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BGMAC_TX_Q3_OCTETS_HIGH 0x3a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BGMAC_RX_GOOD_OCTETS 0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BGMAC_RX_GOOD_OCTETS_HIGH 0x3b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define BGMAC_RX_GOOD_PKTS 0x3b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define BGMAC_RX_OCTETS 0x3bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BGMAC_RX_OCTETS_HIGH 0x3c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BGMAC_RX_PKTS 0x3c4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BGMAC_RX_BROADCAST_PKTS 0x3c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BGMAC_RX_MULTICAST_PKTS 0x3cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BGMAC_RX_LEN_64 0x3d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BGMAC_RX_LEN_65_TO_127 0x3d4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BGMAC_RX_LEN_128_TO_255 0x3d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BGMAC_RX_LEN_256_TO_511 0x3dc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BGMAC_RX_LEN_512_TO_1023 0x3e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BGMAC_RX_LEN_1024_TO_1522 0x3e4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BGMAC_RX_LEN_1523_TO_2047 0x3e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BGMAC_RX_LEN_2048_TO_4095 0x3ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define BGMAC_RX_LEN_4096_TO_8191 0x3f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define BGMAC_RX_LEN_8192_TO_MAX 0x3f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BGMAC_RX_JABBER_PKTS 0x3f8 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BGMAC_RX_OVERSIZE_PKTS 0x3fc /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define BGMAC_RX_FRAGMENT_PKTS 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BGMAC_RX_MISSED_PKTS 0x404 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BGMAC_RX_CRC_ALIGN_ERRS 0x408 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BGMAC_RX_UNDERSIZE 0x40c /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BGMAC_RX_CRC_ERRS 0x410 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define BGMAC_RX_ALIGN_ERRS 0x414 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define BGMAC_RX_SYMBOL_ERRS 0x418 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BGMAC_RX_PAUSE_PKTS 0x41c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BGMAC_RX_NONPAUSE_PKTS 0x420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define BGMAC_RX_SACHANGES 0x424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define BGMAC_RX_UNI_PKTS 0x428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define BGMAC_UNIMAC_VERSION 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define BGMAC_HDBKP_CTL 0x804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define BGMAC_CMDCFG 0x808 /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define BGMAC_CMDCFG_TE 0x00000001 /* Set to activate TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define BGMAC_CMDCFG_RE 0x00000002 /* Set to activate RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define BGMAC_CMDCFG_ES_MASK 0x0000000c /* Ethernet speed see gmac_speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define BGMAC_CMDCFG_ES_10 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define BGMAC_CMDCFG_ES_100 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BGMAC_CMDCFG_ES_1000 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define BGMAC_CMDCFG_ES_2500 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BGMAC_CMDCFG_PROM 0x00000010 /* Set to activate promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define BGMAC_CMDCFG_PAD_EN 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define BGMAC_CMDCFG_CF 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define BGMAC_CMDCFG_PF 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define BGMAC_CMDCFG_RPI 0x00000100 /* Unset to enable 802.3x tx flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define BGMAC_CMDCFG_TAI 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define BGMAC_CMDCFG_HD 0x00000400 /* Set if in half duplex mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define BGMAC_CMDCFG_HD_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define BGMAC_CMDCFG_SR_REV0 0x00000800 /* Set to reset mode, for core rev 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define BGMAC_CMDCFG_SR_REV4 0x00002000 /* Set to reset mode, for core rev >= 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define BGMAC_CMDCFG_ML 0x00008000 /* Set to activate mac loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define BGMAC_CMDCFG_AE 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define BGMAC_CMDCFG_CFE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define BGMAC_CMDCFG_NLC 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define BGMAC_CMDCFG_RL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define BGMAC_CMDCFG_RED 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define BGMAC_CMDCFG_PE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define BGMAC_CMDCFG_TPI 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define BGMAC_CMDCFG_AT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define BGMAC_MACADDR_HIGH 0x80c /* High 4 octets of own mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define BGMAC_MACADDR_LOW 0x810 /* Low 2 octets of own mac address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BGMAC_RXMAX_LENGTH 0x814 /* Max receive frame length with vlan tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define BGMAC_PAUSEQUANTA 0x818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define BGMAC_MAC_MODE 0x844
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define BGMAC_OUTERTAG 0x848
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define BGMAC_INNERTAG 0x84c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define BGMAC_TXIPG 0x85c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define BGMAC_PAUSE_CTL 0xb30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define BGMAC_TX_FLUSH 0xb34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define BGMAC_RX_STATUS 0xb38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define BGMAC_TX_STATUS 0xb3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* BCMA GMAC core specific IO Control (BCMA_IOCTL) flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define BGMAC_BCMA_IOCTL_SW_CLKEN 0x00000004 /* PHY Clock Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define BGMAC_BCMA_IOCTL_SW_RESET 0x00000008 /* PHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* The IOCTL values appear to be different in NS, NSP, and NS2, and do not match
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * the values directly above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define BGMAC_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define BGMAC_RESERVED_0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define BGMAC_SOURCE_SYNC_MODE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define BGMAC_DEST_SYNC_MODE_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define BGMAC_TX_CLK_OUT_INVERT_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define BGMAC_DIRECT_GMII_MODE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define BGMAC_CLK_250_SEL BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define BGMAC_AWCACHE (0xf << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define BGMAC_RESERVED_1 (0x1f << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define BGMAC_ARCACHE (0xf << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define BGMAC_AWUSER (0x3f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define BGMAC_ARUSER (0x3f << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define BGMAC_RESERVED BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* BCMA GMAC core specific IO status (BCMA_IOST) flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define BGMAC_BCMA_IOST_ATTACHED 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define BGMAC_NUM_MIB_TX_REGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) (((BGMAC_TX_Q3_OCTETS_HIGH - BGMAC_TX_GOOD_OCTETS) / 4) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define BGMAC_NUM_MIB_RX_REGS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) (((BGMAC_RX_UNI_PKTS - BGMAC_RX_GOOD_OCTETS) / 4) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define BGMAC_DMA_TX_CTL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define BGMAC_DMA_TX_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define BGMAC_DMA_TX_SUSPEND 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define BGMAC_DMA_TX_LOOPBACK 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define BGMAC_DMA_TX_FLUSH 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define BGMAC_DMA_TX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define BGMAC_DMA_TX_MR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define BGMAC_DMA_TX_MR_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define BGMAC_DMA_TX_MR_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define BGMAC_DMA_TX_PARITY_DISABLE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define BGMAC_DMA_TX_ADDREXT_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define BGMAC_DMA_TX_ADDREXT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define BGMAC_DMA_TX_BL_MASK 0x001C0000 /* BurstLen bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define BGMAC_DMA_TX_BL_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define BGMAC_DMA_TX_BL_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define BGMAC_DMA_TX_BL_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define BGMAC_DMA_TX_BL_64 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define BGMAC_DMA_TX_BL_128 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define BGMAC_DMA_TX_BL_256 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define BGMAC_DMA_TX_BL_512 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define BGMAC_DMA_TX_BL_1024 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define BGMAC_DMA_TX_PC_MASK 0x00E00000 /* Prefetch control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define BGMAC_DMA_TX_PC_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define BGMAC_DMA_TX_PC_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define BGMAC_DMA_TX_PC_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define BGMAC_DMA_TX_PC_8 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define BGMAC_DMA_TX_PC_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define BGMAC_DMA_TX_PT_MASK 0x03000000 /* Prefetch threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define BGMAC_DMA_TX_PT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define BGMAC_DMA_TX_PT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define BGMAC_DMA_TX_PT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define BGMAC_DMA_TX_PT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define BGMAC_DMA_TX_PT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define BGMAC_DMA_TX_INDEX 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define BGMAC_DMA_TX_RINGLO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define BGMAC_DMA_TX_RINGHI 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define BGMAC_DMA_TX_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define BGMAC_DMA_TX_STATDPTR 0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define BGMAC_DMA_TX_STAT 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define BGMAC_DMA_TX_STAT_DISABLED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define BGMAC_DMA_TX_STAT_ACTIVE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define BGMAC_DMA_TX_STAT_IDLEWAIT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define BGMAC_DMA_TX_STAT_STOPPED 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define BGMAC_DMA_TX_STAT_SUSP 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define BGMAC_DMA_TX_ERROR 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define BGMAC_DMA_TX_ERRDPTR 0x0001FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define BGMAC_DMA_TX_ERR 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define BGMAC_DMA_TX_ERR_NOERR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define BGMAC_DMA_TX_ERR_PROT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define BGMAC_DMA_TX_ERR_UNDERRUN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define BGMAC_DMA_TX_ERR_TRANSFER 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define BGMAC_DMA_TX_ERR_DESCREAD 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define BGMAC_DMA_TX_ERR_CORE 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define BGMAC_DMA_RX_CTL 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define BGMAC_DMA_RX_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define BGMAC_DMA_RX_FRAME_OFFSET_MASK 0x000000FE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define BGMAC_DMA_RX_FRAME_OFFSET_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define BGMAC_DMA_RX_DIRECT_FIFO 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define BGMAC_DMA_RX_OVERFLOW_CONT 0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define BGMAC_DMA_RX_PARITY_DISABLE 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define BGMAC_DMA_RX_MR_MASK 0x000000C0 /* Multiple outstanding reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define BGMAC_DMA_RX_MR_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define BGMAC_DMA_TX_MR_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define BGMAC_DMA_TX_MR_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define BGMAC_DMA_RX_ADDREXT_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define BGMAC_DMA_RX_ADDREXT_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define BGMAC_DMA_RX_BL_MASK 0x001C0000 /* BurstLen bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define BGMAC_DMA_RX_BL_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define BGMAC_DMA_RX_BL_16 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define BGMAC_DMA_RX_BL_32 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define BGMAC_DMA_RX_BL_64 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define BGMAC_DMA_RX_BL_128 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define BGMAC_DMA_RX_BL_256 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define BGMAC_DMA_RX_BL_512 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BGMAC_DMA_RX_BL_1024 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define BGMAC_DMA_RX_PC_MASK 0x00E00000 /* Prefetch control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define BGMAC_DMA_RX_PC_SHIFT 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define BGMAC_DMA_RX_PC_0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define BGMAC_DMA_RX_PC_4 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define BGMAC_DMA_RX_PC_8 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define BGMAC_DMA_RX_PC_16 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define BGMAC_DMA_RX_PT_MASK 0x03000000 /* Prefetch threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define BGMAC_DMA_RX_PT_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define BGMAC_DMA_RX_PT_1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define BGMAC_DMA_RX_PT_2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define BGMAC_DMA_RX_PT_4 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define BGMAC_DMA_RX_PT_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define BGMAC_DMA_RX_INDEX 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define BGMAC_DMA_RX_RINGLO 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define BGMAC_DMA_RX_RINGHI 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define BGMAC_DMA_RX_STATUS 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define BGMAC_DMA_RX_STATDPTR 0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define BGMAC_DMA_RX_STAT 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define BGMAC_DMA_RX_STAT_DISABLED 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define BGMAC_DMA_RX_STAT_ACTIVE 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define BGMAC_DMA_RX_STAT_IDLEWAIT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define BGMAC_DMA_RX_STAT_STOPPED 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define BGMAC_DMA_RX_STAT_SUSP 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define BGMAC_DMA_RX_ERROR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define BGMAC_DMA_RX_ERRDPTR 0x0001FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define BGMAC_DMA_RX_ERR 0xF0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define BGMAC_DMA_RX_ERR_NOERR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define BGMAC_DMA_RX_ERR_PROT 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define BGMAC_DMA_RX_ERR_UNDERRUN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define BGMAC_DMA_RX_ERR_TRANSFER 0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define BGMAC_DMA_RX_ERR_DESCREAD 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define BGMAC_DMA_RX_ERR_CORE 0x50000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define BGMAC_DESC_CTL0_EOT 0x10000000 /* End of ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define BGMAC_DESC_CTL0_IOC 0x20000000 /* IRQ on complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define BGMAC_DESC_CTL0_EOF 0x40000000 /* End of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define BGMAC_DESC_CTL0_SOF 0x80000000 /* Start of frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define BGMAC_DESC_CTL1_LEN 0x00003FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define BGMAC_PHY_NOREGS BRCM_PSEUDO_PHY_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define BGMAC_PHY_MASK 0x1F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define BGMAC_MAX_TX_RINGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define BGMAC_MAX_RX_RINGS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define BGMAC_TX_RING_SLOTS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define BGMAC_RX_RING_SLOTS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define BGMAC_RX_HEADER_LEN 28 /* Last 24 bytes are unused. Well... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define BGMAC_RX_FRAME_OFFSET 30 /* There are 2 unused bytes between header and real data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define BGMAC_RX_BUF_OFFSET (NET_SKB_PAD + NET_IP_ALIGN - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) BGMAC_RX_FRAME_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Jumbo frame size with FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define BGMAC_RX_MAX_FRAME_SIZE 9724
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define BGMAC_RX_BUF_SIZE (BGMAC_RX_FRAME_OFFSET + BGMAC_RX_MAX_FRAME_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define BGMAC_RX_ALLOC_SIZE (SKB_DATA_ALIGN(BGMAC_RX_BUF_SIZE + BGMAC_RX_BUF_OFFSET) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define BGMAC_BFL_ENETROBO 0x0010 /* has ephy roboswitch spi */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define BGMAC_BFL_ENETADM 0x0080 /* has ADMtek switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define BGMAC_BFL_ENETVLAN 0x0100 /* can do vlan */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define BGMAC_CHIPCTL_1_IF_TYPE_MASK 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define BGMAC_CHIPCTL_1_IF_TYPE_RMII 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define BGMAC_CHIPCTL_1_IF_TYPE_MII 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define BGMAC_CHIPCTL_1_IF_TYPE_RGMII 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define BGMAC_CHIPCTL_1_SW_TYPE_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define BGMAC_CHIPCTL_1_SW_TYPE_EPHY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYMII 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define BGMAC_CHIPCTL_1_SW_TYPE_RGMII 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define BGMAC_CHIPCTL_1_RXC_DLL_BYPASS 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define BGMAC_CHIPCTL_4_IF_TYPE_MASK 0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define BGMAC_CHIPCTL_4_IF_TYPE_RMII 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define BGMAC_CHIPCTL_4_IF_TYPE_MII 0x00001000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define BGMAC_CHIPCTL_4_IF_TYPE_RGMII 0x00002000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define BGMAC_CHIPCTL_4_SW_TYPE_MASK 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define BGMAC_CHIPCTL_4_SW_TYPE_EPHY 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define BGMAC_CHIPCTL_4_SW_TYPE_EPHYMII 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define BGMAC_CHIPCTL_4_SW_TYPE_EPHYRMII 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define BGMAC_CHIPCTL_4_SW_TYPE_RGMII 0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define BGMAC_CHIPCTL_7_IF_TYPE_MASK 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define BGMAC_CHIPCTL_7_IF_TYPE_RMII 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define BGMAC_CHIPCTL_7_IF_TYPE_MII 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define BGMAC_CHIPCTL_7_IF_TYPE_RGMII 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define BGMAC_WEIGHT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define ETHER_MAX_LEN (ETH_FRAME_LEN + ETH_FCS_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Feature Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define BGMAC_FEAT_TX_MASK_SETUP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define BGMAC_FEAT_RX_MASK_SETUP BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define BGMAC_FEAT_IOST_ATTACHED BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BGMAC_FEAT_NO_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define BGMAC_FEAT_MISC_PLL_REQ BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define BGMAC_FEAT_SW_TYPE_PHY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define BGMAC_FEAT_SW_TYPE_EPHYRMII BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BGMAC_FEAT_SW_TYPE_RGMII BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define BGMAC_FEAT_CMN_PHY_CTL BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define BGMAC_FEAT_FLW_CTRL1 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BGMAC_FEAT_FLW_CTRL2 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BGMAC_FEAT_SET_RXQ_CLK BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define BGMAC_FEAT_CLKCTLST BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BGMAC_FEAT_NO_CLR_MIB BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define BGMAC_FEAT_FORCE_SPEED_2500 BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BGMAC_FEAT_CMDCFG_SR_REV4 BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BGMAC_FEAT_IRQ_ID_OOB_6 BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BGMAC_FEAT_CC4_IF_SW_TYPE BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define BGMAC_FEAT_CC7_IF_TYPE_RGMII BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define BGMAC_FEAT_IDM_MASK BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct bgmac_slot_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct bgmac_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) __le32 ctl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) __le32 ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) __le32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __le32 addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) enum bgmac_dma_ring_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) BGMAC_DMA_RING_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) BGMAC_DMA_RING_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * bgmac_dma_ring - contains info about DMA ring (either TX or RX one)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * @start: index of the first slot containing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * @end: index of a slot that can *not* be read (yet)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Be really aware of the specific @end meaning. It's an index of a slot *after*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * the one containing data that can be read. If @start equals @end the ring is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct bgmac_dma_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct bgmac_dma_desc *cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dma_addr_t dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 index_base; /* Used for unaligned rings only, otherwise 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u16 mmio_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) bool unaligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct bgmac_slot_info slots[BGMAC_RX_RING_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct bgmac_rx_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) __le16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) __le16 pad[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) struct bgmac {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) void __iomem *idm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) void __iomem *nicpm_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) } plat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Reference to CMN core for BCM4706 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct bcma_device *cmn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) } bcma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 feature_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct net_device *net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct bgmac_dma_ring tx_ring[BGMAC_MAX_TX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct bgmac_dma_ring rx_ring[BGMAC_MAX_RX_RINGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) bool stats_grabbed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 mib_tx_regs[BGMAC_NUM_MIB_TX_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 mib_rx_regs[BGMAC_NUM_MIB_RX_REGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* Int */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /* Current MAC state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int mac_speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) int mac_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) bool has_robosw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) bool loopback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u32 (*read)(struct bgmac *bgmac, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) void (*write)(struct bgmac *bgmac, u16 offset, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 (*idm_read)(struct bgmac *bgmac, u16 offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void (*idm_write)(struct bgmac *bgmac, u16 offset, u32 value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) bool (*clk_enabled)(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) void (*clk_enable)(struct bgmac *bgmac, u32 flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void (*cco_ctl_maskset)(struct bgmac *bgmac, u32 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) u32 (*get_bus_clock)(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) void (*cmn_maskset32)(struct bgmac *bgmac, u16 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int (*phy_connect)(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct bgmac *bgmac_alloc(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int bgmac_enet_probe(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) void bgmac_enet_remove(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) void bgmac_adjust_link(struct net_device *net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) int bgmac_phy_connect_direct(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int bgmac_enet_suspend(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int bgmac_enet_resume(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) void bcma_mdio_mii_unregister(struct mii_bus *mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) static inline u32 bgmac_read(struct bgmac *bgmac, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return bgmac->read(bgmac, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) static inline void bgmac_write(struct bgmac *bgmac, u16 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) bgmac->write(bgmac, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static inline u32 bgmac_idm_read(struct bgmac *bgmac, u16 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return bgmac->idm_read(bgmac, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static inline void bgmac_idm_write(struct bgmac *bgmac, u16 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) bgmac->idm_write(bgmac, offset, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static inline bool bgmac_clk_enabled(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return bgmac->clk_enabled(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static inline void bgmac_clk_enable(struct bgmac *bgmac, u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) bgmac->clk_enable(bgmac, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static inline void bgmac_cco_ctl_maskset(struct bgmac *bgmac, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) bgmac->cco_ctl_maskset(bgmac, offset, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) static inline u32 bgmac_get_bus_clock(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) return bgmac->get_bus_clock(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static inline void bgmac_cmn_maskset32(struct bgmac *bgmac, u16 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bgmac->cmn_maskset32(bgmac, offset, mask, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static inline void bgmac_maskset(struct bgmac *bgmac, u16 offset, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) bgmac_write(bgmac, offset, (bgmac_read(bgmac, offset) & mask) | set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static inline void bgmac_mask(struct bgmac *bgmac, u16 offset, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) bgmac_maskset(bgmac, offset, mask, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static inline void bgmac_set(struct bgmac *bgmac, u16 offset, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) bgmac_maskset(bgmac, offset, ~0, set);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static inline int bgmac_phy_connect(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return bgmac->phy_connect(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #endif /* _BGMAC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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