^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for (BCM4706)? GBit MAC core on BCMA bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/bcm47xx_nvram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/phy_fixed.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include "bgmac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) static bool bgmac_wait_value(struct bgmac *bgmac, u16 reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u32 value, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) for (i = 0; i < timeout / 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) val = bgmac_read(bgmac, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if ((val & mask) == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) dev_err(bgmac->dev, "Timeout waiting for reg 0x%X\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static void bgmac_dma_tx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (!ring->mmio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Suspend DMA TX ring first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * bgmac_wait_value doesn't support waiting for any of few values, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * implement whole loop here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) BGMAC_DMA_TX_SUSPEND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) for (i = 0; i < 10000 / 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val &= BGMAC_DMA_TX_STAT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (val == BGMAC_DMA_TX_STAT_DISABLED ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) val == BGMAC_DMA_TX_STAT_IDLEWAIT ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) val == BGMAC_DMA_TX_STAT_STOPPED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) dev_err(bgmac->dev, "Timeout suspending DMA TX ring 0x%X (BGMAC_DMA_TX_STAT: 0x%08X)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ring->mmio_base, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Remove SUSPEND bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (!bgmac_wait_value(bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ring->mmio_base + BGMAC_DMA_TX_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) BGMAC_DMA_TX_STAT, BGMAC_DMA_TX_STAT_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 10000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_warn(bgmac->dev, "DMA TX ring 0x%X wasn't disabled on time, waiting additional 300us\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ring->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) udelay(300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) val = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) if ((val & BGMAC_DMA_TX_STAT) != BGMAC_DMA_TX_STAT_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) dev_err(bgmac->dev, "Reset of DMA TX ring 0x%X failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ring->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static void bgmac_dma_tx_enable(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) if (bgmac->feature_flags & BGMAC_FEAT_TX_MASK_SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ctl &= ~BGMAC_DMA_TX_BL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) ctl |= BGMAC_DMA_TX_BL_128 << BGMAC_DMA_TX_BL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ctl &= ~BGMAC_DMA_TX_MR_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ctl |= BGMAC_DMA_TX_MR_2 << BGMAC_DMA_TX_MR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ctl &= ~BGMAC_DMA_TX_PC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) ctl |= BGMAC_DMA_TX_PC_16 << BGMAC_DMA_TX_PC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ctl &= ~BGMAC_DMA_TX_PT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ctl |= BGMAC_DMA_TX_PT_8 << BGMAC_DMA_TX_PT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ctl |= BGMAC_DMA_TX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) ctl |= BGMAC_DMA_TX_PARITY_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bgmac_dma_tx_add_buf(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int i, int len, u32 ctl0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct bgmac_slot_info *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct bgmac_dma_desc *dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (i == BGMAC_TX_RING_SLOTS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ctl0 |= BGMAC_DESC_CTL0_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ctl1 = len & BGMAC_DESC_CTL1_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) slot = &ring->slots[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dma_desc = &ring->cpu_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dma_desc->addr_low = cpu_to_le32(lower_32_bits(slot->dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) dma_desc->addr_high = cpu_to_le32(upper_32_bits(slot->dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dma_desc->ctl0 = cpu_to_le32(ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dma_desc->ctl1 = cpu_to_le32(ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static netdev_tx_t bgmac_dma_tx_add(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct bgmac_dma_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct sk_buff *skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct net_device *net_dev = bgmac->net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) int index = ring->end % BGMAC_TX_RING_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct bgmac_slot_info *slot = &ring->slots[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) if (skb->len > BGMAC_DESC_CTL1_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) netdev_err(bgmac->net_dev, "Too long skb (%d)\n", skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) goto err_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if (skb->ip_summed == CHECKSUM_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) skb_checksum_help(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) nr_frags = skb_shinfo(skb)->nr_frags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* ring->end - ring->start will return the number of valid slots,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * even when ring->end overflows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (ring->end - ring->start + nr_frags + 1 >= BGMAC_TX_RING_SLOTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) netdev_err(bgmac->net_dev, "TX ring is full, queue should be stopped!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) netif_stop_queue(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) slot->dma_addr = dma_map_single(dma_dev, skb->data, skb_headlen(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) goto err_dma_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) flags = BGMAC_DESC_CTL0_SOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (!nr_frags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) bgmac_dma_tx_add_buf(bgmac, ring, index, skb_headlen(skb), flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) for (i = 0; i < nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) int len = skb_frag_size(frag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) index = (index + 1) % BGMAC_TX_RING_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) slot = &ring->slots[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) slot->dma_addr = skb_frag_dma_map(dma_dev, frag, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) if (unlikely(dma_mapping_error(dma_dev, slot->dma_addr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) goto err_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (i == nr_frags - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) flags |= BGMAC_DESC_CTL0_EOF | BGMAC_DESC_CTL0_IOC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) bgmac_dma_tx_add_buf(bgmac, ring, index, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) slot->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ring->end += nr_frags + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) netdev_sent_queue(net_dev, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Increase ring->end to point empty slot. We tell hardware the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * slot it should *not* read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ring->index_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) (ring->end % BGMAC_TX_RING_SLOTS) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) sizeof(struct bgmac_dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) if (ring->end - ring->start >= BGMAC_TX_RING_SLOTS - 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) netif_stop_queue(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) err_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) dma_unmap_single(dma_dev, slot->dma_addr, skb_headlen(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) while (i-- > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) int index = (ring->end + i) % BGMAC_TX_RING_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct bgmac_slot_info *slot = &ring->slots[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 ctl1 = le32_to_cpu(ring->cpu_base[index].ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int len = ctl1 & BGMAC_DESC_CTL1_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dma_unmap_page(dma_dev, slot->dma_addr, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) err_dma_head:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) netdev_err(bgmac->net_dev, "Mapping error of skb on ring 0x%X\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ring->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) err_drop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) net_dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) net_dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* Free transmitted packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static void bgmac_dma_tx_free(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int empty_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) unsigned bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* The last slot that hardware didn't consume yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) empty_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) empty_slot &= BGMAC_DMA_TX_STATDPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) empty_slot -= ring->index_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) empty_slot &= BGMAC_DMA_TX_STATDPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) empty_slot /= sizeof(struct bgmac_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) while (ring->start != ring->end) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) int slot_idx = ring->start % BGMAC_TX_RING_SLOTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct bgmac_slot_info *slot = &ring->slots[slot_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 ctl0, ctl1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (slot_idx == empty_slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) ctl0 = le32_to_cpu(ring->cpu_base[slot_idx].ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) ctl1 = le32_to_cpu(ring->cpu_base[slot_idx].ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) len = ctl1 & BGMAC_DESC_CTL1_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (ctl0 & BGMAC_DESC_CTL0_SOF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* Unmap no longer used buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dma_unmap_single(dma_dev, slot->dma_addr, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) dma_unmap_page(dma_dev, slot->dma_addr, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (slot->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) bgmac->net_dev->stats.tx_bytes += slot->skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) bgmac->net_dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) bytes_compl += slot->skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* Free memory! :) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev_kfree_skb(slot->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) slot->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) slot->dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ring->start++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (!pkts_compl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) netdev_completed_queue(bgmac->net_dev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (netif_queue_stopped(bgmac->net_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) netif_wake_queue(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static void bgmac_dma_rx_reset(struct bgmac *bgmac, struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (!ring->mmio_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!bgmac_wait_value(bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ring->mmio_base + BGMAC_DMA_RX_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) BGMAC_DMA_RX_STAT, BGMAC_DMA_RX_STAT_DISABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 10000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(bgmac->dev, "Reset of ring 0x%X RX failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) ring->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) static void bgmac_dma_rx_enable(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* preserve ONLY bits 16-17 from current hardware value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (bgmac->feature_flags & BGMAC_FEAT_RX_MASK_SETUP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) ctl &= ~BGMAC_DMA_RX_BL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ctl &= ~BGMAC_DMA_RX_PC_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ctl |= BGMAC_DMA_RX_PC_8 << BGMAC_DMA_RX_PC_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ctl &= ~BGMAC_DMA_RX_PT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) ctl |= BGMAC_DMA_RX_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ctl |= BGMAC_RX_FRAME_OFFSET << BGMAC_DMA_RX_FRAME_OFFSET_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL, ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int bgmac_dma_rx_skb_for_slot(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct bgmac_slot_info *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct bgmac_rx_header *rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* Alloc skb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) buf = netdev_alloc_frag(BGMAC_RX_ALLOC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (!buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Poison - if everything goes fine, hardware will overwrite it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) rx = buf + BGMAC_RX_BUF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) rx->len = cpu_to_le16(0xdead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rx->flags = cpu_to_le16(0xbeef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* Map skb for the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dma_addr = dma_map_single(dma_dev, buf + BGMAC_RX_BUF_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (dma_mapping_error(dma_dev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) netdev_err(bgmac->net_dev, "DMA mapping error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) put_page(virt_to_head_page(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* Update the slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) slot->buf = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) slot->dma_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static void bgmac_dma_rx_update_index(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) dma_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_INDEX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ring->index_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ring->end * sizeof(struct bgmac_dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void bgmac_dma_rx_setup_desc(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct bgmac_dma_ring *ring, int desc_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct bgmac_dma_desc *dma_desc = ring->cpu_base + desc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u32 ctl0 = 0, ctl1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (desc_idx == BGMAC_RX_RING_SLOTS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ctl0 |= BGMAC_DESC_CTL0_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ctl1 |= BGMAC_RX_BUF_SIZE & BGMAC_DESC_CTL1_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /* Is there any BGMAC device that requires extension? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* ctl1 |= (addrext << B43_DMA64_DCTL1_ADDREXT_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * B43_DMA64_DCTL1_ADDREXT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dma_desc->addr_low = cpu_to_le32(lower_32_bits(ring->slots[desc_idx].dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dma_desc->addr_high = cpu_to_le32(upper_32_bits(ring->slots[desc_idx].dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dma_desc->ctl0 = cpu_to_le32(ctl0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dma_desc->ctl1 = cpu_to_le32(ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) ring->end = desc_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) static void bgmac_dma_rx_poison_buf(struct device *dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct bgmac_slot_info *slot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dma_sync_single_for_cpu(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) rx->len = cpu_to_le16(0xdead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) rx->flags = cpu_to_le16(0xbeef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) dma_sync_single_for_device(dma_dev, slot->dma_addr, BGMAC_RX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) static int bgmac_dma_rx_read(struct bgmac *bgmac, struct bgmac_dma_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) int weight)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 end_slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) end_slot = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) end_slot &= BGMAC_DMA_RX_STATDPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) end_slot -= ring->index_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) end_slot &= BGMAC_DMA_RX_STATDPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) end_slot /= sizeof(struct bgmac_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) while (ring->start != end_slot) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct bgmac_slot_info *slot = &ring->slots[ring->start];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct bgmac_rx_header *rx = slot->buf + BGMAC_RX_BUF_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) void *buf = slot->buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dma_addr_t dma_addr = slot->dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u16 len, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* Prepare new skb as replacement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) if (bgmac_dma_rx_skb_for_slot(bgmac, slot)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) bgmac_dma_rx_poison_buf(dma_dev, slot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Unmap buffer to make it accessible to the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) dma_unmap_single(dma_dev, dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) BGMAC_RX_BUF_SIZE, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Get info from the header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) len = le16_to_cpu(rx->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) flags = le16_to_cpu(rx->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Check for poison and drop or pass the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if (len == 0xdead && flags == 0xbeef) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) netdev_err(bgmac->net_dev, "Found poisoned packet at slot %d, DMA issue!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ring->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) put_page(virt_to_head_page(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) bgmac->net_dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (len > BGMAC_RX_ALLOC_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) netdev_err(bgmac->net_dev, "Found oversized packet at slot %d, DMA issue!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) ring->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) put_page(virt_to_head_page(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) bgmac->net_dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) bgmac->net_dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* Omit CRC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) len -= ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) skb = build_skb(buf, BGMAC_RX_ALLOC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (unlikely(!skb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) netdev_err(bgmac->net_dev, "build_skb failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) put_page(virt_to_head_page(buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) bgmac->net_dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) skb_put(skb, BGMAC_RX_FRAME_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) BGMAC_RX_BUF_OFFSET + len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) skb_pull(skb, BGMAC_RX_FRAME_OFFSET +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) BGMAC_RX_BUF_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) skb->protocol = eth_type_trans(skb, bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bgmac->net_dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) bgmac->net_dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) napi_gro_receive(&bgmac->napi, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) handled++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) } while (0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) bgmac_dma_rx_setup_desc(bgmac, ring, ring->start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (++ring->start >= BGMAC_RX_RING_SLOTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) ring->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (handled >= weight) /* Should never be greater */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) bgmac_dma_rx_update_index(bgmac, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /* Does ring support unaligned addressing? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static bool bgmac_dma_unaligned(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct bgmac_dma_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) enum bgmac_dma_ring_type ring_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) switch (ring_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) case BGMAC_DMA_RING_TX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 0xff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) case BGMAC_DMA_RING_RX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 0xff0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) static void bgmac_dma_tx_ring_free(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct bgmac_dma_desc *dma_desc = ring->cpu_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct bgmac_slot_info *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) for (i = 0; i < BGMAC_TX_RING_SLOTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u32 ctl1 = le32_to_cpu(dma_desc[i].ctl1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) unsigned int len = ctl1 & BGMAC_DESC_CTL1_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) slot = &ring->slots[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_kfree_skb(slot->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!slot->dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (slot->skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dma_unmap_single(dma_dev, slot->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) dma_unmap_page(dma_dev, slot->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static void bgmac_dma_rx_ring_free(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct bgmac_dma_ring *ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) struct bgmac_slot_info *slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < BGMAC_RX_RING_SLOTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) slot = &ring->slots[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (!slot->dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dma_unmap_single(dma_dev, slot->dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) BGMAC_RX_BUF_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) put_page(virt_to_head_page(slot->buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) slot->dma_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static void bgmac_dma_ring_desc_free(struct bgmac *bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct bgmac_dma_ring *ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) int num_slots)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) if (!ring->cpu_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Free ring of descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) size = num_slots * sizeof(struct bgmac_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dma_free_coherent(dma_dev, size, ring->cpu_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) ring->dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) static void bgmac_dma_cleanup(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) bgmac_dma_tx_ring_free(bgmac, &bgmac->tx_ring[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bgmac_dma_rx_ring_free(bgmac, &bgmac->rx_ring[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static void bgmac_dma_free(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) bgmac_dma_ring_desc_free(bgmac, &bgmac->tx_ring[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) BGMAC_TX_RING_SLOTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) bgmac_dma_ring_desc_free(bgmac, &bgmac->rx_ring[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) BGMAC_RX_RING_SLOTS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int bgmac_dma_alloc(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct device *dma_dev = bgmac->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct bgmac_dma_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) static const u16 ring_base[] = { BGMAC_DMA_BASE0, BGMAC_DMA_BASE1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) BGMAC_DMA_BASE2, BGMAC_DMA_BASE3, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int size; /* ring size: different for Tx and Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) BUILD_BUG_ON(BGMAC_MAX_TX_RINGS > ARRAY_SIZE(ring_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) BUILD_BUG_ON(BGMAC_MAX_RX_RINGS > ARRAY_SIZE(ring_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!(bgmac_idm_read(bgmac, BCMA_IOST) & BCMA_IOST_DMA64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) dev_err(bgmac->dev, "Core does not report 64-bit DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return -ENOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ring = &bgmac->tx_ring[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ring->mmio_base = ring_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* Alloc ring of descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) size = BGMAC_TX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ring->cpu_base = dma_alloc_coherent(dma_dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) &ring->dma_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!ring->cpu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dev_err(bgmac->dev, "Allocation of TX ring 0x%X failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) ring->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) goto err_dma_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) BGMAC_DMA_RING_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (ring->unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) ring->index_base = lower_32_bits(ring->dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) ring->index_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /* No need to alloc TX slots yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) ring = &bgmac->rx_ring[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) ring->mmio_base = ring_base[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* Alloc ring of descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) size = BGMAC_RX_RING_SLOTS * sizeof(struct bgmac_dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ring->cpu_base = dma_alloc_coherent(dma_dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) &ring->dma_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) if (!ring->cpu_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dev_err(bgmac->dev, "Allocation of RX ring 0x%X failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) ring->mmio_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) goto err_dma_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ring->unaligned = bgmac_dma_unaligned(bgmac, ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) BGMAC_DMA_RING_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) if (ring->unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ring->index_base = lower_32_bits(ring->dma_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ring->index_base = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) err_dma_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) bgmac_dma_free(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static int bgmac_dma_init(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct bgmac_dma_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) for (i = 0; i < BGMAC_MAX_TX_RINGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ring = &bgmac->tx_ring[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (!ring->unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) bgmac_dma_tx_enable(bgmac, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) lower_32_bits(ring->dma_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_TX_RINGHI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) upper_32_bits(ring->dma_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) if (ring->unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) bgmac_dma_tx_enable(bgmac, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ring->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ring->end = 0; /* Points the slot that should *not* be read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) for (i = 0; i < BGMAC_MAX_RX_RINGS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ring = &bgmac->rx_ring[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!ring->unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) bgmac_dma_rx_enable(bgmac, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGLO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) lower_32_bits(ring->dma_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) bgmac_write(bgmac, ring->mmio_base + BGMAC_DMA_RX_RINGHI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) upper_32_bits(ring->dma_base));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (ring->unaligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) bgmac_dma_rx_enable(bgmac, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) ring->start = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) ring->end = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) for (j = 0; j < BGMAC_RX_RING_SLOTS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) err = bgmac_dma_rx_skb_for_slot(bgmac, &ring->slots[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) bgmac_dma_rx_setup_desc(bgmac, ring, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) bgmac_dma_rx_update_index(bgmac, ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) bgmac_dma_cleanup(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Chip ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* TODO: can we just drop @force? Can we don't reset MAC at all if there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * nothing to change? Try if after stabilizng driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) static void bgmac_cmdcfg_maskset(struct bgmac *bgmac, u32 mask, u32 set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) bool force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) u32 cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) u32 new_val = (cmdcfg & mask) | set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) u32 cmdcfg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) bgmac_set(bgmac, BGMAC_CMDCFG, cmdcfg_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (new_val != cmdcfg || force)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) bgmac_write(bgmac, BGMAC_CMDCFG, new_val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) bgmac_mask(bgmac, BGMAC_CMDCFG, ~cmdcfg_sr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void bgmac_write_mac_address(struct bgmac *bgmac, u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) tmp = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) bgmac_write(bgmac, BGMAC_MACADDR_HIGH, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) tmp = (addr[4] << 8) | addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) bgmac_write(bgmac, BGMAC_MACADDR_LOW, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void bgmac_set_rx_mode(struct net_device *net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (net_dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_PROM, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_PROM, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) #if 0 /* We don't use that regs yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static void bgmac_chip_stats_update(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!(bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) bgmac->mib_tx_regs[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) bgmac_read(bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) BGMAC_TX_GOOD_OCTETS + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bgmac->mib_rx_regs[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) bgmac_read(bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) BGMAC_RX_GOOD_OCTETS + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /* TODO: what else? how to handle BCM4706? Specs are needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static void bgmac_clear_mib(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (bgmac->feature_flags & BGMAC_FEAT_NO_CLR_MIB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) bgmac_set(bgmac, BGMAC_DEV_CTL, BGMAC_DC_MROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) for (i = 0; i < BGMAC_NUM_MIB_TX_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) bgmac_read(bgmac, BGMAC_TX_GOOD_OCTETS + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) for (i = 0; i < BGMAC_NUM_MIB_RX_REGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) bgmac_read(bgmac, BGMAC_RX_GOOD_OCTETS + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_speed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) static void bgmac_mac_speed(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 mask = ~(BGMAC_CMDCFG_ES_MASK | BGMAC_CMDCFG_HD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 set = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) switch (bgmac->mac_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) set |= BGMAC_CMDCFG_ES_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) set |= BGMAC_CMDCFG_ES_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) set |= BGMAC_CMDCFG_ES_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case SPEED_2500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) set |= BGMAC_CMDCFG_ES_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) dev_err(bgmac->dev, "Unsupported speed: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) bgmac->mac_speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) if (bgmac->mac_duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) set |= BGMAC_CMDCFG_HD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) bgmac_cmdcfg_maskset(bgmac, mask, set, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) static void bgmac_miiconfig(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) if (bgmac->feature_flags & BGMAC_FEAT_FORCE_SPEED_2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) bgmac_idm_write(bgmac, BCMA_IOCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) bgmac_idm_read(bgmac, BCMA_IOCTL) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) 0x40 | BGMAC_BCMA_IOCTL_SW_CLKEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) bgmac->mac_speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) bgmac->mac_duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) bgmac_mac_speed(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 imode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) imode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) BGMAC_DS_MM_MASK) >> BGMAC_DS_MM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) if (imode == 0 || imode == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) bgmac->mac_speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) bgmac->mac_duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) bgmac_mac_speed(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static void bgmac_chip_reset_idm_config(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) u32 iost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) iost = bgmac_idm_read(bgmac, BCMA_IOST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (bgmac->feature_flags & BGMAC_FEAT_IOST_ATTACHED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) iost &= ~BGMAC_BCMA_IOST_ATTACHED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) /* 3GMAC: for BCM4707 & BCM47094, only do core reset at bgmac_probe() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!(bgmac->feature_flags & BGMAC_FEAT_NO_RESET)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) u32 flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (iost & BGMAC_BCMA_IOST_ATTACHED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) flags = BGMAC_BCMA_IOCTL_SW_CLKEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (!bgmac->has_robosw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) flags |= BGMAC_BCMA_IOCTL_SW_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) bgmac_clk_enable(bgmac, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (iost & BGMAC_BCMA_IOST_ATTACHED && !bgmac->has_robosw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) bgmac_idm_write(bgmac, BCMA_IOCTL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) bgmac_idm_read(bgmac, BCMA_IOCTL) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ~BGMAC_BCMA_IOCTL_SW_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static void bgmac_chip_reset(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) u32 cmdcfg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (bgmac_clk_enabled(bgmac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (!bgmac->stats_grabbed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* bgmac_chip_stats_update(bgmac); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) bgmac->stats_grabbed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) for (i = 0; i < BGMAC_MAX_TX_RINGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) bgmac_dma_tx_reset(bgmac, &bgmac->tx_ring[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) for (i = 0; i < BGMAC_MAX_RX_RINGS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) bgmac_dma_rx_reset(bgmac, &bgmac->rx_ring[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* TODO: Clear software multicast filter list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) bgmac_chip_reset_idm_config(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* Request Misc PLL for corerev > 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (bgmac->feature_flags & BGMAC_FEAT_MISC_PLL_REQ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) bgmac_set(bgmac, BCMA_CLKCTLST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) BGMAC_BCMA_CLKCTLST_MISC_PLL_REQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) bgmac_wait_value(bgmac, BCMA_CLKCTLST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) BGMAC_BCMA_CLKCTLST_MISC_PLL_ST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) u8 et_swtype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) u8 sw_type = BGMAC_CHIPCTL_1_SW_TYPE_EPHY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) BGMAC_CHIPCTL_1_IF_TYPE_MII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (kstrtou8(buf, 0, &et_swtype))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) et_swtype &= 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) et_swtype <<= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) sw_type = et_swtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_EPHYRMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RMII |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) BGMAC_CHIPCTL_1_SW_TYPE_EPHYRMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) } else if (bgmac->feature_flags & BGMAC_FEAT_SW_TYPE_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) sw_type = BGMAC_CHIPCTL_1_IF_TYPE_RGMII |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) BGMAC_CHIPCTL_1_SW_TYPE_RGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) bgmac_cco_ctl_maskset(bgmac, 1, ~(BGMAC_CHIPCTL_1_IF_TYPE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) BGMAC_CHIPCTL_1_SW_TYPE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) sw_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 sw_type = BGMAC_CHIPCTL_4_IF_TYPE_MII |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) BGMAC_CHIPCTL_4_SW_TYPE_EPHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u8 et_swtype = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) char buf[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (bcm47xx_nvram_getenv("et_swtype", buf, sizeof(buf)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (kstrtou8(buf, 0, &et_swtype))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) dev_err(bgmac->dev, "Failed to parse et_swtype (%s)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) sw_type = (et_swtype & 0x0f) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) } else if (bgmac->feature_flags & BGMAC_FEAT_CC4_IF_SW_TYPE_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) sw_type = BGMAC_CHIPCTL_4_IF_TYPE_RGMII |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) BGMAC_CHIPCTL_4_SW_TYPE_RGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) bgmac_cco_ctl_maskset(bgmac, 4, ~(BGMAC_CHIPCTL_4_IF_TYPE_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) BGMAC_CHIPCTL_4_SW_TYPE_MASK),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) sw_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) } else if (bgmac->feature_flags & BGMAC_FEAT_CC7_IF_TYPE_RGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) bgmac_cco_ctl_maskset(bgmac, 7, ~BGMAC_CHIPCTL_7_IF_TYPE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) BGMAC_CHIPCTL_7_IF_TYPE_RGMII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * Specs don't say about using BGMAC_CMDCFG_SR, but in this routine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * BGMAC_CMDCFG is read _after_ putting chip in a reset. So it has to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * be keps until taking MAC out of the reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) bgmac_cmdcfg_maskset(bgmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) ~(BGMAC_CMDCFG_TE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) BGMAC_CMDCFG_RE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) BGMAC_CMDCFG_RPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) BGMAC_CMDCFG_TAI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) BGMAC_CMDCFG_HD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) BGMAC_CMDCFG_ML |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) BGMAC_CMDCFG_CFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) BGMAC_CMDCFG_RL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) BGMAC_CMDCFG_RED |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) BGMAC_CMDCFG_PE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) BGMAC_CMDCFG_TPI |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) BGMAC_CMDCFG_PAD_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) BGMAC_CMDCFG_PF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) BGMAC_CMDCFG_PROM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) BGMAC_CMDCFG_NLC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) BGMAC_CMDCFG_CFE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) cmdcfg_sr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) bgmac->mac_speed = SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) bgmac->mac_duplex = DUPLEX_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bgmac_clear_mib(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) if (bgmac->feature_flags & BGMAC_FEAT_CMN_PHY_CTL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bgmac_cmn_maskset32(bgmac, BCMA_GMAC_CMN_PHY_CTL, ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) BCMA_GMAC_CMN_PC_MTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) bgmac_set(bgmac, BGMAC_PHY_CNTL, BGMAC_PC_MTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) bgmac_miiconfig(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) if (bgmac->mii_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) bgmac->mii_bus->reset(bgmac->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) netdev_reset_queue(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) static void bgmac_chip_intrs_on(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) bgmac_write(bgmac, BGMAC_INT_MASK, bgmac->int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) static void bgmac_chip_intrs_off(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) bgmac_write(bgmac, BGMAC_INT_MASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) bgmac_read(bgmac, BGMAC_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/gmac_enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) static void bgmac_enable(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u32 cmdcfg_sr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 cmdcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u32 mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) if (bgmac->feature_flags & BGMAC_FEAT_CMDCFG_SR_REV4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) cmdcfg_sr = BGMAC_CMDCFG_SR_REV4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) cmdcfg_sr = BGMAC_CMDCFG_SR_REV0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) cmdcfg = bgmac_read(bgmac, BGMAC_CMDCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) bgmac_cmdcfg_maskset(bgmac, ~(BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) cmdcfg_sr, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) cmdcfg |= BGMAC_CMDCFG_TE | BGMAC_CMDCFG_RE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) bgmac_write(bgmac, BGMAC_CMDCFG, cmdcfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) mode = (bgmac_read(bgmac, BGMAC_DEV_STATUS) & BGMAC_DS_MM_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) BGMAC_DS_MM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (bgmac->feature_flags & BGMAC_FEAT_CLKCTLST || mode != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) bgmac_set(bgmac, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (!(bgmac->feature_flags & BGMAC_FEAT_CLKCTLST) && mode == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) bgmac_cco_ctl_maskset(bgmac, 1, ~0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) BGMAC_CHIPCTL_1_RXC_DLL_BYPASS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (bgmac->feature_flags & (BGMAC_FEAT_FLW_CTRL1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) BGMAC_FEAT_FLW_CTRL2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u32 fl_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (bgmac->feature_flags & BGMAC_FEAT_FLW_CTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) fl_ctl = 0x2300e1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) fl_ctl = 0x03cb04cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) bgmac_write(bgmac, BGMAC_FLOW_CTL_THRESH, fl_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) bgmac_write(bgmac, BGMAC_PAUSE_CTL, 0x27fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (bgmac->feature_flags & BGMAC_FEAT_SET_RXQ_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) u32 rxq_ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) u16 bp_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) u8 mdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) rxq_ctl = bgmac_read(bgmac, BGMAC_RXQ_CTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) rxq_ctl &= ~BGMAC_RXQ_CTL_MDP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) bp_clk = bgmac_get_bus_clock(bgmac) / 1000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) mdp = (bp_clk * 128 / 1000) - 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) rxq_ctl |= (mdp << BGMAC_RXQ_CTL_MDP_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) bgmac_write(bgmac, BGMAC_RXQ_CTL, rxq_ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipinit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) static void bgmac_chip_init(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) /* Clear any erroneously pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) /* 1 interrupt per received frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) bgmac_write(bgmac, BGMAC_INT_RECV_LAZY, 1 << BGMAC_IRL_FC_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) /* Enable 802.3x tx flow control (honor received PAUSE frames) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_RPI, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) bgmac_set_rx_mode(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) bgmac_write_mac_address(bgmac, bgmac->net_dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) if (bgmac->loopback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) bgmac_cmdcfg_maskset(bgmac, ~0, BGMAC_CMDCFG_ML, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) bgmac_cmdcfg_maskset(bgmac, ~BGMAC_CMDCFG_ML, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + ETHER_MAX_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) bgmac_chip_intrs_on(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) bgmac_enable(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) static irqreturn_t bgmac_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct bgmac *bgmac = netdev_priv(dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) u32 int_status = bgmac_read(bgmac, BGMAC_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) int_status &= bgmac->int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (!int_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) int_status &= ~(BGMAC_IS_TX0 | BGMAC_IS_RX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (int_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_err(bgmac->dev, "Unknown IRQs: 0x%08X\n", int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) /* Disable new interrupts until handling existing ones */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) bgmac_chip_intrs_off(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) napi_schedule(&bgmac->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static int bgmac_poll(struct napi_struct *napi, int weight)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct bgmac *bgmac = container_of(napi, struct bgmac, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) /* Ack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) bgmac_write(bgmac, BGMAC_INT_STATUS, ~0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) bgmac_dma_tx_free(bgmac, &bgmac->tx_ring[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) handled += bgmac_dma_rx_read(bgmac, &bgmac->rx_ring[0], weight);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) /* Poll again if more events arrived in the meantime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (bgmac_read(bgmac, BGMAC_INT_STATUS) & (BGMAC_IS_TX0 | BGMAC_IS_RX))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) return weight;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (handled < weight) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) napi_complete_done(napi, handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) bgmac_chip_intrs_on(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) return handled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) * net_device_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) static int bgmac_open(struct net_device *net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) bgmac_chip_reset(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) err = bgmac_dma_init(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Specs say about reclaiming rings here, but we do that in DMA init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) bgmac_chip_init(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err = request_irq(bgmac->irq, bgmac_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) net_dev->name, net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) dev_err(bgmac->dev, "IRQ request error: %d!\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) bgmac_dma_cleanup(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) napi_enable(&bgmac->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) phy_start(net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) netif_start_queue(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static int bgmac_stop(struct net_device *net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) netif_carrier_off(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) phy_stop(net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) napi_disable(&bgmac->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) bgmac_chip_intrs_off(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) free_irq(bgmac->irq, net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) bgmac_chip_reset(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) bgmac_dma_cleanup(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) static netdev_tx_t bgmac_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct net_device *net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct bgmac_dma_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* No QOS support yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) ring = &bgmac->tx_ring[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) return bgmac_dma_tx_add(bgmac, ring, skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) static int bgmac_set_mac_address(struct net_device *net_dev, void *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct sockaddr *sa = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) ret = eth_prepare_mac_addr_change(net_dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) ether_addr_copy(net_dev->dev_addr, sa->sa_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) bgmac_write_mac_address(bgmac, net_dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) eth_commit_mac_addr_change(net_dev, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) static int bgmac_change_mtu(struct net_device *net_dev, int mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) bgmac_write(bgmac, BGMAC_RXMAX_LENGTH, 32 + mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static const struct net_device_ops bgmac_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) .ndo_open = bgmac_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .ndo_stop = bgmac_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .ndo_start_xmit = bgmac_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .ndo_set_rx_mode = bgmac_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .ndo_set_mac_address = bgmac_set_mac_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .ndo_do_ioctl = phy_do_ioctl_running,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) .ndo_change_mtu = bgmac_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) * ethtool_ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) struct bgmac_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) u8 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) static struct bgmac_stat bgmac_get_strings_stats[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) { 8, BGMAC_TX_GOOD_OCTETS, "tx_good_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) { 4, BGMAC_TX_GOOD_PKTS, "tx_good" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) { 8, BGMAC_TX_OCTETS, "tx_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) { 4, BGMAC_TX_PKTS, "tx_pkts" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) { 4, BGMAC_TX_BROADCAST_PKTS, "tx_broadcast" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) { 4, BGMAC_TX_MULTICAST_PKTS, "tx_multicast" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) { 4, BGMAC_TX_LEN_64, "tx_64" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) { 4, BGMAC_TX_LEN_65_TO_127, "tx_65_127" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) { 4, BGMAC_TX_LEN_128_TO_255, "tx_128_255" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) { 4, BGMAC_TX_LEN_256_TO_511, "tx_256_511" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) { 4, BGMAC_TX_LEN_512_TO_1023, "tx_512_1023" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) { 4, BGMAC_TX_LEN_1024_TO_1522, "tx_1024_1522" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) { 4, BGMAC_TX_LEN_1523_TO_2047, "tx_1523_2047" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) { 4, BGMAC_TX_LEN_2048_TO_4095, "tx_2048_4095" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) { 4, BGMAC_TX_LEN_4096_TO_8191, "tx_4096_8191" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) { 4, BGMAC_TX_LEN_8192_TO_MAX, "tx_8192_max" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) { 4, BGMAC_TX_JABBER_PKTS, "tx_jabber" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) { 4, BGMAC_TX_OVERSIZE_PKTS, "tx_oversize" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) { 4, BGMAC_TX_FRAGMENT_PKTS, "tx_fragment" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) { 4, BGMAC_TX_UNDERRUNS, "tx_underruns" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) { 4, BGMAC_TX_TOTAL_COLS, "tx_total_cols" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) { 4, BGMAC_TX_SINGLE_COLS, "tx_single_cols" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) { 4, BGMAC_TX_MULTIPLE_COLS, "tx_multiple_cols" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) { 4, BGMAC_TX_EXCESSIVE_COLS, "tx_excessive_cols" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) { 4, BGMAC_TX_LATE_COLS, "tx_late_cols" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) { 4, BGMAC_TX_DEFERED, "tx_defered" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) { 4, BGMAC_TX_CARRIER_LOST, "tx_carrier_lost" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) { 4, BGMAC_TX_PAUSE_PKTS, "tx_pause" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) { 4, BGMAC_TX_UNI_PKTS, "tx_unicast" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) { 4, BGMAC_TX_Q0_PKTS, "tx_q0" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) { 8, BGMAC_TX_Q0_OCTETS, "tx_q0_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) { 4, BGMAC_TX_Q1_PKTS, "tx_q1" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) { 8, BGMAC_TX_Q1_OCTETS, "tx_q1_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) { 4, BGMAC_TX_Q2_PKTS, "tx_q2" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) { 8, BGMAC_TX_Q2_OCTETS, "tx_q2_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) { 4, BGMAC_TX_Q3_PKTS, "tx_q3" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) { 8, BGMAC_TX_Q3_OCTETS, "tx_q3_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) { 8, BGMAC_RX_GOOD_OCTETS, "rx_good_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { 4, BGMAC_RX_GOOD_PKTS, "rx_good" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { 8, BGMAC_RX_OCTETS, "rx_octets" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) { 4, BGMAC_RX_PKTS, "rx_pkts" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) { 4, BGMAC_RX_BROADCAST_PKTS, "rx_broadcast" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) { 4, BGMAC_RX_MULTICAST_PKTS, "rx_multicast" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) { 4, BGMAC_RX_LEN_64, "rx_64" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) { 4, BGMAC_RX_LEN_65_TO_127, "rx_65_127" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) { 4, BGMAC_RX_LEN_128_TO_255, "rx_128_255" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) { 4, BGMAC_RX_LEN_256_TO_511, "rx_256_511" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) { 4, BGMAC_RX_LEN_512_TO_1023, "rx_512_1023" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) { 4, BGMAC_RX_LEN_1024_TO_1522, "rx_1024_1522" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) { 4, BGMAC_RX_LEN_1523_TO_2047, "rx_1523_2047" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) { 4, BGMAC_RX_LEN_2048_TO_4095, "rx_2048_4095" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) { 4, BGMAC_RX_LEN_4096_TO_8191, "rx_4096_8191" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) { 4, BGMAC_RX_LEN_8192_TO_MAX, "rx_8192_max" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) { 4, BGMAC_RX_JABBER_PKTS, "rx_jabber" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) { 4, BGMAC_RX_OVERSIZE_PKTS, "rx_oversize" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) { 4, BGMAC_RX_FRAGMENT_PKTS, "rx_fragment" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) { 4, BGMAC_RX_MISSED_PKTS, "rx_missed" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) { 4, BGMAC_RX_CRC_ALIGN_ERRS, "rx_crc_align" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) { 4, BGMAC_RX_UNDERSIZE, "rx_undersize" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) { 4, BGMAC_RX_CRC_ERRS, "rx_crc" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) { 4, BGMAC_RX_ALIGN_ERRS, "rx_align" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) { 4, BGMAC_RX_SYMBOL_ERRS, "rx_symbol" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) { 4, BGMAC_RX_PAUSE_PKTS, "rx_pause" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) { 4, BGMAC_RX_NONPAUSE_PKTS, "rx_nonpause" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) { 4, BGMAC_RX_SACHANGES, "rx_sa_changes" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) { 4, BGMAC_RX_UNI_PKTS, "rx_unicast" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) #define BGMAC_STATS_LEN ARRAY_SIZE(bgmac_get_strings_stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) static int bgmac_get_sset_count(struct net_device *dev, int string_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) switch (string_set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return BGMAC_STATS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) static void bgmac_get_strings(struct net_device *dev, u32 stringset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (stringset != ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) for (i = 0; i < BGMAC_STATS_LEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) strlcpy(data + i * ETH_GSTRING_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) bgmac_get_strings_stats[i].name, ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static void bgmac_get_ethtool_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) struct ethtool_stats *ss, uint64_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct bgmac *bgmac = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) const struct bgmac_stat *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) u64 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) for (i = 0; i < BGMAC_STATS_LEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) s = &bgmac_get_strings_stats[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (s->size == 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) val = (u64)bgmac_read(bgmac, s->offset + 4) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) val |= bgmac_read(bgmac, s->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) data[i] = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void bgmac_get_drvinfo(struct net_device *net_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) strlcpy(info->driver, KBUILD_MODNAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) strlcpy(info->bus_info, "AXI", sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static const struct ethtool_ops bgmac_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) .get_strings = bgmac_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) .get_sset_count = bgmac_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) .get_ethtool_stats = bgmac_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) .get_drvinfo = bgmac_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) .get_link_ksettings = phy_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) .set_link_ksettings = phy_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) * MII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) void bgmac_adjust_link(struct net_device *net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct bgmac *bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) struct phy_device *phy_dev = net_dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) bool update = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) if (phy_dev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) if (phy_dev->speed != bgmac->mac_speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) bgmac->mac_speed = phy_dev->speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) if (phy_dev->duplex != bgmac->mac_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) bgmac->mac_duplex = phy_dev->duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) update = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) if (update) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) bgmac_mac_speed(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) phy_print_status(phy_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) EXPORT_SYMBOL_GPL(bgmac_adjust_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int bgmac_phy_connect_direct(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct fixed_phy_status fphy_status = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .link = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .speed = SPEED_1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .duplex = DUPLEX_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) struct phy_device *phy_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) phy_dev = fixed_phy_register(PHY_POLL, &fphy_status, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) if (!phy_dev || IS_ERR(phy_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev_err(bgmac->dev, "Failed to register fixed PHY device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) err = phy_connect_direct(bgmac->net_dev, phy_dev, bgmac_adjust_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) PHY_INTERFACE_MODE_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_err(bgmac->dev, "Connecting PHY failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) EXPORT_SYMBOL_GPL(bgmac_phy_connect_direct);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct bgmac *bgmac_alloc(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct net_device *net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) struct bgmac *bgmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* Allocation and references */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) net_dev = devm_alloc_etherdev(dev, sizeof(*bgmac));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (!net_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) net_dev->netdev_ops = &bgmac_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) net_dev->ethtool_ops = &bgmac_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) bgmac = netdev_priv(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) bgmac->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) bgmac->net_dev = net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) return bgmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) EXPORT_SYMBOL_GPL(bgmac_alloc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) int bgmac_enet_probe(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) struct net_device *net_dev = bgmac->net_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) bgmac_chip_intrs_off(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) net_dev->irq = bgmac->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) SET_NETDEV_DEV(net_dev, bgmac->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dev_set_drvdata(bgmac->dev, bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) if (!is_valid_ether_addr(net_dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) dev_err(bgmac->dev, "Invalid MAC addr: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) net_dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) eth_hw_addr_random(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev_warn(bgmac->dev, "Using random MAC: %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) net_dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) /* This (reset &) enable is not preset in specs or reference driver but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) * Broadcom does it in arch PCI code when enabling fake PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) bgmac_clk_enable(bgmac, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) /* This seems to be fixing IRQ by assigning OOB #6 to the core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (!(bgmac->feature_flags & BGMAC_FEAT_IDM_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (bgmac->feature_flags & BGMAC_FEAT_IRQ_ID_OOB_6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) bgmac_idm_write(bgmac, BCMA_OOB_SEL_OUT_A30, 0x86);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) bgmac_chip_reset(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) err = bgmac_dma_alloc(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) dev_err(bgmac->dev, "Unable to alloc memory for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) bgmac->int_mask = BGMAC_IS_ERRMASK | BGMAC_IS_RX | BGMAC_IS_TX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (bcm47xx_nvram_getenv("et0_no_txint", NULL, 0) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) bgmac->int_mask &= ~BGMAC_IS_TX_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) netif_napi_add(net_dev, &bgmac->napi, bgmac_poll, BGMAC_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) err = bgmac_phy_connect(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) dev_err(bgmac->dev, "Cannot connect to phy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) goto err_dma_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) net_dev->features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_IPV6_CSUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) net_dev->hw_features = net_dev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) net_dev->vlan_features = net_dev->features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) /* Omit FCS from max MTU size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) net_dev->max_mtu = BGMAC_RX_MAX_FRAME_SIZE - ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) err = register_netdev(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) dev_err(bgmac->dev, "Cannot register net device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) goto err_phy_disconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) netif_carrier_off(net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) err_phy_disconnect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) phy_disconnect(net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) err_dma_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) bgmac_dma_free(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) EXPORT_SYMBOL_GPL(bgmac_enet_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) void bgmac_enet_remove(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) unregister_netdev(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) phy_disconnect(bgmac->net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) netif_napi_del(&bgmac->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) bgmac_dma_free(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) free_netdev(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) EXPORT_SYMBOL_GPL(bgmac_enet_remove);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) int bgmac_enet_suspend(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (!netif_running(bgmac->net_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) phy_stop(bgmac->net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) netif_stop_queue(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) napi_disable(&bgmac->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) netif_tx_lock(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) netif_device_detach(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) netif_tx_unlock(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) bgmac_chip_intrs_off(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) bgmac_chip_reset(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) bgmac_dma_cleanup(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) EXPORT_SYMBOL_GPL(bgmac_enet_suspend);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) int bgmac_enet_resume(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (!netif_running(bgmac->net_dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) rc = bgmac_dma_init(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) bgmac_chip_init(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) napi_enable(&bgmac->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) netif_tx_lock(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) netif_device_attach(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) netif_tx_unlock(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) netif_start_queue(bgmac->net_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) phy_start(bgmac->net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) EXPORT_SYMBOL_GPL(bgmac_enet_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) MODULE_AUTHOR("Rafał Miłecki");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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