^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Driver for (BCM4706)? GBit MAC core on BCMA bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2012 Rafał Miłecki <zajec5@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Licensed under the GNU/GPL. See COPYING for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/bcma/bcma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "bgmac.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) static bool bcma_mdio_wait_value(struct bcma_device *core, u16 reg, u32 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 value, int timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) for (i = 0; i < timeout / 10; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) val = bcma_read32(core, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) if ((val & mask) == value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) dev_err(&core->dev, "Timeout waiting for reg 0x%X\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * PHY ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static u16 bcma_mdio_phy_read(struct bgmac *bgmac, u8 phyaddr, u8 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u16 phy_access_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u16 phy_ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) BUILD_BUG_ON(BGMAC_PA_DATA_MASK != BCMA_GMAC_CMN_PA_DATA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) BUILD_BUG_ON(BGMAC_PA_ADDR_MASK != BCMA_GMAC_CMN_PA_ADDR_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) BUILD_BUG_ON(BGMAC_PA_ADDR_SHIFT != BCMA_GMAC_CMN_PA_ADDR_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) BUILD_BUG_ON(BGMAC_PA_REG_MASK != BCMA_GMAC_CMN_PA_REG_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) BUILD_BUG_ON(BGMAC_PA_REG_SHIFT != BCMA_GMAC_CMN_PA_REG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) BUILD_BUG_ON(BGMAC_PA_WRITE != BCMA_GMAC_CMN_PA_WRITE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) BUILD_BUG_ON(BGMAC_PA_START != BCMA_GMAC_CMN_PA_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) BUILD_BUG_ON(BGMAC_PC_EPA_MASK != BCMA_GMAC_CMN_PC_EPA_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) BUILD_BUG_ON(BGMAC_PC_MCT_MASK != BCMA_GMAC_CMN_PC_MCT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) BUILD_BUG_ON(BGMAC_PC_MCT_SHIFT != BCMA_GMAC_CMN_PC_MCT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) BUILD_BUG_ON(BGMAC_PC_MTE != BCMA_GMAC_CMN_PC_MTE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) core = bgmac->bcma.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) phy_access_addr = BGMAC_PHY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) phy_ctl_addr = BGMAC_PHY_CNTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) tmp = bcma_read32(core, phy_ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) tmp &= ~BGMAC_PC_EPA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) tmp |= phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) bcma_write32(core, phy_ctl_addr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) tmp = BGMAC_PA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) tmp |= reg << BGMAC_PA_REG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) bcma_write32(core, phy_access_addr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) dev_err(&core->dev, "Reading PHY %d register 0x%X failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) phyaddr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) return bcma_read32(core, phy_access_addr) & BGMAC_PA_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphywr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static int bcma_mdio_phy_write(struct bgmac *bgmac, u8 phyaddr, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct bcma_device *core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u16 phy_access_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u16 phy_ctl_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (bgmac->bcma.core->id.id == BCMA_CORE_4706_MAC_GBIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) core = bgmac->bcma.core->bus->drv_gmac_cmn.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) phy_access_addr = BCMA_GMAC_CMN_PHY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) phy_ctl_addr = BCMA_GMAC_CMN_PHY_CTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) core = bgmac->bcma.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) phy_access_addr = BGMAC_PHY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) phy_ctl_addr = BGMAC_PHY_CNTL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tmp = bcma_read32(core, phy_ctl_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) tmp &= ~BGMAC_PC_EPA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) tmp |= phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) bcma_write32(core, phy_ctl_addr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) bcma_write32(bgmac->bcma.core, BGMAC_INT_STATUS, BGMAC_IS_MDIO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) if (bcma_read32(bgmac->bcma.core, BGMAC_INT_STATUS) & BGMAC_IS_MDIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) dev_warn(&core->dev, "Error setting MDIO int\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) tmp = BGMAC_PA_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tmp |= BGMAC_PA_WRITE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tmp |= phyaddr << BGMAC_PA_ADDR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) tmp |= reg << BGMAC_PA_REG_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) tmp |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bcma_write32(core, phy_access_addr, tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!bcma_mdio_wait_value(core, phy_access_addr, BGMAC_PA_START, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 1000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) dev_err(&core->dev, "Writing to PHY %d register 0x%X failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) phyaddr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyinit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void bcma_mdio_phy_init(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct bcma_chipinfo *ci = &bgmac->bcma.core->bus->chipinfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u8 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* For some legacy hardware we do chipset-based PHY initialization here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * without even detecting PHY ID. It's hacky and should be cleaned as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * soon as someone can test it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) if (ci->id == BCMA_CHIP_ID_BCM5356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x008b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bcma_mdio_phy_write(bgmac, i, 0x15, 0x0100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) bcma_mdio_phy_write(bgmac, i, 0x12, 0x2aaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if ((ci->id == BCMA_CHIP_ID_BCM5357 && ci->pkg != 10) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) (ci->id == BCMA_CHIP_ID_BCM4749 && ci->pkg != 10) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) (ci->id == BCMA_CHIP_ID_BCM53572 && ci->pkg != 9)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct bcma_drv_cc *cc = &bgmac->bcma.core->bus->drv_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) bcma_chipco_chipctl_maskset(cc, 2, ~0xc0000000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bcma_chipco_chipctl_maskset(cc, 4, ~0x80000000, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) for (i = 0; i < 5; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) bcma_mdio_phy_write(bgmac, i, 0x16, 0x5284);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) bcma_mdio_phy_write(bgmac, i, 0x17, 0x0010);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000f);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bcma_mdio_phy_write(bgmac, i, 0x16, 0x5296);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) bcma_mdio_phy_write(bgmac, i, 0x17, 0x1073);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bcma_mdio_phy_write(bgmac, i, 0x17, 0x9073);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) bcma_mdio_phy_write(bgmac, i, 0x16, 0x52b6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) bcma_mdio_phy_write(bgmac, i, 0x17, 0x9273);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bcma_mdio_phy_write(bgmac, i, 0x1f, 0x000b);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* For all other hw do initialization using PHY subsystem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (bgmac->net_dev && bgmac->net_dev->phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) phy_init_hw(bgmac->net_dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* http://bcm-v4.sipsolutions.net/mac-gbit/gmac/chipphyreset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static int bcma_mdio_phy_reset(struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct bgmac *bgmac = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u8 phyaddr = bgmac->phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (phyaddr == BGMAC_PHY_NOREGS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) bcma_mdio_phy_write(bgmac, phyaddr, MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (bcma_mdio_phy_read(bgmac, phyaddr, MII_BMCR) & BMCR_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) dev_err(bgmac->dev, "PHY reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) bcma_mdio_phy_init(bgmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /**************************************************
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * MII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) **************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static int bcma_mdio_mii_read(struct mii_bus *bus, int mii_id, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return bcma_mdio_phy_read(bus->priv, mii_id, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static int bcma_mdio_mii_write(struct mii_bus *bus, int mii_id, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) return bcma_mdio_phy_write(bus->priv, mii_id, regnum, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct mii_bus *bcma_mdio_mii_register(struct bgmac *bgmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct bcma_device *core = bgmac->bcma.core;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (!mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) mii_bus->name = "bcma_mdio mii bus";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) sprintf(mii_bus->id, "%s-%d-%d", "bcma_mdio", core->bus->num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) core->core_unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) mii_bus->priv = bgmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mii_bus->read = bcma_mdio_mii_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) mii_bus->write = bcma_mdio_mii_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) mii_bus->reset = bcma_mdio_phy_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) mii_bus->parent = &core->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mii_bus->phy_mask = ~(1 << bgmac->phyaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = mdiobus_register(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dev_err(&core->dev, "Registration of mii bus failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) goto err_free_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) err_free_bus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mdiobus_free(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) EXPORT_SYMBOL_GPL(bcma_mdio_mii_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) void bcma_mdio_mii_unregister(struct mii_bus *mii_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (!mii_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mdiobus_unregister(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mdiobus_free(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) EXPORT_SYMBOL_GPL(bcma_mdio_mii_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MODULE_AUTHOR("Rafał Miłecki");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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