^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _B44_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _B44_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/brcmphy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Register layout. (These correspond to struct _bcmenettregs in bcm4400.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define B44_DEVCTRL 0x0000UL /* Device Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define DEVCTRL_MPM 0x00000040 /* Magic Packet PME Enable (B0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DEVCTRL_PFE 0x00000080 /* Pattern Filtering Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DEVCTRL_IPP 0x00000400 /* Internal EPHY Present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DEVCTRL_EPR 0x00008000 /* EPHY Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DEVCTRL_PME 0x00001000 /* PHY Mode Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DEVCTRL_PMCE 0x00002000 /* PHY Mode Clocks Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DEVCTRL_PADDR 0x0007c000 /* PHY Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DEVCTRL_PADDR_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define B44_BIST_STAT 0x000CUL /* Built-In Self-Test Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define B44_WKUP_LEN 0x0010UL /* Wakeup Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define WKUP_LEN_P0_MASK 0x0000007f /* Pattern 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define WKUP_LEN_D0 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define WKUP_LEN_P1_MASK 0x00007f00 /* Pattern 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define WKUP_LEN_P1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define WKUP_LEN_D1 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define WKUP_LEN_P2_MASK 0x007f0000 /* Pattern 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define WKUP_LEN_P2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define WKUP_LEN_D2 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define WKUP_LEN_P3_MASK 0x7f000000 /* Pattern 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WKUP_LEN_P3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define WKUP_LEN_D3 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define WKUP_LEN_DISABLE 0x80808080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define WKUP_LEN_ENABLE_TWO 0x80800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define WKUP_LEN_ENABLE_THREE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define B44_ISTAT 0x0020UL /* Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ISTAT_LS 0x00000020 /* Link Change (B0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ISTAT_PME 0x00000040 /* Power Management Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ISTAT_TO 0x00000080 /* General Purpose Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ISTAT_DSCE 0x00000400 /* Descriptor Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ISTAT_DATAE 0x00000800 /* Data Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ISTAT_RX 0x00010000 /* RX Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ISTAT_TX 0x01000000 /* TX Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ISTAT_ERRORS (ISTAT_DSCE|ISTAT_DATAE|ISTAT_DPE|ISTAT_RDU|ISTAT_RFO|ISTAT_TFU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define B44_IMASK 0x0024UL /* Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMASK_DEF (ISTAT_ERRORS | ISTAT_TO | ISTAT_RX | ISTAT_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define B44_GPTIMER 0x0028UL /* General Purpose Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define B44_ADDR_LO 0x0088UL /* ENET Address Lo (B0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define B44_ADDR_HI 0x008CUL /* ENET Address Hi (B0 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define B44_FILT_ADDR 0x0090UL /* ENET Filter Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define B44_FILT_DATA 0x0094UL /* ENET Filter Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define B44_TXBURST 0x00A0UL /* TX Max Burst Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define B44_RXBURST 0x00A4UL /* RX Max Burst Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define B44_MAC_CTRL 0x00A8UL /* MAC Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MAC_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MAC_CTRL_PHY_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MAC_CTRL_PHY_EDET 0x00000008 /* Onchip EPHY Energy Detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MAC_CTRL_PHY_LEDCTRL 0x000000e0 /* Onchip EPHY LED Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MAC_CTRL_PHY_LEDCTRL_SHIFT 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define B44_MAC_FLOW 0x00ACUL /* MAC Flow Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MAC_FLOW_RX_HI_WATER 0x000000ff /* Receive FIFO HI Water Mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MAC_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define B44_RCV_LAZY 0x0100UL /* Lazy Interrupt Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define RCV_LAZY_TO_MASK 0x00ffffff /* Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define RCV_LAZY_FC_MASK 0xff000000 /* Frame Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define RCV_LAZY_FC_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define B44_DMATX_CTRL 0x0200UL /* DMA TX Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMATX_CTRL_ENABLE 0x00000001 /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMATX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DMATX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DMATX_CTRL_FAIRPRIOR 0x00000008 /* Fair Priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DMATX_CTRL_FLUSH 0x00000010 /* Flush Request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define B44_DMATX_ADDR 0x0204UL /* DMA TX Descriptor Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define B44_DMATX_PTR 0x0208UL /* DMA TX Last Posted Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define B44_DMATX_STAT 0x020CUL /* DMA TX Current Active Desc. + Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DMATX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DMATX_STAT_SMASK 0x0000f000 /* State Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DMATX_STAT_SDISABLED 0x00000000 /* State Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DMATX_STAT_SACTIVE 0x00001000 /* State Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DMATX_STAT_SIDLE 0x00002000 /* State Idle Wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DMATX_STAT_SSTOPPED 0x00003000 /* State Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DMATX_STAT_SSUSP 0x00004000 /* State Suspend Pending */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DMATX_STAT_EMASK 0x000f0000 /* Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DMATX_STAT_ENONE 0x00000000 /* Error None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DMATX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DMATX_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DMATX_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DMATX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DMATX_STAT_FLUSHED 0x00100000 /* Flushed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define B44_DMARX_CTRL 0x0210UL /* DMA RX Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DMARX_CTRL_ENABLE 0x00000001 /* Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DMARX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DMARX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define B44_DMARX_ADDR 0x0214UL /* DMA RX Descriptor Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define B44_DMARX_PTR 0x0218UL /* DMA RX Last Posted Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define B44_DMARX_STAT 0x021CUL /* DMA RX Current Active Desc. + Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DMARX_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define DMARX_STAT_SMASK 0x0000f000 /* State Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DMARX_STAT_SDISABLED 0x00000000 /* State Disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DMARX_STAT_SACTIVE 0x00001000 /* State Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DMARX_STAT_SIDLE 0x00002000 /* State Idle Wait */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DMARX_STAT_SSTOPPED 0x00003000 /* State Stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DMARX_STAT_EMASK 0x000f0000 /* Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DMARX_STAT_ENONE 0x00000000 /* Error None */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DMARX_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DMARX_STAT_EDFO 0x00020000 /* Error Data FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DMARX_STAT_EBEBW 0x00030000 /* Error Bus Error on Buffer Write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define DMARX_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define B44_DMAFIFO_AD 0x0220UL /* DMA FIFO Diag Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define DMAFIFO_AD_OMASK 0x0000ffff /* Offset Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DMAFIFO_AD_SMASK 0x000f0000 /* Select Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DMAFIFO_AD_SXDD 0x00000000 /* Select Transmit DMA Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DMAFIFO_AD_SXDP 0x00010000 /* Select Transmit DMA Pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DMAFIFO_AD_SRDD 0x00040000 /* Select Receive DMA Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define DMAFIFO_AD_SRDP 0x00050000 /* Select Receive DMA Pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define DMAFIFO_AD_SXFD 0x00080000 /* Select Transmit FIFO Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DMAFIFO_AD_SXFP 0x00090000 /* Select Transmit FIFO Pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMAFIFO_AD_SRFD 0x000c0000 /* Select Receive FIFO Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DMAFIFO_AD_SRFP 0x000c0000 /* Select Receive FIFO Pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define B44_DMAFIFO_LO 0x0224UL /* DMA FIFO Diag Low Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define B44_DMAFIFO_HI 0x0228UL /* DMA FIFO Diag High Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define B44_RXCONFIG 0x0400UL /* EMAC RX Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define RXCONFIG_DBCAST 0x00000001 /* Disable Broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define RXCONFIG_ALLMULTI 0x00000002 /* Accept All Multicast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define RXCONFIG_NORX_WHILE_TX 0x00000004 /* Receive Disable While Transmitting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define RXCONFIG_PROMISC 0x00000008 /* Promiscuous Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define RXCONFIG_LPBACK 0x00000010 /* Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define RXCONFIG_FLOW 0x00000020 /* Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define RXCONFIG_FLOW_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define RXCONFIG_RFILT 0x00000080 /* Reject Filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RXCONFIG_CAM_ABSENT 0x00000100 /* CAM Absent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define B44_RXMAXLEN 0x0404UL /* EMAC RX Max Packet Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define B44_TXMAXLEN 0x0408UL /* EMAC TX Max Packet Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define B44_MDIO_CTRL 0x0410UL /* EMAC MDIO Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MDIO_CTRL_MAXF_MASK 0x0000007f /* MDC Frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MDIO_CTRL_PREAMBLE 0x00000080 /* MII Preamble Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define B44_MDIO_DATA 0x0414UL /* EMAC MDIO Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MDIO_DATA_DATA 0x0000ffff /* R/W Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MDIO_DATA_TA_MASK 0x00030000 /* Turnaround Value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MDIO_DATA_TA_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MDIO_TA_VALID 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MDIO_DATA_RA_MASK 0x007c0000 /* Register Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MDIO_DATA_RA_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MDIO_DATA_PMD_MASK 0x0f800000 /* Physical Media Device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MDIO_DATA_PMD_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MDIO_DATA_OP_MASK 0x30000000 /* Opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MDIO_DATA_OP_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MDIO_OP_WRITE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MDIO_OP_READ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MDIO_DATA_SB_MASK 0xc0000000 /* Start Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MDIO_DATA_SB_SHIFT 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MDIO_DATA_SB_START 0x40000000 /* Start Of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define B44_EMAC_IMASK 0x0418UL /* EMAC Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define B44_EMAC_ISTAT 0x041CUL /* EMAC Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define B44_CAM_DATA_LO 0x0420UL /* EMAC CAM Data Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define B44_CAM_DATA_HI 0x0424UL /* EMAC CAM Data High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CAM_DATA_HI_VALID 0x00010000 /* Valid Bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define B44_CAM_CTRL 0x0428UL /* EMAC CAM Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CAM_CTRL_ENABLE 0x00000001 /* CAM Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CAM_CTRL_MSEL 0x00000002 /* Mask Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CAM_CTRL_READ 0x00000004 /* Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CAM_CTRL_WRITE 0x00000008 /* Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CAM_CTRL_INDEX_MASK 0x003f0000 /* Index Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CAM_CTRL_INDEX_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CAM_CTRL_BUSY 0x80000000 /* CAM Busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define B44_ENET_CTRL 0x042CUL /* EMAC ENET Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ENET_CTRL_ENABLE 0x00000001 /* EMAC Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ENET_CTRL_DISABLE 0x00000002 /* EMAC Disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ENET_CTRL_SRST 0x00000004 /* EMAC Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ENET_CTRL_EPSEL 0x00000008 /* External PHY Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define B44_TX_CTRL 0x0430UL /* EMAC TX Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TX_CTRL_DUPLEX 0x00000001 /* Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TX_CTRL_FMODE 0x00000002 /* Flow Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TX_CTRL_SBENAB 0x00000004 /* Single Backoff Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TX_CTRL_SMALL_SLOT 0x00000008 /* Small Slottime */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define B44_TX_WMARK 0x0434UL /* EMAC TX Watermark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define B44_MIB_CTRL 0x0438UL /* EMAC MIB Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MIB_CTRL_CLR_ON_READ 0x00000001 /* Autoclear on Read */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define B44_TX_GOOD_O 0x0500UL /* MIB TX Good Octets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define B44_TX_GOOD_P 0x0504UL /* MIB TX Good Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define B44_TX_O 0x0508UL /* MIB TX Octets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define B44_TX_P 0x050CUL /* MIB TX Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define B44_TX_BCAST 0x0510UL /* MIB TX Broadcast Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define B44_TX_MCAST 0x0514UL /* MIB TX Multicast Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define B44_TX_64 0x0518UL /* MIB TX <= 64 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define B44_TX_65_127 0x051CUL /* MIB TX 65 to 127 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define B44_TX_128_255 0x0520UL /* MIB TX 128 to 255 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define B44_TX_256_511 0x0524UL /* MIB TX 256 to 511 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define B44_TX_512_1023 0x0528UL /* MIB TX 512 to 1023 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define B44_TX_1024_MAX 0x052CUL /* MIB TX 1024 to max byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define B44_TX_JABBER 0x0530UL /* MIB TX Jabber Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define B44_TX_OSIZE 0x0534UL /* MIB TX Oversize Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define B44_TX_FRAG 0x0538UL /* MIB TX Fragment Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define B44_TX_URUNS 0x053CUL /* MIB TX Underruns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define B44_TX_TCOLS 0x0540UL /* MIB TX Total Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define B44_TX_SCOLS 0x0544UL /* MIB TX Single Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define B44_TX_MCOLS 0x0548UL /* MIB TX Multiple Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define B44_TX_ECOLS 0x054CUL /* MIB TX Excessive Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define B44_TX_LCOLS 0x0550UL /* MIB TX Late Collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define B44_TX_DEFERED 0x0554UL /* MIB TX Defered Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define B44_TX_CLOST 0x0558UL /* MIB TX Carrier Lost */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define B44_TX_PAUSE 0x055CUL /* MIB TX Pause Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define B44_RX_GOOD_O 0x0580UL /* MIB RX Good Octets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define B44_RX_GOOD_P 0x0584UL /* MIB RX Good Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define B44_RX_O 0x0588UL /* MIB RX Octets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define B44_RX_P 0x058CUL /* MIB RX Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define B44_RX_BCAST 0x0590UL /* MIB RX Broadcast Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define B44_RX_MCAST 0x0594UL /* MIB RX Multicast Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define B44_RX_64 0x0598UL /* MIB RX <= 64 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define B44_RX_65_127 0x059CUL /* MIB RX 65 to 127 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define B44_RX_128_255 0x05A0UL /* MIB RX 128 to 255 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define B44_RX_256_511 0x05A4UL /* MIB RX 256 to 511 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define B44_RX_512_1023 0x05A8UL /* MIB RX 512 to 1023 byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define B44_RX_1024_MAX 0x05ACUL /* MIB RX 1024 to max byte Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define B44_RX_JABBER 0x05B0UL /* MIB RX Jabber Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define B44_RX_OSIZE 0x05B4UL /* MIB RX Oversize Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define B44_RX_FRAG 0x05B8UL /* MIB RX Fragment Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define B44_RX_MISS 0x05BCUL /* MIB RX Missed Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define B44_RX_CRCA 0x05C0UL /* MIB RX CRC Align Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define B44_RX_USIZE 0x05C4UL /* MIB RX Undersize Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define B44_RX_CRC 0x05C8UL /* MIB RX CRC Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define B44_RX_ALIGN 0x05CCUL /* MIB RX Align Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define B44_RX_SYM 0x05D0UL /* MIB RX Symbol Errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define B44_RX_PAUSE 0x05D4UL /* MIB RX Pause Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define B44_RX_NPAUSE 0x05D8UL /* MIB RX Non-Pause Packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* 4400 PHY registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define B44_MII_AUXCTRL 24 /* Auxiliary Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MII_AUXCTRL_DUPLEX 0x0001 /* Full Duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MII_AUXCTRL_SPEED 0x0002 /* 1=100Mbps, 0=10Mbps */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MII_AUXCTRL_FORCED 0x0004 /* Forced 10/100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define B44_MII_ALEDCTRL 26 /* Activity LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MII_ALEDCTRL_ALLMSK 0x7fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define B44_MII_TLEDCTRL 27 /* Traffic Meter LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MII_TLEDCTRL_ENABLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) __le32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* There are only 12 bits in the DMA engine for descriptor offsetting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * so the table must be aligned on a boundary of this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define DMA_TABLE_BYTES 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define DESC_CTRL_LEN 0x00001fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DESC_CTRL_CMASK 0x0ff00000 /* Core specific bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DESC_CTRL_EOT 0x10000000 /* End of Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define DESC_CTRL_IOC 0x20000000 /* Interrupt On Completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define DESC_CTRL_EOF 0x40000000 /* End of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define DESC_CTRL_SOF 0x80000000 /* Start of Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define RX_COPY_THRESHOLD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct rx_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) __le16 pad[12];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define RX_HEADER_LEN 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define RX_FLAG_CRCERR 0x00000002 /* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define RX_FLAG_ERRORS (RX_FLAG_ODD | RX_FLAG_SERR | RX_FLAG_CRCERR | RX_FLAG_OFIFO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) struct ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define B44_MCAST_TABLE_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) /* no local phy regs, e.g: Broadcom switches pseudo-PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define B44_PHY_ADDR_NO_LOCAL_PHY BRCM_PSEUDO_PHY_ADDR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* no phy present at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define B44_PHY_ADDR_NO_PHY 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define B44_MDC_RATIO 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define B44_STAT_REG_DECLARE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) _B44(tx_good_octets) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) _B44(tx_good_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) _B44(tx_octets) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) _B44(tx_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) _B44(tx_broadcast_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) _B44(tx_multicast_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) _B44(tx_len_64) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) _B44(tx_len_65_to_127) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) _B44(tx_len_128_to_255) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) _B44(tx_len_256_to_511) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) _B44(tx_len_512_to_1023) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) _B44(tx_len_1024_to_max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) _B44(tx_jabber_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) _B44(tx_oversize_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) _B44(tx_fragment_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) _B44(tx_underruns) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) _B44(tx_total_cols) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) _B44(tx_single_cols) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) _B44(tx_multiple_cols) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) _B44(tx_excessive_cols) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) _B44(tx_late_cols) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) _B44(tx_defered) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) _B44(tx_carrier_lost) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) _B44(tx_pause_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) _B44(rx_good_octets) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) _B44(rx_good_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) _B44(rx_octets) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) _B44(rx_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) _B44(rx_broadcast_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) _B44(rx_multicast_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) _B44(rx_len_64) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) _B44(rx_len_65_to_127) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) _B44(rx_len_128_to_255) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) _B44(rx_len_256_to_511) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) _B44(rx_len_512_to_1023) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) _B44(rx_len_1024_to_max) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) _B44(rx_jabber_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) _B44(rx_oversize_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) _B44(rx_fragment_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) _B44(rx_missed_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) _B44(rx_crc_align_errs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) _B44(rx_undersize) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) _B44(rx_crc_errs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) _B44(rx_align_errs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) _B44(rx_symbol_errs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) _B44(rx_pause_pkts) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) _B44(rx_nonpause_pkts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* SW copy of device statistics, kept up to date by periodic timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * which probes HW values. Check b44_stats_update if you mess with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * the layout
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct b44_hw_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define _B44(x) u64 x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) B44_STAT_REG_DECLARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #undef _B44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct u64_stats_sync syncp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define B44_BOARDFLAG_ROBO 0x0010 /* Board has robo switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define B44_BOARDFLAG_ADM 0x0080 /* Board has ADMtek switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct ssb_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct b44 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) u32 imask, istat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct dma_desc *rx_ring, *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 tx_prod, tx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 rx_prod, rx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct ring_info *rx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct ring_info *tx_buffers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u32 dma_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define B44_FLAG_B0_ANDLATER 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define B44_FLAG_BUGGY_TXPTR 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define B44_FLAG_REORDER_BUG 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define B44_FLAG_PAUSE_AUTO 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define B44_FLAG_FULL_DUPLEX 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define B44_FLAG_100_BASE_T 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define B44_FLAG_TX_PAUSE 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define B44_FLAG_RX_PAUSE 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define B44_FLAG_FORCE_LINK 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define B44_FLAG_ADV_10HALF 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define B44_FLAG_ADV_10FULL 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define B44_FLAG_ADV_100HALF 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define B44_FLAG_ADV_100FULL 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define B44_FLAG_EXTERNAL_PHY 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define B44_FLAG_RX_RING_HACK 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define B44_FLAG_TX_RING_HACK 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define B44_FLAG_WOL_ENABLE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) struct b44_hw_stats hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct ssb_device *sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dma_addr_t rx_ring_dma, tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u32 rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 tx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u8 phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u8 force_copybreak;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int old_link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) struct mii_if_info mii_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #endif /* _B44_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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