^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* b44.c: Broadcom 44xx/47xx Fast Ethernet device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2002 David S. Miller (davem@redhat.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2004 Pekka Pietikainen (pp@ee.oulu.fi)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 Felix Fietkau (nbd@openwrt.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (C) 2006 Broadcom Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 2007 Michael Buesch <m@bues.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2013 Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Distribute under GPL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/ssb/ssb.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "b44.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DRV_MODULE_NAME "b44"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DRV_DESCRIPTION "Broadcom 44xx/47xx 10/100 PCI ethernet driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define B44_DEF_MSG_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) (NETIF_MSG_DRV | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) NETIF_MSG_PROBE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) NETIF_MSG_LINK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) NETIF_MSG_TIMER | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) NETIF_MSG_IFDOWN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) NETIF_MSG_IFUP | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) NETIF_MSG_RX_ERR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) NETIF_MSG_TX_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* length of time before we decide the hardware is borked,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * and dev->tx_timeout() should be called to fix the problem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define B44_TX_TIMEOUT (5 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* hardware minimum and maximum for a single frame's data payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define B44_MIN_MTU ETH_ZLEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define B44_MAX_MTU ETH_DATA_LEN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define B44_RX_RING_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define B44_DEF_RX_RING_PENDING 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) B44_RX_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define B44_TX_RING_SIZE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) B44_TX_RING_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TX_RING_GAP(BP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) (B44_TX_RING_SIZE - (BP)->tx_pending)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TX_BUFFS_AVAIL(BP) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) (((BP)->tx_cons <= (BP)->tx_prod) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RX_PKT_OFFSET (RX_HEADER_LEN + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RX_PKT_BUF_SZ (1536 + RX_PKT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* minimum number of free TX descriptors required to wake up TX process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* b44 internal pattern match filter info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define B44_PATTERN_BASE 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define B44_PATTERN_SIZE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define B44_PMASK_BASE 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define B44_PMASK_SIZE 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define B44_MAX_PATTERNS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define B44_ETHIPV6UDP_HLEN 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define B44_ETHIPV4UDP_HLEN 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MODULE_AUTHOR("Felix Fietkau, Florian Schirmer, Pekka Pietikainen, David S. Miller");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) MODULE_DESCRIPTION(DRV_DESCRIPTION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) static int b44_debug = -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) module_param(b44_debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) MODULE_PARM_DESC(b44_debug, "B44 bitmapped debugging message enable value");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #ifdef CONFIG_B44_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static const struct pci_device_id b44_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B0) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, PCI_DEVICE_ID_BCM4401B1) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) { 0 } /* terminate list with empty entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) MODULE_DEVICE_TABLE(pci, b44_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static struct pci_driver b44_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .name = DRV_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .id_table = b44_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #endif /* CONFIG_B44_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static const struct ssb_device_id b44_ssb_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) SSB_DEVICE(SSB_VENDOR_BROADCOM, SSB_DEV_ETHERNET, SSB_ANY_REV),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) MODULE_DEVICE_TABLE(ssb, b44_ssb_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) static void b44_halt(struct b44 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void b44_init_rings(struct b44 *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define B44_FULL_RESET 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define B44_FULL_RESET_SKIP_PHY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define B44_PARTIAL_RESET 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define B44_CHIP_RESET_FULL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define B44_CHIP_RESET_PARTIAL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void b44_init_hw(struct b44 *, int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static int dma_desc_sync_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int instance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static const char b44_gstrings[][ETH_GSTRING_LEN] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define _B44(x...) # x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) B44_STAT_REG_DECLARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #undef _B44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) static inline void b44_sync_dma_desc_for_device(struct ssb_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dma_addr_t dma_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dma_sync_single_for_device(sdev->dma_dev, dma_base + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dma_desc_sync_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) static inline void b44_sync_dma_desc_for_cpu(struct ssb_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dma_addr_t dma_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned long offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dma_sync_single_for_cpu(sdev->dma_dev, dma_base + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dma_desc_sync_size, dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline unsigned long br32(const struct b44 *bp, unsigned long reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) return ssb_read32(bp->sdev, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline void bw32(const struct b44 *bp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) unsigned long reg, unsigned long val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ssb_write32(bp->sdev, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int b44_wait_bit(struct b44 *bp, unsigned long reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u32 bit, unsigned long timeout, const int clear)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) unsigned long i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = 0; i < timeout; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 val = br32(bp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (clear && !(val & bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) if (!clear && (val & bit))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (i == timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (net_ratelimit())
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) netdev_err(bp->dev, "BUG! Timeout waiting for bit %08x of register %lx to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) bit, reg, clear ? "clear" : "set");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static inline void __b44_cam_read(struct b44 *bp, unsigned char *data, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bw32(bp, B44_CAM_CTRL, (CAM_CTRL_READ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) (index << CAM_CTRL_INDEX_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) val = br32(bp, B44_CAM_DATA_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) data[2] = (val >> 24) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) data[3] = (val >> 16) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) data[4] = (val >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) data[5] = (val >> 0) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) val = br32(bp, B44_CAM_DATA_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) data[0] = (val >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) data[1] = (val >> 0) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static inline void __b44_cam_write(struct b44 *bp, unsigned char *data, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) val = ((u32) data[2]) << 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) val |= ((u32) data[3]) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) val |= ((u32) data[4]) << 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) val |= ((u32) data[5]) << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) bw32(bp, B44_CAM_DATA_LO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) val = (CAM_DATA_HI_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) (((u32) data[0]) << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) (((u32) data[1]) << 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bw32(bp, B44_CAM_DATA_HI, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) bw32(bp, B44_CAM_CTRL, (CAM_CTRL_WRITE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) (index << CAM_CTRL_INDEX_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) b44_wait_bit(bp, B44_CAM_CTRL, CAM_CTRL_BUSY, 100, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) static inline void __b44_disable_ints(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) bw32(bp, B44_IMASK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static void b44_disable_ints(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __b44_disable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* Flush posted writes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) br32(bp, B44_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void b44_enable_ints(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) bw32(bp, B44_IMASK, bp->imask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static int __b44_readphy(struct b44 *bp, int phy_addr, int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) (MDIO_OP_READ << MDIO_DATA_OP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) (phy_addr << MDIO_DATA_PMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) (reg << MDIO_DATA_RA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) err = b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) *val = br32(bp, B44_MDIO_DATA) & MDIO_DATA_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) static int __b44_writephy(struct b44 *bp, int phy_addr, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) bw32(bp, B44_EMAC_ISTAT, EMAC_INT_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) bw32(bp, B44_MDIO_DATA, (MDIO_DATA_SB_START |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) (MDIO_OP_WRITE << MDIO_DATA_OP_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) (phy_addr << MDIO_DATA_PMD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) (reg << MDIO_DATA_RA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) (MDIO_TA_VALID << MDIO_DATA_TA_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) (val & MDIO_DATA_DATA)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return b44_wait_bit(bp, B44_EMAC_ISTAT, EMAC_INT_MII, 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static inline int b44_readphy(struct b44 *bp, int reg, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) return __b44_readphy(bp, bp->phy_addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static inline int b44_writephy(struct b44 *bp, int reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return __b44_writephy(bp, bp->phy_addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* miilib interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static int b44_mdio_read_mii(struct net_device *dev, int phy_id, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int rc = __b44_readphy(bp, phy_id, location, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) static void b44_mdio_write_mii(struct net_device *dev, int phy_id, int location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) __b44_writephy(bp, phy_id, location, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static int b44_mdio_read_phylib(struct mii_bus *bus, int phy_id, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct b44 *bp = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int rc = __b44_readphy(bp, phy_id, location, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static int b44_mdio_write_phylib(struct mii_bus *bus, int phy_id, int location,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct b44 *bp = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return __b44_writephy(bp, phy_id, location, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static int b44_phy_reset(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) err = b44_writephy(bp, MII_BMCR, BMCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) err = b44_readphy(bp, MII_BMCR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (val & BMCR_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) netdev_err(bp->dev, "PHY Reset would not complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) static void __b44_set_flow_ctrl(struct b44 *bp, u32 pause_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) bp->flags &= ~(B44_FLAG_TX_PAUSE | B44_FLAG_RX_PAUSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) bp->flags |= pause_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = br32(bp, B44_RXCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (pause_flags & B44_FLAG_RX_PAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val |= RXCONFIG_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) val &= ~RXCONFIG_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bw32(bp, B44_RXCONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) val = br32(bp, B44_MAC_FLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (pause_flags & B44_FLAG_TX_PAUSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) val |= (MAC_FLOW_PAUSE_ENAB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) (0xc0 & MAC_FLOW_RX_HI_WATER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) val &= ~MAC_FLOW_PAUSE_ENAB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bw32(bp, B44_MAC_FLOW, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) static void b44_set_flow_ctrl(struct b44 *bp, u32 local, u32 remote)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) u32 pause_enab = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* The driver supports only rx pause by default because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) the b44 mac tx pause mechanism generates excessive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) pause frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) Use ethtool to turn on b44 tx pause if necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if ((local & ADVERTISE_PAUSE_CAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) (local & ADVERTISE_PAUSE_ASYM)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if ((remote & LPA_PAUSE_ASYM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) !(remote & LPA_PAUSE_CAP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) pause_enab |= B44_FLAG_RX_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) __b44_set_flow_ctrl(bp, pause_enab);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #ifdef CONFIG_BCM47XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #include <linux/bcm47xx_nvram.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static void b44_wap54g10_workaround(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) char buf[20];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * workaround for bad hardware design in Linksys WAP54G v1.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * see https://dev.openwrt.org/ticket/146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * check and reset bit "isolate"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (bcm47xx_nvram_getenv("boardnum", buf, sizeof(buf)) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (simple_strtoul(buf, NULL, 0) == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) err = __b44_readphy(bp, 0, MII_BMCR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!(val & BMCR_ISOLATE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) val &= ~BMCR_ISOLATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) err = __b44_writephy(bp, 0, MII_BMCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) goto error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) error:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) pr_warn("PHY: cannot reset MII transceiver isolate bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) static inline void b44_wap54g10_workaround(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int b44_setup_phy(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) b44_wap54g10_workaround(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if ((err = b44_readphy(bp, B44_MII_ALEDCTRL, &val)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) if ((err = b44_writephy(bp, B44_MII_ALEDCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) val & MII_ALEDCTRL_ALLMSK)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if ((err = b44_readphy(bp, B44_MII_TLEDCTRL, &val)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if ((err = b44_writephy(bp, B44_MII_TLEDCTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) val | MII_TLEDCTRL_ENABLE)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (!(bp->flags & B44_FLAG_FORCE_LINK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u32 adv = ADVERTISE_CSMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (bp->flags & B44_FLAG_ADV_10HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) adv |= ADVERTISE_10HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (bp->flags & B44_FLAG_ADV_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) adv |= ADVERTISE_10FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (bp->flags & B44_FLAG_ADV_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) adv |= ADVERTISE_100HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) if (bp->flags & B44_FLAG_ADV_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) adv |= ADVERTISE_100FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (bp->flags & B44_FLAG_PAUSE_AUTO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) adv |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if ((err = b44_writephy(bp, MII_ADVERTISE, adv)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if ((err = b44_writephy(bp, MII_BMCR, (BMCR_ANENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) BMCR_ANRESTART))) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if ((err = b44_readphy(bp, MII_BMCR, &bmcr)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bmcr &= ~(BMCR_FULLDPLX | BMCR_ANENABLE | BMCR_SPEED100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (bp->flags & B44_FLAG_100_BASE_T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) bmcr |= BMCR_SPEED100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (bp->flags & B44_FLAG_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) bmcr |= BMCR_FULLDPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if ((err = b44_writephy(bp, MII_BMCR, bmcr)) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /* Since we will not be negotiating there is no safe way
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) * to determine if the link partner supports flow control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) * or not. So just disable it completely in this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) b44_set_flow_ctrl(bp, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static void b44_stats_update(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u64 *val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val = &bp->hw_stats.tx_good_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u64_stats_update_begin(&bp->hw_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) *val++ += br32(bp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *val++ += br32(bp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u64_stats_update_end(&bp->hw_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) static void b44_link_report(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) if (!netif_carrier_ok(bp->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) netdev_info(bp->dev, "Link is down\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) netdev_info(bp->dev, "Link is up at %d Mbps, %s duplex\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) (bp->flags & B44_FLAG_100_BASE_T) ? 100 : 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) (bp->flags & B44_FLAG_FULL_DUPLEX) ? "full" : "half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) netdev_info(bp->dev, "Flow control is %s for TX and %s for RX\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) (bp->flags & B44_FLAG_TX_PAUSE) ? "on" : "off",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) (bp->flags & B44_FLAG_RX_PAUSE) ? "on" : "off");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) static void b44_check_phy(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 bmsr, aux;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) bp->flags |= B44_FLAG_100_BASE_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) if (!netif_carrier_ok(bp->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 val = br32(bp, B44_TX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (bp->flags & B44_FLAG_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val |= TX_CTRL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val &= ~TX_CTRL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) bw32(bp, B44_TX_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) netif_carrier_on(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) b44_link_report(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (!b44_readphy(bp, MII_BMSR, &bmsr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) !b44_readphy(bp, B44_MII_AUXCTRL, &aux) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) (bmsr != 0xffff)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (aux & MII_AUXCTRL_SPEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bp->flags |= B44_FLAG_100_BASE_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) bp->flags &= ~B44_FLAG_100_BASE_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (aux & MII_AUXCTRL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) bp->flags |= B44_FLAG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) bp->flags &= ~B44_FLAG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (!netif_carrier_ok(bp->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) (bmsr & BMSR_LSTATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 val = br32(bp, B44_TX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 local_adv, remote_adv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (bp->flags & B44_FLAG_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) val |= TX_CTRL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) val &= ~TX_CTRL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) bw32(bp, B44_TX_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (!(bp->flags & B44_FLAG_FORCE_LINK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) !b44_readphy(bp, MII_ADVERTISE, &local_adv) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) !b44_readphy(bp, MII_LPA, &remote_adv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) b44_set_flow_ctrl(bp, local_adv, remote_adv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Link now up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) netif_carrier_on(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) b44_link_report(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) } else if (netif_carrier_ok(bp->dev) && !(bmsr & BMSR_LSTATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /* Link now down */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) netif_carrier_off(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) b44_link_report(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (bmsr & BMSR_RFAULT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) netdev_warn(bp->dev, "Remote fault detected in PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (bmsr & BMSR_JCD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) netdev_warn(bp->dev, "Jabber detected in PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void b44_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct b44 *bp = from_timer(bp, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) b44_check_phy(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) b44_stats_update(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) mod_timer(&bp->timer, round_jiffies(jiffies + HZ));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static void b44_tx(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u32 cur, cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cur = br32(bp, B44_DMATX_STAT) & DMATX_STAT_CDMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) cur /= sizeof(struct dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* XXX needs updating when NETIF_F_SG is supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) for (cons = bp->tx_cons; cons != cur; cons = NEXT_TX(cons)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) struct ring_info *rp = &bp->tx_buffers[cons];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct sk_buff *skb = rp->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) BUG_ON(skb == NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dma_unmap_single(bp->sdev->dma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) rp->mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) rp->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) bytes_compl += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) netdev_completed_queue(bp->dev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) bp->tx_cons = cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (netif_queue_stopped(bp->dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) TX_BUFFS_AVAIL(bp) > B44_TX_WAKEUP_THRESH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) netif_wake_queue(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) bw32(bp, B44_GPTIMER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Works like this. This chip writes a 'struct rx_header" 30 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * before the DMA address you give it. So we allocate 30 more bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * point the chip at 30 bytes past where the rx_header will go.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int b44_alloc_rx_skb(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct dma_desc *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct ring_info *src_map, *map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct rx_header *rh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) int dest_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) src_map = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) if (src_idx >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) src_map = &bp->rx_buffers[src_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) map = &bp->rx_buffers[dest_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) skb = netdev_alloc_skb(bp->dev, RX_PKT_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) RX_PKT_BUF_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* Hardware bug work-around, the chip is unable to do PCI DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) to/from anything above 1GB :-( */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* Sigh... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) dma_unmap_single(bp->sdev->dma_dev, mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) RX_PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) skb = alloc_skb(RX_PKT_BUF_SZ, GFP_ATOMIC | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) mapping = dma_map_single(bp->sdev->dma_dev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) RX_PKT_BUF_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (dma_mapping_error(bp->sdev->dma_dev, mapping) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) mapping + RX_PKT_BUF_SZ > DMA_BIT_MASK(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dma_unmap_single(bp->sdev->dma_dev, mapping, RX_PKT_BUF_SZ,DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bp->force_copybreak = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rh = (struct rx_header *) skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) rh->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) rh->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) map->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) map->mapping = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (src_map != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) src_map->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ctrl = (DESC_CTRL_LEN & RX_PKT_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) if (dest_idx == (B44_RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) ctrl |= DESC_CTRL_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dp = &bp->rx_ring[dest_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dp->ctrl = cpu_to_le32(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dp->addr = cpu_to_le32((u32) mapping + bp->dma_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (bp->flags & B44_FLAG_RX_RING_HACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dest_idx * sizeof(*dp),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) return RX_PKT_BUF_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) static void b44_recycle_rx(struct b44 *bp, int src_idx, u32 dest_idx_unmasked)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct dma_desc *src_desc, *dest_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct ring_info *src_map, *dest_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) struct rx_header *rh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) int dest_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) __le32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) dest_idx = dest_idx_unmasked & (B44_RX_RING_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dest_desc = &bp->rx_ring[dest_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dest_map = &bp->rx_buffers[dest_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) src_desc = &bp->rx_ring[src_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) src_map = &bp->rx_buffers[src_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) dest_map->skb = src_map->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) rh = (struct rx_header *) src_map->skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) rh->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) rh->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) dest_map->mapping = src_map->mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (bp->flags & B44_FLAG_RX_RING_HACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) b44_sync_dma_desc_for_cpu(bp->sdev, bp->rx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) src_idx * sizeof(*src_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) ctrl = src_desc->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) if (dest_idx == (B44_RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) ctrl |= cpu_to_le32(DESC_CTRL_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) ctrl &= cpu_to_le32(~DESC_CTRL_EOT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dest_desc->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) dest_desc->addr = src_desc->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) src_map->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (bp->flags & B44_FLAG_RX_RING_HACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) b44_sync_dma_desc_for_device(bp->sdev, bp->rx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) dest_idx * sizeof(*dest_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dma_sync_single_for_device(bp->sdev->dma_dev, dest_map->mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) RX_PKT_BUF_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int b44_rx(struct b44 *bp, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) int received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 cons, prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) received = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) prod = br32(bp, B44_DMARX_STAT) & DMARX_STAT_CDMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) prod /= sizeof(struct dma_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) cons = bp->rx_cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) while (cons != prod && budget > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct ring_info *rp = &bp->rx_buffers[cons];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) struct sk_buff *skb = rp->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dma_addr_t map = rp->mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) struct rx_header *rh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) u16 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dma_sync_single_for_cpu(bp->sdev->dma_dev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) RX_PKT_BUF_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) rh = (struct rx_header *) skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) len = le16_to_cpu(rh->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if ((len > (RX_PKT_BUF_SZ - RX_PKT_OFFSET)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) (rh->flags & cpu_to_le16(RX_FLAG_ERRORS))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) drop_it:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) b44_recycle_rx(bp, cons, bp->rx_prod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) drop_it_no_recycle:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) bp->dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) goto next_pkt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if (len == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) len = le16_to_cpu(rh->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } while (len == 0 && i++ < 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) goto drop_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /* Omit CRC. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!bp->force_copybreak && len > RX_COPY_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int skb_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) skb_size = b44_alloc_rx_skb(bp, cons, bp->rx_prod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (skb_size < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) goto drop_it;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) dma_unmap_single(bp->sdev->dma_dev, map,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) skb_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Leave out rx_header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) skb_put(skb, len + RX_PKT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) skb_pull(skb, RX_PKT_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) struct sk_buff *copy_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) b44_recycle_rx(bp, cons, bp->rx_prod);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) copy_skb = napi_alloc_skb(&bp->napi, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (copy_skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) goto drop_it_no_recycle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) skb_put(copy_skb, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /* DMA sync done above, copy just the actual packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) skb_copy_from_linear_data_offset(skb, RX_PKT_OFFSET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) copy_skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) skb = copy_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) skb_checksum_none_assert(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) skb->protocol = eth_type_trans(skb, bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) received++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) budget--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) next_pkt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) bp->rx_prod = (bp->rx_prod + 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) (B44_RX_RING_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) cons = (cons + 1) & (B44_RX_RING_SIZE - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) bp->rx_cons = cons;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) bw32(bp, B44_DMARX_PTR, cons * sizeof(struct dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return received;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int b44_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct b44 *bp = container_of(napi, struct b44, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) spin_lock_irqsave(&bp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (bp->istat & (ISTAT_TX | ISTAT_TO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* spin_lock(&bp->tx_lock); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) b44_tx(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* spin_unlock(&bp->tx_lock); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) if (bp->istat & ISTAT_RFO) { /* fast recovery, in ~20msec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) bp->istat &= ~ISTAT_RFO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) b44_disable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ssb_device_enable(bp->sdev, 0); /* resets ISTAT_RFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) netif_wake_queue(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) spin_unlock_irqrestore(&bp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) if (bp->istat & ISTAT_RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) work_done += b44_rx(bp, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (bp->istat & ISTAT_ERRORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) spin_lock_irqsave(&bp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) b44_init_hw(bp, B44_FULL_RESET_SKIP_PHY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) netif_wake_queue(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) spin_unlock_irqrestore(&bp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) work_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) napi_complete_done(napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) static irqreturn_t b44_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) u32 istat, imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) spin_lock(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) istat = br32(bp, B44_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) imask = br32(bp, B44_IMASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* The interrupt mask register controls which interrupt bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) * will actually raise an interrupt to the CPU when set by hw/firmware,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) * but doesn't mask off the bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) istat &= imask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (istat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) if (unlikely(!netif_running(dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) netdev_info(dev, "late interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) goto irq_ack;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if (napi_schedule_prep(&bp->napi)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* NOTE: These writes are posted by the readback of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * the ISTAT register below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) bp->istat = istat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) __b44_disable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) __napi_schedule(&bp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) irq_ack:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) bw32(bp, B44_ISTAT, istat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) br32(bp, B44_ISTAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) spin_unlock(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static void b44_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) netdev_err(dev, "transmit timed out, resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) b44_init_hw(bp, B44_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) static netdev_tx_t b44_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) int rc = NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dma_addr_t mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) u32 len, entry, ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) spin_lock_irqsave(&bp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* This is a hard error, log it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) if (unlikely(TX_BUFFS_AVAIL(bp) < 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) netdev_err(dev, "BUG! Tx Ring full when queue awake!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) mapping = dma_map_single(bp->sdev->dma_dev, skb->data, len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct sk_buff *bounce_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* Chip can't handle DMA to/from >1GB, use bounce buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) dma_unmap_single(bp->sdev->dma_dev, mapping, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) bounce_skb = alloc_skb(len, GFP_ATOMIC | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (!bounce_skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) mapping = dma_map_single(bp->sdev->dma_dev, bounce_skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (dma_mapping_error(bp->sdev->dma_dev, mapping) || mapping + len > DMA_BIT_MASK(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (!dma_mapping_error(bp->sdev->dma_dev, mapping))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dma_unmap_single(bp->sdev->dma_dev, mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev_kfree_skb_any(bounce_skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) skb_copy_from_linear_data(skb, skb_put(bounce_skb, len), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) skb = bounce_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) entry = bp->tx_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) bp->tx_buffers[entry].skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) bp->tx_buffers[entry].mapping = mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ctrl = (len & DESC_CTRL_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) ctrl |= DESC_CTRL_IOC | DESC_CTRL_SOF | DESC_CTRL_EOF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) if (entry == (B44_TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ctrl |= DESC_CTRL_EOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bp->tx_ring[entry].ctrl = cpu_to_le32(ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) bp->tx_ring[entry].addr = cpu_to_le32((u32) mapping+bp->dma_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (bp->flags & B44_FLAG_TX_RING_HACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) b44_sync_dma_desc_for_device(bp->sdev, bp->tx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) entry * sizeof(bp->tx_ring[0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) entry = NEXT_TX(entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) bp->tx_prod = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (bp->flags & B44_FLAG_BUGGY_TXPTR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) bw32(bp, B44_DMATX_PTR, entry * sizeof(struct dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (bp->flags & B44_FLAG_REORDER_BUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) br32(bp, B44_DMATX_PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) netdev_sent_queue(dev, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) if (TX_BUFFS_AVAIL(bp) < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) out_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) spin_unlock_irqrestore(&bp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) rc = NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) goto out_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) static int b44_change_mtu(struct net_device *dev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (!netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) /* We'll just catch it later when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) * device is up'd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) dev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) b44_init_hw(bp, B44_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /* Free up pending packets in all rx/tx rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * The chip has been shut down and the driver detached from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * the networking, so no interrupts or new tx packets will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * end up in the driver. bp->lock is not held and we are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * in an interrupt context and thus may sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static void b44_free_rings(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct ring_info *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) for (i = 0; i < B44_RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) rp = &bp->rx_buffers[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (rp->skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) dma_unmap_single(bp->sdev->dma_dev, rp->mapping, RX_PKT_BUF_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) dev_kfree_skb_any(rp->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) rp->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* XXX needs changes once NETIF_F_SG is set... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) for (i = 0; i < B44_TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) rp = &bp->tx_buffers[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (rp->skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dma_unmap_single(bp->sdev->dma_dev, rp->mapping, rp->skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_kfree_skb_any(rp->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) rp->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) /* Initialize tx/rx rings for packet processing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * The chip has been shut down and the driver detached from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * the networking, so no interrupts or new tx packets will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * end up in the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) static void b44_init_rings(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) b44_free_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) memset(bp->rx_ring, 0, B44_RX_RING_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) memset(bp->tx_ring, 0, B44_TX_RING_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) if (bp->flags & B44_FLAG_RX_RING_HACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) dma_sync_single_for_device(bp->sdev->dma_dev, bp->rx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (bp->flags & B44_FLAG_TX_RING_HACK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dma_sync_single_for_device(bp->sdev->dma_dev, bp->tx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) DMA_TABLE_BYTES, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) for (i = 0; i < bp->rx_pending; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (b44_alloc_rx_skb(bp, -1, i) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) * Must not be invoked with interrupt sources disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) * the hardware shutdown down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static void b44_free_consistent(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) kfree(bp->rx_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) bp->rx_buffers = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) kfree(bp->tx_buffers);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) bp->tx_buffers = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (bp->rx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (bp->flags & B44_FLAG_RX_RING_HACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dma_unmap_single(bp->sdev->dma_dev, bp->rx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) DMA_TABLE_BYTES, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) kfree(bp->rx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) bp->rx_ring, bp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) bp->rx_ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) bp->flags &= ~B44_FLAG_RX_RING_HACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (bp->tx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (bp->flags & B44_FLAG_TX_RING_HACK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dma_unmap_single(bp->sdev->dma_dev, bp->tx_ring_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) DMA_TABLE_BYTES, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) kfree(bp->tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dma_free_coherent(bp->sdev->dma_dev, DMA_TABLE_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) bp->tx_ring, bp->tx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) bp->tx_ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) bp->flags &= ~B44_FLAG_TX_RING_HACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) * Must not be invoked with interrupt sources disabled and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) * the hardware shutdown down. Can sleep.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) static int b44_alloc_consistent(struct b44 *bp, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) size = B44_RX_RING_SIZE * sizeof(struct ring_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) bp->rx_buffers = kzalloc(size, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (!bp->rx_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) size = B44_TX_RING_SIZE * sizeof(struct ring_info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) bp->tx_buffers = kzalloc(size, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (!bp->tx_buffers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) size = DMA_TABLE_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) bp->rx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) &bp->rx_ring_dma, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (!bp->rx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Allocation may have failed due to pci_alloc_consistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) insisting on use of GFP_DMA, which is more restrictive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) than necessary... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct dma_desc *rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) rx_ring = kzalloc(size, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (!rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) rx_ring_dma = dma_map_single(bp->sdev->dma_dev, rx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) DMA_TABLE_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (dma_mapping_error(bp->sdev->dma_dev, rx_ring_dma) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) rx_ring_dma + size > DMA_BIT_MASK(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) kfree(rx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) bp->rx_ring = rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) bp->rx_ring_dma = rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) bp->flags |= B44_FLAG_RX_RING_HACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) bp->tx_ring = dma_alloc_coherent(bp->sdev->dma_dev, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) &bp->tx_ring_dma, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (!bp->tx_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* Allocation may have failed due to ssb_dma_alloc_consistent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) insisting on use of GFP_DMA, which is more restrictive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) than necessary... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct dma_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) tx_ring = kzalloc(size, gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (!tx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) tx_ring_dma = dma_map_single(bp->sdev->dma_dev, tx_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) DMA_TABLE_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) if (dma_mapping_error(bp->sdev->dma_dev, tx_ring_dma) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) tx_ring_dma + size > DMA_BIT_MASK(30)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) kfree(tx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) goto out_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) bp->tx_ring = tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) bp->tx_ring_dma = tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) bp->flags |= B44_FLAG_TX_RING_HACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) out_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) b44_free_consistent(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) /* bp->lock is held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) static void b44_clear_stats(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) unsigned long reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) for (reg = B44_TX_GOOD_O; reg <= B44_TX_PAUSE; reg += 4UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) br32(bp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) for (reg = B44_RX_GOOD_O; reg <= B44_RX_NPAUSE; reg += 4UL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) br32(bp, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) /* bp->lock is held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) static void b44_chip_reset(struct b44 *bp, int reset_kind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) struct ssb_device *sdev = bp->sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) bool was_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) was_enabled = ssb_device_is_enabled(bp->sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) ssb_device_enable(bp->sdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) ssb_pcicore_dev_irqvecs_enable(&sdev->bus->pcicore, sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) if (was_enabled) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) bw32(bp, B44_RCV_LAZY, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) bw32(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) b44_wait_bit(bp, B44_ENET_CTRL, ENET_CTRL_DISABLE, 200, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) bw32(bp, B44_DMATX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) bp->tx_prod = bp->tx_cons = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (br32(bp, B44_DMARX_STAT) & DMARX_STAT_EMASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) b44_wait_bit(bp, B44_DMARX_STAT, DMARX_STAT_SIDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) 100, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) bw32(bp, B44_DMARX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) bp->rx_prod = bp->rx_cons = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) b44_clear_stats(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * Don't enable PHY if we are doing a partial reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * we are probably going to power down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) if (reset_kind == B44_CHIP_RESET_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) switch (sdev->bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) (DIV_ROUND_CLOSEST(ssb_clockspeed(sdev->bus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) B44_MDC_RATIO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) & MDIO_CTRL_MAXF_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) bw32(bp, B44_MDIO_CTRL, (MDIO_CTRL_PREAMBLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) (0x0d & MDIO_CTRL_MAXF_MASK)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) WARN_ON(1); /* A device with this bus does not exist. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) br32(bp, B44_MDIO_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) if (!(br32(bp, B44_DEVCTRL) & DEVCTRL_IPP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) bw32(bp, B44_ENET_CTRL, ENET_CTRL_EPSEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) br32(bp, B44_ENET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) bp->flags |= B44_FLAG_EXTERNAL_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) u32 val = br32(bp, B44_DEVCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (val & DEVCTRL_EPR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) bw32(bp, B44_DEVCTRL, (val & ~DEVCTRL_EPR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) br32(bp, B44_DEVCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) udelay(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) bp->flags &= ~B44_FLAG_EXTERNAL_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* bp->lock is held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) static void b44_halt(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) b44_disable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) /* reset PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) b44_phy_reset(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) /* power down PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) netdev_info(bp->dev, "powering down PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) bw32(bp, B44_MAC_CTRL, MAC_CTRL_PHY_PDOWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* now reset the chip, but without enabling the MAC&PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * part of it. This has to be done _after_ we shut down the PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) b44_chip_reset(bp, B44_CHIP_RESET_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* bp->lock is held. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static void __b44_set_mac_addr(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) bw32(bp, B44_CAM_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (!(bp->dev->flags & IFF_PROMISC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) __b44_cam_write(bp, bp->dev->dev_addr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) val = br32(bp, B44_CAM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int b44_set_mac_addr(struct net_device *dev, void *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct sockaddr *addr = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (!is_valid_ether_addr(addr->sa_data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) memcpy(dev->dev_addr, addr->sa_data, dev->addr_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) val = br32(bp, B44_RXCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (!(val & RXCONFIG_CAM_ABSENT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) __b44_set_mac_addr(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* Called at device open time to get the chip ready for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * packet processing. Invoked with bp->lock held.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) static void __b44_set_rx_mode(struct net_device *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) static void b44_init_hw(struct b44 *bp, int reset_kind)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) b44_chip_reset(bp, B44_CHIP_RESET_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (reset_kind == B44_FULL_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) b44_phy_reset(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) b44_setup_phy(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) /* Enable CRC32, set proper LED modes and power on PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) bw32(bp, B44_MAC_CTRL, MAC_CTRL_CRC32_ENAB | MAC_CTRL_PHY_LEDCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) bw32(bp, B44_RCV_LAZY, (1 << RCV_LAZY_FC_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) /* This sets the MAC address too. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) __b44_set_rx_mode(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* MTU + eth header + possible VLAN tag + struct rx_header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) bw32(bp, B44_RXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) bw32(bp, B44_TXMAXLEN, bp->dev->mtu + ETH_HLEN + 8 + RX_HEADER_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) bw32(bp, B44_TX_WMARK, 56); /* XXX magic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (reset_kind == B44_PARTIAL_RESET) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) bw32(bp, B44_DMATX_CTRL, DMATX_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) bw32(bp, B44_DMATX_ADDR, bp->tx_ring_dma + bp->dma_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) bw32(bp, B44_DMARX_CTRL, (DMARX_CTRL_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) (RX_PKT_OFFSET << DMARX_CTRL_ROSHIFT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) bw32(bp, B44_DMARX_ADDR, bp->rx_ring_dma + bp->dma_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) bw32(bp, B44_DMARX_PTR, bp->rx_pending);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) bp->rx_prod = bp->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) bw32(bp, B44_MIB_CTRL, MIB_CTRL_CLR_ON_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) val = br32(bp, B44_ENET_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) bw32(bp, B44_ENET_CTRL, (val | ENET_CTRL_ENABLE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) netdev_reset_queue(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) static int b44_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) err = b44_alloc_consistent(bp, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) napi_enable(&bp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) b44_init_hw(bp, B44_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) b44_check_phy(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) err = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (unlikely(err < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) napi_disable(&bp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) b44_chip_reset(bp, B44_CHIP_RESET_PARTIAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) b44_free_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) b44_free_consistent(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) timer_setup(&bp->timer, b44_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) bp->timer.expires = jiffies + HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) add_timer(&bp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) phy_start(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * Polling receive - used by netconsole and other diagnostic tools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * to allow network i/o with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) static void b44_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) disable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) b44_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) enable_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) static void bwfilter_table(struct b44 *bp, u8 *pp, u32 bytes, u32 table_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) u32 *pattern = (u32 *) pp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) for (i = 0; i < bytes; i += sizeof(u32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) bw32(bp, B44_FILT_ADDR, table_offset + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) bw32(bp, B44_FILT_DATA, pattern[i / sizeof(u32)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) static int b44_magic_pattern(u8 *macaddr, u8 *ppattern, u8 *pmask, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) int magicsync = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) int k, j, len = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) int ethaddr_bytes = ETH_ALEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) memset(ppattern + offset, 0xff, magicsync);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) for (j = 0; j < magicsync; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) pmask[len >> 3] |= BIT(len & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) for (j = 0; j < B44_MAX_PATTERNS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if ((B44_PATTERN_SIZE - len) >= ETH_ALEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ethaddr_bytes = ETH_ALEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) ethaddr_bytes = B44_PATTERN_SIZE - len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (ethaddr_bytes <=0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) for (k = 0; k< ethaddr_bytes; k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) ppattern[offset + magicsync +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) (j * ETH_ALEN) + k] = macaddr[k];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) pmask[len >> 3] |= BIT(len & 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) return len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) /* Setup magic packet patterns in the b44 WOL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) * pattern matching filter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) static void b44_setup_pseudo_magicp(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) int plen0, plen1, plen2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) u8 *pwol_pattern;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) u8 pwol_mask[B44_PMASK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) pwol_pattern = kzalloc(B44_PATTERN_SIZE, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (!pwol_pattern)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* Ipv4 magic packet pattern - pattern 0.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) memset(pwol_mask, 0, B44_PMASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) plen0 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) B44_ETHIPV4UDP_HLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE, B44_PATTERN_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE, B44_PMASK_BASE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) /* Raw ethernet II magic packet pattern - pattern 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) memset(pwol_pattern, 0, B44_PATTERN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) memset(pwol_mask, 0, B44_PMASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) plen1 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ETH_HLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) B44_PATTERN_BASE + B44_PATTERN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) B44_PMASK_BASE + B44_PMASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) /* Ipv6 magic packet pattern - pattern 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) memset(pwol_pattern, 0, B44_PATTERN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) memset(pwol_mask, 0, B44_PMASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) plen2 = b44_magic_pattern(bp->dev->dev_addr, pwol_pattern, pwol_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) B44_ETHIPV6UDP_HLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) bwfilter_table(bp, pwol_pattern, B44_PATTERN_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) B44_PATTERN_BASE + B44_PATTERN_SIZE + B44_PATTERN_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) bwfilter_table(bp, pwol_mask, B44_PMASK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) B44_PMASK_BASE + B44_PMASK_SIZE + B44_PMASK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) kfree(pwol_pattern);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* set these pattern's lengths: one less than each real length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) val = plen0 | (plen1 << 8) | (plen2 << 16) | WKUP_LEN_ENABLE_THREE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) bw32(bp, B44_WKUP_LEN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) /* enable wakeup pattern matching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) val = br32(bp, B44_DEVCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) bw32(bp, B44_DEVCTRL, val | DEVCTRL_PFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) #ifdef CONFIG_B44_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) static void b44_setup_wol_pci(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) if (bp->sdev->bus->bustype != SSB_BUSTYPE_SSB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) bw32(bp, SSB_TMSLOW, br32(bp, SSB_TMSLOW) | SSB_TMSLOW_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) pci_read_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) pci_write_config_word(bp->sdev->bus->host_pci, SSB_PMCSR, val | SSB_PE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) static inline void b44_setup_wol_pci(struct b44 *bp) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) #endif /* CONFIG_B44_PCI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) static void b44_setup_wol(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) bw32(bp, B44_RXCONFIG, RXCONFIG_ALLMULTI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (bp->flags & B44_FLAG_B0_ANDLATER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) bw32(bp, B44_WKUP_LEN, WKUP_LEN_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) val = bp->dev->dev_addr[2] << 24 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) bp->dev->dev_addr[3] << 16 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) bp->dev->dev_addr[4] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) bp->dev->dev_addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) bw32(bp, B44_ADDR_LO, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) val = bp->dev->dev_addr[0] << 8 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) bp->dev->dev_addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) bw32(bp, B44_ADDR_HI, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) val = br32(bp, B44_DEVCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) bw32(bp, B44_DEVCTRL, val | DEVCTRL_MPM | DEVCTRL_PFE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) b44_setup_pseudo_magicp(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) b44_setup_wol_pci(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) static int b44_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) phy_stop(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) napi_disable(&bp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) del_timer_sync(&bp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) b44_free_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (bp->flags & B44_FLAG_WOL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) b44_init_hw(bp, B44_PARTIAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) b44_setup_wol(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) b44_free_consistent(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static void b44_get_stats64(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) struct rtnl_link_stats64 *nstat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct b44_hw_stats *hwstat = &bp->hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) start = u64_stats_fetch_begin_irq(&hwstat->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) /* Convert HW stats into rtnl_link_stats64 stats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) nstat->rx_packets = hwstat->rx_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) nstat->tx_packets = hwstat->tx_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) nstat->rx_bytes = hwstat->rx_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) nstat->tx_bytes = hwstat->tx_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) nstat->tx_errors = (hwstat->tx_jabber_pkts +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) hwstat->tx_oversize_pkts +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) hwstat->tx_underruns +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) hwstat->tx_excessive_cols +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) hwstat->tx_late_cols);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) nstat->multicast = hwstat->rx_multicast_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) nstat->collisions = hwstat->tx_total_cols;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) hwstat->rx_undersize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) nstat->rx_over_errors = hwstat->rx_missed_pkts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) nstat->rx_frame_errors = hwstat->rx_align_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) nstat->rx_crc_errors = hwstat->rx_crc_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) nstat->rx_errors = (hwstat->rx_jabber_pkts +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) hwstat->rx_oversize_pkts +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) hwstat->rx_missed_pkts +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) hwstat->rx_crc_align_errs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) hwstat->rx_undersize +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) hwstat->rx_crc_errs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) hwstat->rx_align_errs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) hwstat->rx_symbol_errs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) nstat->tx_aborted_errors = hwstat->tx_underruns;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /* Carrier lost counter seems to be broken for some devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) nstat->tx_carrier_errors = hwstat->tx_carrier_lost;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) } while (u64_stats_fetch_retry_irq(&hwstat->syncp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) static int __b44_load_mcast(struct b44 *bp, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) int i, num_ents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) num_ents = min_t(int, netdev_mc_count(dev), B44_MCAST_TABLE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (i == num_ents)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) __b44_cam_write(bp, ha->addr, i++ + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) return i+1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) static void __b44_set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) val = br32(bp, B44_RXCONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) val &= ~(RXCONFIG_PROMISC | RXCONFIG_ALLMULTI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if ((dev->flags & IFF_PROMISC) || (val & RXCONFIG_CAM_ABSENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) val |= RXCONFIG_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) bw32(bp, B44_RXCONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) unsigned char zero[6] = {0, 0, 0, 0, 0, 0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) int i = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) __b44_set_mac_addr(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if ((dev->flags & IFF_ALLMULTI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) (netdev_mc_count(dev) > B44_MCAST_TABLE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) val |= RXCONFIG_ALLMULTI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) i = __b44_load_mcast(bp, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) for (; i < 64; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) __b44_cam_write(bp, zero, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) bw32(bp, B44_RXCONFIG, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) val = br32(bp, B44_CAM_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) bw32(bp, B44_CAM_CTRL, val | CAM_CTRL_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) static void b44_set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) __b44_set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) static u32 b44_get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) return bp->msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) static void b44_set_msglevel(struct net_device *dev, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) bp->msg_enable = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) static void b44_get_drvinfo (struct net_device *dev, struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) struct ssb_bus *bus = bp->sdev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) strlcpy(info->driver, DRV_MODULE_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) switch (bus->bustype) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) case SSB_BUSTYPE_PCI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) strlcpy(info->bus_info, pci_name(bus->host_pci), sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) case SSB_BUSTYPE_SSB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) strlcpy(info->bus_info, "SSB", sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) case SSB_BUSTYPE_PCMCIA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) case SSB_BUSTYPE_SDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) WARN_ON(1); /* A device with this bus does not exist. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) static int b44_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) u32 bmcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) int r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) b44_readphy(bp, MII_BMCR, &bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) b44_readphy(bp, MII_BMCR, &bmcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) r = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (bmcr & BMCR_ANENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) b44_writephy(bp, MII_BMCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) bmcr | BMCR_ANRESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) return r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) static int b44_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) u32 supported, advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) BUG_ON(!dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) phy_ethtool_ksettings_get(dev->phydev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) supported = (SUPPORTED_Autoneg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) supported |= (SUPPORTED_100baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) SUPPORTED_100baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) SUPPORTED_10baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) SUPPORTED_10baseT_Full |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) SUPPORTED_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) advertising = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (bp->flags & B44_FLAG_ADV_10HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) advertising |= ADVERTISED_10baseT_Half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) if (bp->flags & B44_FLAG_ADV_10FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) advertising |= ADVERTISED_10baseT_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (bp->flags & B44_FLAG_ADV_100HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) advertising |= ADVERTISED_100baseT_Half;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) if (bp->flags & B44_FLAG_ADV_100FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) advertising |= ADVERTISED_100baseT_Full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) advertising |= ADVERTISED_Pause | ADVERTISED_Asym_Pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) cmd->base.speed = (bp->flags & B44_FLAG_100_BASE_T) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) SPEED_100 : SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) cmd->base.duplex = (bp->flags & B44_FLAG_FULL_DUPLEX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) DUPLEX_FULL : DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) cmd->base.port = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) cmd->base.phy_address = bp->phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) cmd->base.autoneg = (bp->flags & B44_FLAG_FORCE_LINK) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) AUTONEG_DISABLE : AUTONEG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (cmd->base.autoneg == AUTONEG_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) advertising |= ADVERTISED_Autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) ethtool_convert_legacy_u32_to_link_mode(cmd->link_modes.advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) if (!netif_running(dev)){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) cmd->base.speed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) cmd->base.duplex = 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static int b44_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) u32 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) u32 advertising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) BUG_ON(!dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) b44_setup_phy(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) ret = phy_ethtool_ksettings_set(dev->phydev, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) speed = cmd->base.speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ethtool_convert_link_mode_to_legacy_u32(&advertising,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) cmd->link_modes.advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* We do not support gigabit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (cmd->base.autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) if (advertising &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) (ADVERTISED_1000baseT_Half |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ADVERTISED_1000baseT_Full))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) } else if ((speed != SPEED_100 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) speed != SPEED_10) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) (cmd->base.duplex != DUPLEX_HALF &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) cmd->base.duplex != DUPLEX_FULL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (cmd->base.autoneg == AUTONEG_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) bp->flags &= ~(B44_FLAG_FORCE_LINK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) B44_FLAG_100_BASE_T |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) B44_FLAG_FULL_DUPLEX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) B44_FLAG_ADV_10HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) B44_FLAG_ADV_10FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) B44_FLAG_ADV_100HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) B44_FLAG_ADV_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (advertising == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) bp->flags |= (B44_FLAG_ADV_10HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) B44_FLAG_ADV_10FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) B44_FLAG_ADV_100HALF |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) B44_FLAG_ADV_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) if (advertising & ADVERTISED_10baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) bp->flags |= B44_FLAG_ADV_10HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) if (advertising & ADVERTISED_10baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) bp->flags |= B44_FLAG_ADV_10FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (advertising & ADVERTISED_100baseT_Half)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) bp->flags |= B44_FLAG_ADV_100HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (advertising & ADVERTISED_100baseT_Full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) bp->flags |= B44_FLAG_ADV_100FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) bp->flags |= B44_FLAG_FORCE_LINK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) bp->flags &= ~(B44_FLAG_100_BASE_T | B44_FLAG_FULL_DUPLEX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) if (speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) bp->flags |= B44_FLAG_100_BASE_T;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) if (cmd->base.duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) bp->flags |= B44_FLAG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) if (netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) b44_setup_phy(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static void b44_get_ringparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct ethtool_ringparam *ering)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) ering->rx_max_pending = B44_RX_RING_SIZE - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) ering->rx_pending = bp->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* XXX ethtool lacks a tx_max_pending, oops... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) static int b44_set_ringparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) struct ethtool_ringparam *ering)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if ((ering->rx_pending > B44_RX_RING_SIZE - 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) (ering->rx_mini_pending != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) (ering->rx_jumbo_pending != 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) (ering->tx_pending > B44_TX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) bp->rx_pending = ering->rx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) bp->tx_pending = ering->tx_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) b44_init_hw(bp, B44_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) netif_wake_queue(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static void b44_get_pauseparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) struct ethtool_pauseparam *epause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) epause->autoneg =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) (bp->flags & B44_FLAG_PAUSE_AUTO) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) epause->rx_pause =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) (bp->flags & B44_FLAG_RX_PAUSE) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) epause->tx_pause =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) (bp->flags & B44_FLAG_TX_PAUSE) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) static int b44_set_pauseparam(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) struct ethtool_pauseparam *epause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (epause->autoneg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) bp->flags |= B44_FLAG_PAUSE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) bp->flags &= ~B44_FLAG_PAUSE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (epause->rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) bp->flags |= B44_FLAG_RX_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) bp->flags &= ~B44_FLAG_RX_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (epause->tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) bp->flags |= B44_FLAG_TX_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) bp->flags &= ~B44_FLAG_TX_PAUSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (bp->flags & B44_FLAG_PAUSE_AUTO) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) b44_init_hw(bp, B44_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) __b44_set_flow_ctrl(bp, bp->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static void b44_get_strings(struct net_device *dev, u32 stringset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) switch(stringset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) memcpy(data, *b44_gstrings, sizeof(b44_gstrings));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) static int b44_get_sset_count(struct net_device *dev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) switch (sset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return ARRAY_SIZE(b44_gstrings);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static void b44_get_ethtool_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) struct b44_hw_stats *hwstat = &bp->hw_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) u64 *data_src, *data_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) unsigned int start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) b44_stats_update(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) data_src = &hwstat->tx_good_octets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) data_dst = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) start = u64_stats_fetch_begin_irq(&hwstat->syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) for (i = 0; i < ARRAY_SIZE(b44_gstrings); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) *data_dst++ = *data_src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) } while (u64_stats_fetch_retry_irq(&hwstat->syncp, start));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) static void b44_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) wol->supported = WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (bp->flags & B44_FLAG_WOL_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) wol->wolopts = WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) memset(&wol->sopass, 0, sizeof(wol->sopass));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static int b44_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) if (wol->wolopts & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) bp->flags |= B44_FLAG_WOL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) bp->flags &= ~B44_FLAG_WOL_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) device_set_wakeup_enable(bp->sdev->dev, wol->wolopts & WAKE_MAGIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) static const struct ethtool_ops b44_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .get_drvinfo = b44_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .nway_reset = b44_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) .get_wol = b44_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) .set_wol = b44_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) .get_ringparam = b44_get_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) .set_ringparam = b44_set_ringparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) .get_pauseparam = b44_get_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) .set_pauseparam = b44_set_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) .get_msglevel = b44_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) .set_msglevel = b44_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) .get_strings = b44_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) .get_sset_count = b44_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) .get_ethtool_stats = b44_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) .get_link_ksettings = b44_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) .set_link_ksettings = b44_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) static int b44_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) int err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) BUG_ON(!dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) err = phy_mii_ioctl(dev->phydev, ifr, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) err = generic_mii_ioctl(&bp->mii_if, if_mii(ifr), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) static int b44_get_invariants(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) struct ssb_device *sdev = bp->sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) u8 *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) bp->dma_offset = ssb_dma_translation(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (sdev->bus->bustype == SSB_BUSTYPE_SSB &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) instance > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) addr = sdev->bus->sprom.et1mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) bp->phy_addr = sdev->bus->sprom.et1phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) addr = sdev->bus->sprom.et0mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) bp->phy_addr = sdev->bus->sprom.et0phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) /* Some ROMs have buggy PHY addresses with the high
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) * bits set (sign extension?). Truncate them to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) * valid PHY address. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) bp->phy_addr &= 0x1F;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) memcpy(bp->dev->dev_addr, addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) if (!is_valid_ether_addr(&bp->dev->dev_addr[0])){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) pr_err("Invalid MAC address found in EEPROM\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) bp->imask = IMASK_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) /* XXX - really required?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) bp->flags |= B44_FLAG_BUGGY_TXPTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) if (bp->sdev->id.revision >= 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) bp->flags |= B44_FLAG_B0_ANDLATER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) static const struct net_device_ops b44_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) .ndo_open = b44_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) .ndo_stop = b44_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) .ndo_start_xmit = b44_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) .ndo_get_stats64 = b44_get_stats64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) .ndo_set_rx_mode = b44_set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .ndo_set_mac_address = b44_set_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .ndo_do_ioctl = b44_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) .ndo_tx_timeout = b44_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .ndo_change_mtu = b44_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .ndo_poll_controller = b44_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static void b44_adjust_link(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) struct phy_device *phydev = dev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) bool status_changed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) BUG_ON(!phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) if (bp->old_link != phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) status_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) bp->old_link = phydev->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) /* reflect duplex change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) if ((phydev->duplex == DUPLEX_HALF) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) (bp->flags & B44_FLAG_FULL_DUPLEX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) status_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) bp->flags &= ~B44_FLAG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) } else if ((phydev->duplex == DUPLEX_FULL) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) !(bp->flags & B44_FLAG_FULL_DUPLEX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) status_changed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) bp->flags |= B44_FLAG_FULL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) if (status_changed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) u32 val = br32(bp, B44_TX_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) if (bp->flags & B44_FLAG_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) val |= TX_CTRL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) val &= ~TX_CTRL_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) bw32(bp, B44_TX_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) phy_print_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static int b44_register_phy_one(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct ssb_device *sdev = bp->sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) char bus_id[MII_BUS_ID_SIZE + 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) struct ssb_sprom *sprom = &sdev->bus->sprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) if (!mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) dev_err(sdev->dev, "mdiobus_alloc() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) mii_bus->priv = bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) mii_bus->read = b44_mdio_read_phylib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) mii_bus->write = b44_mdio_write_phylib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) mii_bus->name = "b44_eth_mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) mii_bus->parent = sdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) mii_bus->phy_mask = ~(1 << bp->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%x", instance);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) bp->mii_bus = mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) err = mdiobus_register(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) dev_err(sdev->dev, "failed to register MII bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) goto err_out_mdiobus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (!mdiobus_is_registered_device(bp->mii_bus, bp->phy_addr) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) (sprom->boardflags_lo & (B44_BOARDFLAG_ROBO | B44_BOARDFLAG_ADM))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) dev_info(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) "could not find PHY at %i, use fixed one\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) bp->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) bp->phy_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, "fixed-0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) bp->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) snprintf(bus_id, sizeof(bus_id), PHY_ID_FMT, mii_bus->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) bp->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) phydev = phy_connect(bp->dev, bus_id, &b44_adjust_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) PHY_INTERFACE_MODE_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) if (IS_ERR(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) dev_err(sdev->dev, "could not attach PHY at %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) bp->phy_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) err = PTR_ERR(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) goto err_out_mdiobus_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* mask with MAC supported features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) linkmode_and(phydev->supported, phydev->supported, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) linkmode_copy(phydev->advertising, phydev->supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) bp->old_link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) bp->phy_addr = phydev->mdio.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) phy_attached_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) err_out_mdiobus_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) mdiobus_unregister(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) err_out_mdiobus:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) mdiobus_free(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) static void b44_unregister_phy_one(struct b44 *bp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct net_device *dev = bp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) struct mii_bus *mii_bus = bp->mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) phy_disconnect(dev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) mdiobus_unregister(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) mdiobus_free(mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) static int b44_init_one(struct ssb_device *sdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) const struct ssb_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) struct b44 *bp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) instance++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) dev = alloc_etherdev(sizeof(*bp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) SET_NETDEV_DEV(dev, sdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) /* No interesting netdevice features in this card... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) dev->features |= 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) bp->sdev = sdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) bp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) bp->force_copybreak = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) bp->msg_enable = netif_msg_init(b44_debug, B44_DEF_MSG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) spin_lock_init(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) u64_stats_init(&bp->hw_stats.syncp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) bp->rx_pending = B44_DEF_RX_RING_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) bp->tx_pending = B44_DEF_TX_RING_PENDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) dev->netdev_ops = &b44_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) netif_napi_add(dev, &bp->napi, b44_poll, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) dev->watchdog_timeo = B44_TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) dev->min_mtu = B44_MIN_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) dev->max_mtu = B44_MAX_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) dev->irq = sdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) dev->ethtool_ops = &b44_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) err = ssb_bus_powerup(sdev->bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "Failed to powerup the bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) goto err_out_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) err = dma_set_mask_and_coherent(sdev->dma_dev, DMA_BIT_MASK(30));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) "Required 30BIT DMA mask unsupported by the system\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) goto err_out_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) err = b44_get_invariants(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) "Problem fetching invariants of chip, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) goto err_out_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) if (bp->phy_addr == B44_PHY_ADDR_NO_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) dev_err(sdev->dev, "No PHY present on this MAC, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) goto err_out_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) bp->mii_if.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) bp->mii_if.mdio_read = b44_mdio_read_mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) bp->mii_if.mdio_write = b44_mdio_write_mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) bp->mii_if.phy_id = bp->phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) bp->mii_if.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) bp->mii_if.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) /* By default, advertise all speed/duplex settings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) bp->flags |= (B44_FLAG_ADV_10HALF | B44_FLAG_ADV_10FULL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) B44_FLAG_ADV_100HALF | B44_FLAG_ADV_100FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) /* By default, auto-negotiate PAUSE. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) bp->flags |= B44_FLAG_PAUSE_AUTO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) dev_err(sdev->dev, "Cannot register net device, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) goto err_out_powerdown;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) ssb_set_drvdata(sdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* Chip reset provides power to the b44 MAC & PCI cores, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * is necessary for MAC register access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) b44_chip_reset(bp, B44_CHIP_RESET_FULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* do a phy reset to test if there is an active phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) err = b44_phy_reset(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) dev_err(sdev->dev, "phy reset failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) goto err_out_unregister_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) if (bp->flags & B44_FLAG_EXTERNAL_PHY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) err = b44_register_phy_one(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) dev_err(sdev->dev, "Cannot register PHY, aborting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) goto err_out_unregister_netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) device_set_wakeup_capable(sdev->dev, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) netdev_info(dev, "%s %pM\n", DRV_DESCRIPTION, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) err_out_unregister_netdev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) err_out_powerdown:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) ssb_bus_may_powerdown(sdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) err_out_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) netif_napi_del(&bp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) static void b44_remove_one(struct ssb_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) struct net_device *dev = ssb_get_drvdata(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) if (bp->flags & B44_FLAG_EXTERNAL_PHY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) b44_unregister_phy_one(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) ssb_device_disable(sdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) ssb_bus_may_powerdown(sdev->bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) netif_napi_del(&bp->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) ssb_pcihost_set_power_state(sdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) ssb_set_drvdata(sdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) static int b44_suspend(struct ssb_device *sdev, pm_message_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) struct net_device *dev = ssb_get_drvdata(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) del_timer_sync(&bp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) netif_carrier_off(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) netif_device_detach(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) b44_free_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) if (bp->flags & B44_FLAG_WOL_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) b44_init_hw(bp, B44_PARTIAL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) b44_setup_wol(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) ssb_pcihost_set_power_state(sdev, PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) static int b44_resume(struct ssb_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) struct net_device *dev = ssb_get_drvdata(sdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) struct b44 *bp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) int rc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) rc = ssb_bus_powerup(sdev->bus, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) dev_err(sdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) "Failed to powerup the bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) b44_init_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) b44_init_hw(bp, B44_FULL_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) * As a shared interrupt, the handler can be called immediately. To be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) * able to check the interrupt status the hardware must already be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) * powered back on (b44_init_hw).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) rc = request_irq(dev->irq, b44_interrupt, IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) netdev_err(dev, "request_irq failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) spin_lock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) b44_halt(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) b44_free_rings(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) spin_unlock_irq(&bp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) netif_device_attach(bp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) b44_enable_ints(bp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) mod_timer(&bp->timer, jiffies + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) static struct ssb_driver b44_ssb_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .name = DRV_MODULE_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .id_table = b44_ssb_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .probe = b44_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .remove = b44_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .suspend = b44_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) .resume = b44_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) static inline int __init b44_pci_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) #ifdef CONFIG_B44_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) err = ssb_pcihost_register(&b44_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) static inline void b44_pci_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) #ifdef CONFIG_B44_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) ssb_pcihost_unregister(&b44_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static int __init b44_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) unsigned int dma_desc_align_size = dma_get_cache_alignment();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) /* Setup paramaters for syncing RX/TX DMA descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) dma_desc_sync_size = max_t(unsigned int, dma_desc_align_size, sizeof(struct dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) err = b44_pci_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) err = ssb_driver_register(&b44_ssb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) b44_pci_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) static void __exit b44_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) ssb_driver_unregister(&b44_ssb_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) b44_pci_exit();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) module_init(b44_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) module_exit(b44_cleanup);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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