^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Atheros AR71xx built-in ethernet mac driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2019 Oleksij Rempel <o.rempel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * List of authors contributed to this driver before mainlining:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Alexander Couzens <lynxis@fe80.eu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Christian Lamparter <chunkeey@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Chuanhong Guo <gch981213@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Daniel F. Dickinson <cshored@thecshore.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * David Bauer <mail@david-bauer.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Felix Fietkau <nbd@nbd.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Gabor Juhos <juhosg@freemail.hu>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Hauke Mehrtens <hauke@hauke-m.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Johann Neuhauser <johann@it-neuhauser.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * John Crispin <john@phrozen.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Jo-Philipp Wich <jo@mein.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Koen Vandeputte <koen.vandeputte@ncentric.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Lucian Cristian <lucian.cristian@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Matt Merhar <mattmerhar@protonmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * Milan Krstic <milan.krstic@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Petr Štetiar <ynezz@true.cz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * Rosen Penev <rosenp@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * Stephen Walker <stephendwalker+github@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * Vittorio Gambaletta <openwrt@vittgam.net>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * Weijie Gao <hackpascal@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Imre Kaloz <kaloz@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/phylink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* For our NAPI weight bigger does *NOT* mean better - it means more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * D-cache misses and lots more wasted cycles than we'll ever
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * possibly gain from saving instructions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AG71XX_NAPI_WEIGHT 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AG71XX_OOM_REFILL (1 + HZ / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define AG71XX_TX_MTU_LEN 1540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AG71XX_TX_RING_SPLIT 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AG71XX_TX_RING_DS_PER_PKT DIV_ROUND_UP(AG71XX_TX_MTU_LEN, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) AG71XX_TX_RING_SPLIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AG71XX_TX_RING_SIZE_DEFAULT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AG71XX_RX_RING_SIZE_DEFAULT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AG71XX_MDIO_RETRY 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define AG71XX_MDIO_DELAY 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define AG71XX_MDIO_MAX_CLK 5000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AG71XX_REG_MAC_CFG1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MAC_CFG1_SR BIT(31) /* Soft Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MAC_CFG1_SRX | MAC_CFG1_STX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define AG71XX_REG_MAC_CFG2 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MAC_CFG2_FDX BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MAC_CFG2_PAD_CRC_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MAC_CFG2_LEN_CHECK BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MAC_CFG2_IF_1000 BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MAC_CFG2_IF_10_100 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define AG71XX_REG_MAC_MFL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define AG71XX_REG_MII_CFG 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MII_CFG_CLK_DIV_4 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MII_CFG_CLK_DIV_6 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MII_CFG_CLK_DIV_8 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MII_CFG_CLK_DIV_10 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MII_CFG_CLK_DIV_14 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MII_CFG_CLK_DIV_20 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MII_CFG_CLK_DIV_28 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define MII_CFG_CLK_DIV_34 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MII_CFG_CLK_DIV_42 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MII_CFG_CLK_DIV_50 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MII_CFG_CLK_DIV_58 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MII_CFG_CLK_DIV_66 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MII_CFG_CLK_DIV_74 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MII_CFG_CLK_DIV_82 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MII_CFG_CLK_DIV_98 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MII_CFG_RESET BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define AG71XX_REG_MII_CMD 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MII_CMD_READ BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define AG71XX_REG_MII_ADDR 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MII_ADDR_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define AG71XX_REG_MII_CTRL 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define AG71XX_REG_MII_STATUS 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AG71XX_REG_MII_IND 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MII_IND_BUSY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MII_IND_INVALID BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define AG71XX_REG_MAC_IFCTL 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MAC_IFCTL_SPEED BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define AG71XX_REG_MAC_ADDR1 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define AG71XX_REG_MAC_ADDR2 0x0044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define AG71XX_REG_FIFO_CFG0 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define FIFO_CFG0_INIT (FIFO_CFG0_ALL << FIFO_CFG0_ENABLE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define FIFO_CFG0_ENABLE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define AG71XX_REG_FIFO_CFG1 0x004c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define AG71XX_REG_FIFO_CFG2 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define AG71XX_REG_FIFO_CFG3 0x0054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AG71XX_REG_FIFO_CFG4 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define FIFO_CFG4_DE BIT(0) /* Drop Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FIFO_CFG4_FC BIT(2) /* False Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FIFO_CFG4_CE BIT(3) /* Code Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FIFO_CFG4_CR BIT(4) /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FIFO_CFG4_LO BIT(6) /* Length out of range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define FIFO_CFG4_DR BIT(10) /* Dribble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define FIFO_CFG4_LE BIT(11) /* Long Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define FIFO_CFG4_CF BIT(12) /* Control Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) FIFO_CFG4_CE | FIFO_CFG4_CR | FIFO_CFG4_LM | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) FIFO_CFG4_LO | FIFO_CFG4_OK | FIFO_CFG4_MC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) FIFO_CFG4_BC | FIFO_CFG4_DR | FIFO_CFG4_LE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) FIFO_CFG4_CF | FIFO_CFG4_PF | FIFO_CFG4_UO | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) FIFO_CFG4_VT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define AG71XX_REG_FIFO_CFG5 0x005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define FIFO_CFG5_DE BIT(0) /* Drop Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define FIFO_CFG5_FC BIT(2) /* False Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FIFO_CFG5_CE BIT(3) /* Code Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define FIFO_CFG5_DR BIT(9) /* Dribble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define FIFO_CFG5_CF BIT(10) /* Control Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FIFO_CFG5_LE BIT(14) /* Long Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FIFO_CFG5_16 BIT(16) /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FIFO_CFG5_17 BIT(17) /* unknown */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FIFO_CFG5_SF BIT(18) /* Short Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) FIFO_CFG5_17 | FIFO_CFG5_SF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AG71XX_REG_TX_CTRL 0x0180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TX_CTRL_TXE BIT(0) /* Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define AG71XX_REG_TX_DESC 0x0184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AG71XX_REG_TX_STATUS 0x0188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TX_STATUS_PS BIT(0) /* Packet Sent */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TX_STATUS_UR BIT(1) /* Tx Underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TX_STATUS_BE BIT(3) /* Bus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AG71XX_REG_RX_CTRL 0x018c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RX_CTRL_RXE BIT(0) /* Rx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AG71XX_DMA_RETRY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AG71XX_DMA_DELAY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AG71XX_REG_RX_DESC 0x0190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AG71XX_REG_RX_STATUS 0x0194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define RX_STATUS_PR BIT(0) /* Packet Received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define RX_STATUS_OF BIT(2) /* Rx Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define RX_STATUS_BE BIT(3) /* Bus Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AG71XX_REG_INT_ENABLE 0x0198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AG71XX_REG_INT_STATUS 0x019c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AG71XX_INT_TX_PS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AG71XX_INT_TX_UR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AG71XX_INT_TX_BE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AG71XX_INT_RX_PR BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AG71XX_INT_RX_OF BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AG71XX_INT_RX_BE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AG71XX_REG_FIFO_DEPTH 0x01a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AG71XX_REG_RX_SM 0x01b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define AG71XX_REG_TX_SM 0x01b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AG71XX_DEFAULT_MSG_ENABLE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) (NETIF_MSG_DRV \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) | NETIF_MSG_PROBE \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) | NETIF_MSG_LINK \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) | NETIF_MSG_TIMER \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) | NETIF_MSG_IFDOWN \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) | NETIF_MSG_IFUP \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) | NETIF_MSG_RX_ERR \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) | NETIF_MSG_TX_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct ag71xx_statistic {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) unsigned short offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) const char name[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const struct ag71xx_statistic ag71xx_statistics[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) { 0x0080, GENMASK(17, 0), "Tx/Rx 64 Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) { 0x0084, GENMASK(17, 0), "Tx/Rx 65-127 Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) { 0x0088, GENMASK(17, 0), "Tx/Rx 128-255 Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) { 0x008C, GENMASK(17, 0), "Tx/Rx 256-511 Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) { 0x0090, GENMASK(17, 0), "Tx/Rx 512-1023 Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) { 0x0094, GENMASK(17, 0), "Tx/Rx 1024-1518 Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) { 0x0098, GENMASK(17, 0), "Tx/Rx 1519-1522 Byte VLAN", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) { 0x009C, GENMASK(23, 0), "Rx Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) { 0x00A0, GENMASK(17, 0), "Rx Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) { 0x00A4, GENMASK(11, 0), "Rx FCS Error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) { 0x00A8, GENMASK(17, 0), "Rx Multicast Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) { 0x00AC, GENMASK(21, 0), "Rx Broadcast Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) { 0x00B0, GENMASK(17, 0), "Rx Control Frame Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) { 0x00B4, GENMASK(11, 0), "Rx Pause Frame Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) { 0x00B8, GENMASK(11, 0), "Rx Unknown OPCode Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { 0x00BC, GENMASK(11, 0), "Rx Alignment Error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { 0x00C0, GENMASK(15, 0), "Rx Frame Length Error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { 0x00C4, GENMASK(11, 0), "Rx Code Error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { 0x00C8, GENMASK(11, 0), "Rx Carrier Sense Error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) { 0x00CC, GENMASK(11, 0), "Rx Undersize Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) { 0x00D0, GENMASK(11, 0), "Rx Oversize Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) { 0x00D4, GENMASK(11, 0), "Rx Fragments", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) { 0x00D8, GENMASK(11, 0), "Rx Jabber", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) { 0x00DC, GENMASK(11, 0), "Rx Dropped Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) { 0x00E0, GENMASK(23, 0), "Tx Byte", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) { 0x00E4, GENMASK(17, 0), "Tx Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) { 0x00E8, GENMASK(17, 0), "Tx Multicast Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) { 0x00EC, GENMASK(17, 0), "Tx Broadcast Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) { 0x00F0, GENMASK(11, 0), "Tx Pause Control Frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) { 0x00F4, GENMASK(11, 0), "Tx Deferral Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) { 0x00F8, GENMASK(11, 0), "Tx Excessive Deferral Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) { 0x00FC, GENMASK(11, 0), "Tx Single Collision Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) { 0x0100, GENMASK(11, 0), "Tx Multiple Collision", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) { 0x0104, GENMASK(11, 0), "Tx Late Collision Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) { 0x0108, GENMASK(11, 0), "Tx Excessive Collision Packet", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) { 0x010C, GENMASK(12, 0), "Tx Total Collision", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) { 0x0110, GENMASK(11, 0), "Tx Pause Frames Honored", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) { 0x0114, GENMASK(11, 0), "Tx Drop Frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) { 0x0118, GENMASK(11, 0), "Tx Jabber Frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) { 0x011C, GENMASK(11, 0), "Tx FCS Error", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) { 0x0120, GENMASK(11, 0), "Tx Control Frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) { 0x0124, GENMASK(11, 0), "Tx Oversize Frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) { 0x0128, GENMASK(11, 0), "Tx Undersize Frame", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) { 0x012C, GENMASK(11, 0), "Tx Fragment", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define DESC_EMPTY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define DESC_MORE BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define DESC_PKTLEN_M 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct ag71xx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } __aligned(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define AG71XX_DESC_SIZE roundup(sizeof(struct ag71xx_desc), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) L1_CACHE_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct ag71xx_buf {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) void *rx_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) } rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct ag71xx_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* "Hot" fields in the data path. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned int curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) unsigned int dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* "Cold" fields - not used in the data path. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ag71xx_buf *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 desc_split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dma_addr_t descs_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 *descs_cpu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) enum ag71xx_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) AR7100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) AR7240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) AR9130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) AR9330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) AR9340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) QCA9530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) QCA9550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) struct ag71xx_dcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 max_frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) const u32 *fifodata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u16 desc_pktlen_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bool tx_hang_workaround;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum ag71xx_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct ag71xx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* Critical data related to the per-packet data path are clustered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * early in this structure to help improve the D-cache footprint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct ag71xx_ring rx_ring ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct ag71xx_ring tx_ring ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u16 rx_buf_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 rx_buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct platform_device *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) const struct ag71xx_dcfg *dcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* From this point onwards we're not looking at per-packet fields. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) void __iomem *mac_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct ag71xx_desc *stop_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dma_addr_t stop_desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) phy_interface_t phy_if_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct phylink *phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) struct phylink_config phylink_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct delayed_work restart_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct timer_list oom_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct reset_control *mac_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 fifodata[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int mac_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct reset_control *mdio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct clk *clk_mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct clk *clk_eth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static int ag71xx_desc_empty(struct ag71xx_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return (desc->ctrl & DESC_EMPTY) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static struct ag71xx_desc *ag71xx_ring_desc(struct ag71xx_ring *ring, int idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return (struct ag71xx_desc *)&ring->descs_cpu[idx * AG71XX_DESC_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static int ag71xx_ring_size_order(int size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return fls(size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static bool ag71xx_is(struct ag71xx *ag, enum ag71xx_type type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return ag->dcfg->type == type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static void ag71xx_wr(struct ag71xx *ag, unsigned int reg, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) iowrite32(value, ag->mac_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) (void)ioread32(ag->mac_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static u32 ag71xx_rr(struct ag71xx *ag, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return ioread32(ag->mac_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void ag71xx_sb(struct ag71xx *ag, unsigned int reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) void __iomem *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) r = ag->mac_base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) iowrite32(ioread32(r) | mask, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) (void)ioread32(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static void ag71xx_cb(struct ag71xx *ag, unsigned int reg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void __iomem *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) r = ag->mac_base + reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) iowrite32(ioread32(r) & ~mask, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /* flush write */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) (void)ioread32(r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) static void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) static void ag71xx_get_drvinfo(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) strlcpy(info->driver, "ag71xx", sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) strlcpy(info->bus_info, of_node_full_name(ag->pdev->dev.of_node),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int ag71xx_get_link_ksettings(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct ethtool_link_ksettings *kset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return phylink_ethtool_ksettings_get(ag->phylink, kset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) static int ag71xx_set_link_ksettings(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) const struct ethtool_link_ksettings *kset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return phylink_ethtool_ksettings_set(ag->phylink, kset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int ag71xx_ethtool_nway_reset(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return phylink_ethtool_nway_reset(ag->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) static void ag71xx_ethtool_get_pauseparam(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) struct ethtool_pauseparam *pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) phylink_ethtool_get_pauseparam(ag->phylink, pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static int ag71xx_ethtool_set_pauseparam(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct ethtool_pauseparam *pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return phylink_ethtool_set_pauseparam(ag->phylink, pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (sset == ETH_SS_STATS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) memcpy(data + i * ETH_GSTRING_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ag71xx_statistics[i].name, ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static void ag71xx_ethtool_get_stats(struct net_device *ndev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) *data++ = ag71xx_rr(ag, ag71xx_statistics[i].offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) & ag71xx_statistics[i].mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) static int ag71xx_ethtool_get_sset_count(struct net_device *ndev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (sset == ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return ARRAY_SIZE(ag71xx_statistics);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static const struct ethtool_ops ag71xx_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .get_drvinfo = ag71xx_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .get_ts_info = ethtool_op_get_ts_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .get_link_ksettings = ag71xx_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .set_link_ksettings = ag71xx_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .nway_reset = ag71xx_ethtool_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .get_pauseparam = ag71xx_ethtool_get_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .set_pauseparam = ag71xx_ethtool_set_pauseparam,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .get_strings = ag71xx_ethtool_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .get_ethtool_stats = ag71xx_ethtool_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .get_sset_count = ag71xx_ethtool_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) static int ag71xx_mdio_wait_busy(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) for (i = 0; i < AG71XX_MDIO_RETRY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) udelay(AG71XX_MDIO_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) busy = ag71xx_rr(ag, AG71XX_REG_MII_IND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) if (!busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) udelay(AG71XX_MDIO_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) netif_err(ag, link, ndev, "MDIO operation timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) static int ag71xx_mdio_mii_read(struct mii_bus *bus, int addr, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct ag71xx *ag = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) int err, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err = ag71xx_mdio_wait_busy(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* enable read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) ag71xx_wr(ag, AG71XX_REG_MII_CMD, MII_CMD_READ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) err = ag71xx_mdio_wait_busy(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) val = ag71xx_rr(ag, AG71XX_REG_MII_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* disable read mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) ag71xx_wr(ag, AG71XX_REG_MII_CMD, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) netif_dbg(ag, link, ag->ndev, "mii_read: addr=%04x, reg=%04x, value=%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static int ag71xx_mdio_mii_write(struct mii_bus *bus, int addr, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct ag71xx *ag = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) netif_dbg(ag, link, ag->ndev, "mii_write: addr=%04x, reg=%04x, value=%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ag71xx_wr(ag, AG71XX_REG_MII_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) ((addr & 0x1f) << MII_ADDR_SHIFT) | (reg & 0xff));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ag71xx_wr(ag, AG71XX_REG_MII_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return ag71xx_mdio_wait_busy(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static const u32 ar71xx_mdio_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) 4, 4, 6, 8, 10, 14, 20, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static const u32 ar7240_mdio_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 2, 2, 4, 6, 8, 12, 18, 26, 32, 40, 48, 56, 62, 70, 78, 96,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) static const u32 ar933x_mdio_div_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 4, 4, 6, 8, 10, 14, 20, 28, 34, 42, 50, 58, 66, 74, 82, 98,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) static int ag71xx_mdio_get_divider(struct ag71xx *ag, u32 *div)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned long ref_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) const u32 *table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int ndivs, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ref_clock = clk_get_rate(ag->clk_mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) if (!ref_clock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (ag71xx_is(ag, AR9330) || ag71xx_is(ag, AR9340)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) table = ar933x_mdio_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ndivs = ARRAY_SIZE(ar933x_mdio_div_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) } else if (ag71xx_is(ag, AR7240)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) table = ar7240_mdio_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ndivs = ARRAY_SIZE(ar7240_mdio_div_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) table = ar71xx_mdio_div_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) ndivs = ARRAY_SIZE(ar71xx_mdio_div_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) for (i = 0; i < ndivs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned long t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) t = ref_clock / table[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (t <= AG71XX_MDIO_MAX_CLK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) *div = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int ag71xx_mdio_reset(struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) struct ag71xx *ag = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) err = ag71xx_mdio_get_divider(ag, &t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ag71xx_wr(ag, AG71XX_REG_MII_CFG, t | MII_CFG_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ag71xx_wr(ag, AG71XX_REG_MII_CFG, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) usleep_range(100, 200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static int ag71xx_mdio_probe(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct device *dev = &ag->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct device_node *np, *mnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) ag->mii_bus = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) ag->clk_mdio = devm_clk_get(dev, "mdio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (IS_ERR(ag->clk_mdio)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) netif_err(ag, probe, ndev, "Failed to get mdio clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return PTR_ERR(ag->clk_mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) err = clk_prepare_enable(ag->clk_mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) netif_err(ag, probe, ndev, "Failed to enable mdio clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) mii_bus = devm_mdiobus_alloc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) goto mdio_err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if (IS_ERR(ag->mdio_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) netif_err(ag, probe, ndev, "Failed to get reset mdio.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) err = PTR_ERR(ag->mdio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) goto mdio_err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) mii_bus->name = "ag71xx_mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mii_bus->read = ag71xx_mdio_mii_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) mii_bus->write = ag71xx_mdio_mii_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) mii_bus->reset = ag71xx_mdio_reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mii_bus->priv = ag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) mii_bus->parent = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (!IS_ERR(ag->mdio_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) reset_control_assert(ag->mdio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) reset_control_deassert(ag->mdio_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) mnp = of_get_child_by_name(np, "mdio");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) err = of_mdiobus_register(mii_bus, mnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) of_node_put(mnp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) goto mdio_err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ag->mii_bus = mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) mdio_err_put_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) clk_disable_unprepare(ag->clk_mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void ag71xx_mdio_remove(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) if (ag->mii_bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) mdiobus_unregister(ag->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) clk_disable_unprepare(ag->clk_mdio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) static void ag71xx_hw_stop(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* disable all interrupts and stop the rx/tx engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static bool ag71xx_check_dma_stuck(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) unsigned long timestamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) u32 rx_sm, tx_sm, rx_fd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) timestamp = netdev_get_tx_queue(ag->ndev, 0)->trans_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (likely(time_before(jiffies, timestamp + HZ / 10)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (!netif_carrier_ok(ag->ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rx_sm = ag71xx_rr(ag, AG71XX_REG_RX_SM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if ((rx_sm & 0x7) == 0x3 && ((rx_sm >> 4) & 0x7) == 0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) tx_sm = ag71xx_rr(ag, AG71XX_REG_TX_SM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) rx_fd = ag71xx_rr(ag, AG71XX_REG_FIFO_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (((tx_sm >> 4) & 0x7) == 0 && ((rx_sm & 0x7) == 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) ((rx_sm >> 4) & 0x7) == 0 && rx_fd == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int ag71xx_tx_packets(struct ag71xx *ag, bool flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct ag71xx_ring *ring = &ag->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) int sent = 0, bytes_compl = 0, n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) int ring_mask, ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) bool dma_stuck = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) ring_size = BIT(ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) netif_dbg(ag, tx_queued, ndev, "processing TX ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) while (ring->dirty + n != ring->curr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct ag71xx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) i = (ring->dirty + n) & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) skb = ring->buf[i].tx.skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (!flush && !ag71xx_desc_empty(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) if (ag->dcfg->tx_hang_workaround &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ag71xx_check_dma_stuck(ag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) schedule_delayed_work(&ag->restart_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) HZ / 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) dma_stuck = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (flush)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) desc->ctrl |= DESC_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ring->buf[i].tx.skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) bytes_compl += ring->buf[i].tx.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) sent++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ring->dirty += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) while (n > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) n--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) netif_dbg(ag, tx_done, ndev, "%d packets sent out\n", sent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (!sent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) ag->ndev->stats.tx_bytes += bytes_compl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) ag->ndev->stats.tx_packets += sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) netdev_completed_queue(ag->ndev, sent, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if ((ring->curr - ring->dirty) < (ring_size * 3) / 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) netif_wake_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (!dma_stuck)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) cancel_delayed_work(&ag->restart_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return sent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void ag71xx_dma_wait_stop(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) for (i = 0; i < AG71XX_DMA_RETRY; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u32 rx, tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) mdelay(AG71XX_DMA_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) rx = ag71xx_rr(ag, AG71XX_REG_RX_CTRL) & RX_CTRL_RXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) tx = ag71xx_rr(ag, AG71XX_REG_TX_CTRL) & TX_CTRL_TXE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) if (!rx && !tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) netif_err(ag, hw, ndev, "DMA stop operation timed out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static void ag71xx_dma_reset(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* stop RX and TX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) /* give the hardware some time to really stop all rx/tx activity
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * clearing the descriptors too early causes random memory corruption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) ag71xx_dma_wait_stop(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /* clear descriptor addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->stop_desc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->stop_desc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /* clear pending RX/TX interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) for (i = 0; i < 256; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /* clear pending errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE | RX_STATUS_OF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE | TX_STATUS_UR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) val = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) netif_err(ag, hw, ndev, "unable to clear DMA Rx status: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) val = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) /* mask out reserved bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) val &= ~0xff000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) netif_err(ag, hw, ndev, "unable to clear DMA Tx status: %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static void ag71xx_hw_setup(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) u32 init = MAC_CFG1_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) /* setup MAC configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* setup max frame length to zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) ag71xx_wr(ag, AG71XX_REG_MAC_MFL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* setup FIFO configuration registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, FIFO_CFG0_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, ag->fifodata[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, ag->fifodata[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, FIFO_CFG4_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, FIFO_CFG5_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static unsigned int ag71xx_max_frame_len(unsigned int mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return ETH_HLEN + VLAN_HLEN + mtu + ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) u32 t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) t = (((u32)mac[5]) << 24) | (((u32)mac[4]) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) | (((u32)mac[3]) << 8) | ((u32)mac[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) t = (((u32)mac[1]) << 24) | (((u32)mac[0]) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static void ag71xx_fast_reset(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) struct net_device *dev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) u32 rx_ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) u32 mii_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) ag71xx_hw_stop(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mii_reg = ag71xx_rr(ag, AG71XX_REG_MII_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) rx_ds = ag71xx_rr(ag, AG71XX_REG_RX_DESC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) ag71xx_tx_packets(ag, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) reset_control_assert(ag->mac_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) reset_control_deassert(ag->mac_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ag71xx_dma_reset(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ag71xx_hw_setup(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) ag->tx_ring.curr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) ag->tx_ring.dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) netdev_reset_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /* setup max frame length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) ag71xx_max_frame_len(ag->ndev->mtu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ag71xx_wr(ag, AG71XX_REG_RX_DESC, rx_ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) ag71xx_wr(ag, AG71XX_REG_MII_CFG, mii_reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ag71xx_hw_set_macaddr(ag, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static void ag71xx_hw_start(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) /* start RX engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) netif_wake_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static void ag71xx_mac_config(struct phylink_config *config, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if (phylink_autoneg_inband(mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ag71xx_fast_reset(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) if (ag->tx_ring.desc_split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ag->fifodata[2] &= 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ag->fifodata[2] |= ((2048 - ag->tx_ring.desc_split) / 4) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG3, ag->fifodata[2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) static void ag71xx_mac_validate(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) unsigned long *supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) switch (state->interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) case PHY_INTERFACE_MODE_NA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case PHY_INTERFACE_MODE_MII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) ag71xx_is(ag, AR9340) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ag71xx_is(ag, QCA9530) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case PHY_INTERFACE_MODE_GMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) (ag71xx_is(ag, AR9340) && ag->mac_idx == 1) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) (ag71xx_is(ag, QCA9530) && ag->mac_idx == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ag71xx_is(ag, QCA9550) && ag->mac_idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) case PHY_INTERFACE_MODE_RMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ag71xx_is(ag, AR9340) && ag->mac_idx == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) if ((ag71xx_is(ag, AR9340) && ag->mac_idx == 0) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) (ag71xx_is(ag, QCA9550) && ag->mac_idx == 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) phylink_set(mask, MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) phylink_set(mask, Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) phylink_set(mask, Asym_Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) phylink_set(mask, Autoneg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) phylink_set(mask, 10baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) phylink_set(mask, 10baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) phylink_set(mask, 100baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) phylink_set(mask, 100baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (state->interface == PHY_INTERFACE_MODE_NA ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) state->interface == PHY_INTERFACE_MODE_SGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) state->interface == PHY_INTERFACE_MODE_RGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) state->interface == PHY_INTERFACE_MODE_GMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) phylink_set(mask, 1000baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) phylink_set(mask, 1000baseX_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) bitmap_and(supported, supported, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) bitmap_and(state->advertising, state->advertising, mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) unsupported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) static void ag71xx_mac_pcs_get_state(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) state->link = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static void ag71xx_mac_an_restart(struct phylink_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* Not Supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) static void ag71xx_mac_link_down(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) unsigned int mode, phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) ag71xx_hw_stop(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) static void ag71xx_mac_link_up(struct phylink_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct phy_device *phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) unsigned int mode, phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) int speed, int duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) bool tx_pause, bool rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct ag71xx *ag = netdev_priv(to_net_dev(config->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) u32 cfg1, cfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) u32 ifctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u32 fifo5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) cfg2 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) cfg2 &= ~(MAC_CFG2_IF_1000 | MAC_CFG2_IF_10_100 | MAC_CFG2_FDX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) cfg2 |= duplex ? MAC_CFG2_FDX : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) ifctl = ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ifctl &= ~(MAC_IFCTL_SPEED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) fifo5 = ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) fifo5 &= ~FIFO_CFG5_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) cfg2 |= MAC_CFG2_IF_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) fifo5 |= FIFO_CFG5_BM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) cfg2 |= MAC_CFG2_IF_10_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) ifctl |= MAC_IFCTL_SPEED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) cfg2 |= MAC_CFG2_IF_10_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) ag71xx_wr(ag, AG71XX_REG_MAC_CFG2, cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, fifo5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) ag71xx_wr(ag, AG71XX_REG_MAC_IFCTL, ifctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) cfg1 = ag71xx_rr(ag, AG71XX_REG_MAC_CFG1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) cfg1 &= ~(MAC_CFG1_TFC | MAC_CFG1_RFC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cfg1 |= MAC_CFG1_TFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) cfg1 |= MAC_CFG1_RFC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) ag71xx_hw_start(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) static const struct phylink_mac_ops ag71xx_phylink_mac_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) .validate = ag71xx_mac_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) .mac_pcs_get_state = ag71xx_mac_pcs_get_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) .mac_an_restart = ag71xx_mac_an_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .mac_config = ag71xx_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .mac_link_down = ag71xx_mac_link_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .mac_link_up = ag71xx_mac_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) static int ag71xx_phylink_setup(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) struct phylink *phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) ag->phylink_config.dev = &ag->ndev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) ag->phylink_config.type = PHYLINK_NETDEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) phylink = phylink_create(&ag->phylink_config, ag->pdev->dev.fwnode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ag->phy_if_mode, &ag71xx_phylink_mac_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (IS_ERR(phylink))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) return PTR_ERR(phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) ag->phylink = phylink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static void ag71xx_ring_tx_clean(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct ag71xx_ring *ring = &ag->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) int ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u32 bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) while (ring->curr != ring->dirty) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct ag71xx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) u32 i = ring->dirty & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (!ag71xx_desc_empty(desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) desc->ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) ndev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (ring->buf[i].tx.skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) bytes_compl += ring->buf[i].tx.len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) dev_kfree_skb_any(ring->buf[i].tx.skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) ring->buf[i].tx.skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) ring->dirty++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) /* flush descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) netdev_completed_queue(ndev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static void ag71xx_ring_tx_init(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) struct ag71xx_ring *ring = &ag->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) int ring_size = BIT(ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) int ring_mask = ring_size - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) for (i = 0; i < ring_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) desc->next = (u32)(ring->descs_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) desc->ctrl = DESC_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ring->buf[i].tx.skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) /* flush descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ring->curr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) ring->dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) netdev_reset_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) static void ag71xx_ring_rx_clean(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct ag71xx_ring *ring = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) int ring_size = BIT(ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (!ring->buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) for (i = 0; i < ring_size; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (ring->buf[i].rx.rx_buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dma_unmap_single(&ag->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ring->buf[i].rx.dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) ag->rx_buf_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) skb_free_frag(ring->buf[i].rx.rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) static int ag71xx_buffer_size(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return ag->rx_buf_size +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) static bool ag71xx_fill_rx_buf(struct ag71xx *ag, struct ag71xx_buf *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) void *(*alloc)(unsigned int size))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct ag71xx_ring *ring = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct ag71xx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) desc = ag71xx_ring_desc(ring, buf - &ring->buf[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) data = alloc(ag71xx_buffer_size(ag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (!data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) buf->rx.rx_buf = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) buf->rx.dma_addr = dma_map_single(&ag->pdev->dev, data, ag->rx_buf_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) desc->data = (u32)buf->rx.dma_addr + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) static int ag71xx_ring_rx_init(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct ag71xx_ring *ring = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) int ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int ring_size = BIT(ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) for (i = 0; i < ring_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) desc->next = (u32)(ring->descs_dma +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) AG71XX_DESC_SIZE * ((i + 1) & ring_mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) netif_dbg(ag, rx_status, ndev, "RX desc at %p, next is %08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) desc, desc->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) for (i = 0; i < ring_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (!ag71xx_fill_rx_buf(ag, &ring->buf[i], ag->rx_buf_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) netdev_alloc_frag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) desc->ctrl = DESC_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) /* flush descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) ring->curr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) ring->dirty = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) static int ag71xx_ring_rx_refill(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct ag71xx_ring *ring = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) int ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) int offset = ag->rx_buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) unsigned int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) for (; ring->curr - ring->dirty > 0; ring->dirty++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) struct ag71xx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) i = ring->dirty & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) if (!ring->buf[i].rx.rx_buf &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) !ag71xx_fill_rx_buf(ag, &ring->buf[i], offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) napi_alloc_frag))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) desc->ctrl = DESC_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) /* flush descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) netif_dbg(ag, rx_status, ag->ndev, "%u rx descriptors refilled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) static int ag71xx_rings_init(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) struct ag71xx_ring *tx = &ag->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) struct ag71xx_ring *rx = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) int ring_size, tx_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) ring_size = BIT(tx->order) + BIT(rx->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) tx_size = BIT(tx->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) tx->buf = kcalloc(ring_size, sizeof(*tx->buf), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (!tx->buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) tx->descs_cpu = dma_alloc_coherent(&ag->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) ring_size * AG71XX_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) &tx->descs_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (!tx->descs_cpu) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) kfree(tx->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) tx->buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) rx->buf = &tx->buf[tx_size];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) rx->descs_cpu = ((void *)tx->descs_cpu) + tx_size * AG71XX_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) rx->descs_dma = tx->descs_dma + tx_size * AG71XX_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) ag71xx_ring_tx_init(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return ag71xx_ring_rx_init(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static void ag71xx_rings_free(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) struct ag71xx_ring *tx = &ag->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) struct ag71xx_ring *rx = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) int ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) ring_size = BIT(tx->order) + BIT(rx->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (tx->descs_cpu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) dma_free_coherent(&ag->pdev->dev, ring_size * AG71XX_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) tx->descs_cpu, tx->descs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) kfree(tx->buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) tx->descs_cpu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) rx->descs_cpu = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) tx->buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) rx->buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) static void ag71xx_rings_cleanup(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) ag71xx_ring_rx_clean(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) ag71xx_ring_tx_clean(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) ag71xx_rings_free(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) netdev_reset_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) static void ag71xx_hw_init(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) ag71xx_hw_stop(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) usleep_range(20, 30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) reset_control_assert(ag->mac_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) msleep(100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) reset_control_deassert(ag->mac_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) msleep(200);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ag71xx_hw_setup(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) ag71xx_dma_reset(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static int ag71xx_hw_enable(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) ret = ag71xx_rings_init(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) napi_enable(&ag->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) netif_start_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static void ag71xx_hw_disable(struct ag71xx *ag)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) netif_stop_queue(ag->ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) ag71xx_hw_stop(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ag71xx_dma_reset(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) napi_disable(&ag->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) del_timer_sync(&ag->oom_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) ag71xx_rings_cleanup(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) static int ag71xx_open(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) unsigned int max_frame_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) ret = phylink_of_phy_connect(ag->phylink, ag->pdev->dev.of_node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) netif_err(ag, link, ndev, "phylink_of_phy_connect filed with err: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) max_frame_len = ag71xx_max_frame_len(ndev->mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ag->rx_buf_size =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) SKB_DATA_ALIGN(max_frame_len + NET_SKB_PAD + NET_IP_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* setup max frame length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) ag71xx_wr(ag, AG71XX_REG_MAC_MFL, max_frame_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) ag71xx_hw_set_macaddr(ag, ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) ret = ag71xx_hw_enable(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) phylink_start(ag->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) ag71xx_rings_cleanup(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static int ag71xx_stop(struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) phylink_stop(ag->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) phylink_disconnect_phy(ag->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) ag71xx_hw_disable(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) static int ag71xx_fill_dma_desc(struct ag71xx_ring *ring, u32 addr, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) int i, ring_mask, ndesc, split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) struct ag71xx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) ndesc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) split = ring->desc_split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) if (!split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) split = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) unsigned int cur_len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) i = (ring->curr + ndesc) & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (!ag71xx_desc_empty(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) if (cur_len > split) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) cur_len = split;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) /* TX will hang if DMA transfers <= 4 bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) * make sure next segment is more than 4 bytes long.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (len <= split + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) cur_len -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) desc->data = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) addr += cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) len -= cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) if (len > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) cur_len |= DESC_MORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) /* prevent early tx attempt of this descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) if (!ndesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) cur_len |= DESC_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) desc->ctrl = cur_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) ndesc++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) return ndesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) static netdev_tx_t ag71xx_hard_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) struct net_device *ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) int i, n, ring_min, ring_mask, ring_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) struct ag71xx_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) struct ag71xx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) ring = &ag->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) ring_size = BIT(ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (skb->len <= 4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) netif_dbg(ag, tx_err, ndev, "packet len is too small\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) goto err_drop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dma_addr = dma_map_single(&ag->pdev->dev, skb->data, skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) i = ring->curr & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* setup descriptor fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) n = ag71xx_fill_dma_desc(ring, (u32)dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) skb->len & ag->dcfg->desc_pktlen_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) if (n < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) goto err_drop_unmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) i = (ring->curr + n - 1) & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) ring->buf[i].tx.len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ring->buf[i].tx.skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) netdev_sent_queue(ndev, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) desc->ctrl &= ~DESC_EMPTY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) ring->curr += n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) /* flush descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) ring_min = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (ring->desc_split)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) ring_min *= AG71XX_TX_RING_DS_PER_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (ring->curr - ring->dirty >= ring_size - ring_min) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) netif_dbg(ag, tx_err, ndev, "tx queue full\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) netif_stop_queue(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) netif_dbg(ag, tx_queued, ndev, "packet injected into TX queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* enable TX engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) err_drop_unmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) dma_unmap_single(&ag->pdev->dev, dma_addr, skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) err_drop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) ndev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) static void ag71xx_oom_timer_handler(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct ag71xx *ag = from_timer(ag, t, oom_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) napi_schedule(&ag->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static void ag71xx_tx_timeout(struct net_device *ndev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) netif_err(ag, tx_err, ndev, "tx timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) schedule_delayed_work(&ag->restart_work, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) static void ag71xx_restart_work_func(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) struct ag71xx *ag = container_of(work, struct ag71xx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) restart_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) rtnl_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) ag71xx_hw_disable(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ag71xx_hw_enable(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) phylink_stop(ag->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) phylink_start(ag->phylink);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) rtnl_unlock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) int ring_mask, ring_size, done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) unsigned int pktlen_mask, offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) struct sk_buff *next, *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) struct ag71xx_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) struct list_head rx_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) ring = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) pktlen_mask = ag->dcfg->desc_pktlen_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) offset = ag->rx_buf_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) ring_mask = BIT(ring->order) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) ring_size = BIT(ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) netif_dbg(ag, rx_status, ndev, "rx packets, limit=%d, curr=%u, dirty=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) limit, ring->curr, ring->dirty);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) INIT_LIST_HEAD(&rx_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) while (done < limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) unsigned int i = ring->curr & ring_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct ag71xx_desc *desc = ag71xx_ring_desc(ring, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) int pktlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) if (ag71xx_desc_empty(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) if ((ring->dirty + ring_size) == ring->curr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) WARN_ONCE(1, "RX out of ring");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) pktlen = desc->ctrl & pktlen_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) pktlen -= ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) dma_unmap_single(&ag->pdev->dev, ring->buf[i].rx.dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) ag->rx_buf_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) ndev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) ndev->stats.rx_bytes += pktlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) skb = build_skb(ring->buf[i].rx.rx_buf, ag71xx_buffer_size(ag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) skb_free_frag(ring->buf[i].rx.rx_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) skb_reserve(skb, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) skb_put(skb, pktlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) ndev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) skb->dev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) skb->ip_summed = CHECKSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) list_add_tail(&skb->list, &rx_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) ring->buf[i].rx.rx_buf = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) ring->curr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) ag71xx_ring_rx_refill(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) list_for_each_entry_safe(skb, next, &rx_list, list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) skb->protocol = eth_type_trans(skb, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) netif_receive_skb_list(&rx_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) netif_dbg(ag, rx_status, ndev, "rx finish, curr=%u, dirty=%u, done=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) ring->curr, ring->dirty, done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) return done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) static int ag71xx_poll(struct napi_struct *napi, int limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct ag71xx_ring *rx_ring = &ag->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) int rx_ring_size = BIT(rx_ring->order);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) struct net_device *ndev = ag->ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) int tx_done, rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) tx_done = ag71xx_tx_packets(ag, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) netif_dbg(ag, rx_status, ndev, "processing RX ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) rx_done = ag71xx_rx_packets(ag, limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (!rx_ring->buf[rx_ring->dirty % rx_ring_size].rx.rx_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) goto oom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) status = ag71xx_rr(ag, AG71XX_REG_RX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (unlikely(status & RX_STATUS_OF)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) ndev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) /* restart RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (rx_done < limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) if (status & RX_STATUS_PR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) goto more;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) status = ag71xx_rr(ag, AG71XX_REG_TX_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (status & TX_STATUS_PS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) goto more;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) netif_dbg(ag, rx_status, ndev, "disable polling mode, rx=%d, tx=%d,limit=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) rx_done, tx_done, limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) napi_complete(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) /* enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) ag71xx_int_enable(ag, AG71XX_INT_POLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return rx_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) more:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) netif_dbg(ag, rx_status, ndev, "stay in polling mode, rx=%d, tx=%d, limit=%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) rx_done, tx_done, limit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) oom:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) netif_err(ag, rx_err, ndev, "out of memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) mod_timer(&ag->oom_timer, jiffies + AG71XX_OOM_REFILL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) napi_complete(napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) struct net_device *ndev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) struct ag71xx *ag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) if (unlikely(!status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (unlikely(status & AG71XX_INT_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (status & AG71XX_INT_TX_BE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) netif_err(ag, intr, ndev, "TX BUS error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (status & AG71XX_INT_RX_BE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) netif_err(ag, intr, ndev, "RX BUS error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) if (likely(status & AG71XX_INT_POLL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) ag71xx_int_disable(ag, AG71XX_INT_POLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) netif_dbg(ag, intr, ndev, "enable polling mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) napi_schedule(&ag->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) static int ag71xx_change_mtu(struct net_device *ndev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) struct ag71xx *ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) ndev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) ag71xx_wr(ag, AG71XX_REG_MAC_MFL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) ag71xx_max_frame_len(ndev->mtu));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) static const struct net_device_ops ag71xx_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .ndo_open = ag71xx_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .ndo_stop = ag71xx_stop,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .ndo_start_xmit = ag71xx_hard_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .ndo_do_ioctl = phy_do_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .ndo_tx_timeout = ag71xx_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .ndo_change_mtu = ag71xx_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static const u32 ar71xx_addr_ar7100[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) 0x19000000, 0x1a000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) static int ag71xx_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) const struct ag71xx_dcfg *dcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) struct net_device *ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) const void *mac_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) int tx_size, err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) struct ag71xx *ag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (!np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ndev = devm_alloc_etherdev(&pdev->dev, sizeof(*ag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (!ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) dcfg = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (!dcfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) ag->mac_idx = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) for (i = 0; i < ARRAY_SIZE(ar71xx_addr_ar7100); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) if (ar71xx_addr_ar7100[i] == res->start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) ag->mac_idx = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (ag->mac_idx < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) netif_err(ag, probe, ndev, "unknown mac idx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) ag->clk_eth = devm_clk_get(&pdev->dev, "eth");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) if (IS_ERR(ag->clk_eth)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) netif_err(ag, probe, ndev, "Failed to get eth clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) return PTR_ERR(ag->clk_eth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) SET_NETDEV_DEV(ndev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) ag->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) ag->ndev = ndev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) ag->dcfg = dcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) ag->msg_enable = netif_msg_init(-1, AG71XX_DEFAULT_MSG_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) memcpy(ag->fifodata, dcfg->fifodata, sizeof(ag->fifodata));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) ag->mac_reset = devm_reset_control_get(&pdev->dev, "mac");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) if (IS_ERR(ag->mac_reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) netif_err(ag, probe, ndev, "missing mac reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) return PTR_ERR(ag->mac_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) ag->mac_base = devm_ioremap(&pdev->dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) if (!ag->mac_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ndev->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) 0x0, dev_name(&pdev->dev), ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) netif_err(ag, probe, ndev, "unable to request IRQ %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) ndev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) ndev->netdev_ops = &ag71xx_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) ndev->ethtool_ops = &ag71xx_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) INIT_DELAYED_WORK(&ag->restart_work, ag71xx_restart_work_func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) timer_setup(&ag->oom_timer, ag71xx_oom_timer_handler, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) tx_size = AG71XX_TX_RING_SIZE_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) ag->rx_ring.order = ag71xx_ring_size_order(AG71XX_RX_RING_SIZE_DEFAULT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) ndev->min_mtu = 68;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) ndev->max_mtu = dcfg->max_frame_len - ag71xx_max_frame_len(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) ag->rx_buf_offset = NET_SKB_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) if (!ag71xx_is(ag, AR7100) && !ag71xx_is(ag, AR9130))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) ag->rx_buf_offset += NET_IP_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) if (ag71xx_is(ag, AR7100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) ag->tx_ring.desc_split = AG71XX_TX_RING_SPLIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) tx_size *= AG71XX_TX_RING_DS_PER_PKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) ag->tx_ring.order = ag71xx_ring_size_order(tx_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) ag->stop_desc = dmam_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) sizeof(struct ag71xx_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) &ag->stop_desc_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (!ag->stop_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) ag->stop_desc->data = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) ag->stop_desc->ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ag->stop_desc->next = (u32)ag->stop_desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) mac_addr = of_get_mac_address(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (!IS_ERR(mac_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) if (IS_ERR(mac_addr) || !is_valid_ether_addr(ndev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) netif_err(ag, probe, ndev, "invalid MAC address, using random address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) eth_random_addr(ndev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) err = of_get_phy_mode(np, &ag->phy_if_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) netif_err(ag, probe, ndev, "missing phy-mode property in DT\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) netif_napi_add(ndev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) err = clk_prepare_enable(ag->clk_eth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) netif_err(ag, probe, ndev, "Failed to enable eth clk.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) ag71xx_hw_init(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) err = ag71xx_mdio_probe(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) goto err_put_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) platform_set_drvdata(pdev, ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) err = ag71xx_phylink_setup(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) netif_err(ag, probe, ndev, "failed to setup phylink (%d)\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) goto err_mdio_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) err = register_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) netif_err(ag, probe, ndev, "unable to register net device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) goto err_mdio_remove;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) netif_info(ag, probe, ndev, "Atheros AG71xx at 0x%08lx, irq %d, mode:%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) (unsigned long)ag->mac_base, ndev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) phy_modes(ag->phy_if_mode));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) err_mdio_remove:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) ag71xx_mdio_remove(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) err_put_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) clk_disable_unprepare(ag->clk_eth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) static int ag71xx_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) struct net_device *ndev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) struct ag71xx *ag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (!ndev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) ag = netdev_priv(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) unregister_netdev(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) ag71xx_mdio_remove(ag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) clk_disable_unprepare(ag->clk_eth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) static const u32 ar71xx_fifo_ar7100[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) 0x0fff0000, 0x00001fff, 0x00780fff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) static const u32 ar71xx_fifo_ar9130[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) 0x0fff0000, 0x00001fff, 0x008001ff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) static const u32 ar71xx_fifo_ar9330[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) 0x0010ffff, 0x015500aa, 0x01f00140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) static const struct ag71xx_dcfg ag71xx_dcfg_ar7100 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) .type = AR7100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) .fifodata = ar71xx_fifo_ar7100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) .max_frame_len = 1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) .desc_pktlen_mask = SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) .tx_hang_workaround = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) static const struct ag71xx_dcfg ag71xx_dcfg_ar7240 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) .type = AR7240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) .fifodata = ar71xx_fifo_ar7100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) .max_frame_len = 1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) .desc_pktlen_mask = SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) .tx_hang_workaround = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) static const struct ag71xx_dcfg ag71xx_dcfg_ar9130 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) .type = AR9130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) .fifodata = ar71xx_fifo_ar9130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) .max_frame_len = 1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) .desc_pktlen_mask = SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) .tx_hang_workaround = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) static const struct ag71xx_dcfg ag71xx_dcfg_ar9330 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) .type = AR9330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) .fifodata = ar71xx_fifo_ar9330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) .max_frame_len = 1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) .desc_pktlen_mask = SZ_4K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) .tx_hang_workaround = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) static const struct ag71xx_dcfg ag71xx_dcfg_ar9340 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) .type = AR9340,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) .fifodata = ar71xx_fifo_ar9330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) .max_frame_len = SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) .desc_pktlen_mask = SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) .tx_hang_workaround = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) static const struct ag71xx_dcfg ag71xx_dcfg_qca9530 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) .type = QCA9530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) .fifodata = ar71xx_fifo_ar9330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) .max_frame_len = SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) .desc_pktlen_mask = SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) .tx_hang_workaround = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) static const struct ag71xx_dcfg ag71xx_dcfg_qca9550 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) .type = QCA9550,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) .fifodata = ar71xx_fifo_ar9330,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) .max_frame_len = 1540,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) .desc_pktlen_mask = SZ_16K - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) .tx_hang_workaround = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) static const struct of_device_id ag71xx_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) { .compatible = "qca,ar7100-eth", .data = &ag71xx_dcfg_ar7100 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) { .compatible = "qca,ar7240-eth", .data = &ag71xx_dcfg_ar7240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) { .compatible = "qca,ar7241-eth", .data = &ag71xx_dcfg_ar7240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) { .compatible = "qca,ar7242-eth", .data = &ag71xx_dcfg_ar7240 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) { .compatible = "qca,ar9130-eth", .data = &ag71xx_dcfg_ar9130 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) { .compatible = "qca,ar9330-eth", .data = &ag71xx_dcfg_ar9330 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) { .compatible = "qca,ar9340-eth", .data = &ag71xx_dcfg_ar9340 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) { .compatible = "qca,qca9530-eth", .data = &ag71xx_dcfg_qca9530 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) { .compatible = "qca,qca9550-eth", .data = &ag71xx_dcfg_qca9550 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) { .compatible = "qca,qca9560-eth", .data = &ag71xx_dcfg_qca9550 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) static struct platform_driver ag71xx_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) .probe = ag71xx_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) .remove = ag71xx_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) .name = "ag71xx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) .of_match_table = ag71xx_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) module_platform_driver(ag71xx_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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