^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2004-2013 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Registers and bits definitions of ARC EMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef ARC_EMAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ARC_EMAC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* STATUS and ENABLE Register bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TXINT_MASK (1 << 0) /* Transmit interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define RXINT_MASK (1 << 1) /* Receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ERR_MASK (1 << 2) /* Error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TXCH_MASK (1 << 3) /* Transmit chaining error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MSER_MASK (1 << 4) /* Missed packet counter error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define RXCR_MASK (1 << 8) /* RXCRCERR counter rolled over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RXFR_MASK (1 << 9) /* RXFRAMEERR counter rolled over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define RXFL_MASK (1 << 10) /* RXOFLOWERR counter rolled over */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MDIO_MASK (1 << 12) /* MDIO complete interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TXPL_MASK (1 << 31) /* Force polling of BD by EMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* CONTROL Register bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EN_MASK (1 << 0) /* VMAC enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TXRN_MASK (1 << 3) /* TX enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RXRN_MASK (1 << 4) /* RX enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DSBC_MASK (1 << 8) /* Disable receive broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ENFL_MASK (1 << 10) /* Enable Full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PROM_MASK (1 << 11) /* Promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Buffer descriptor INFO bit masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define OWN_MASK (1 << 31) /* 0-CPU or 1-EMAC owns buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define FIRST_MASK (1 << 16) /* First buffer in chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define LAST_MASK (1 << 17) /* Last buffer in chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define LEN_MASK 0x000007FF /* last 11 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CRLS (1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DEFR (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define DROP (1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define RTRY (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LTCL (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define UFLO (1 << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define FOR_EMAC OWN_MASK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define FOR_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* ARC EMAC register set combines entries for MAC and MDIO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) R_ID = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) R_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) R_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) R_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) R_POLLRATE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) R_RXERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) R_MISS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) R_TX_RING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) R_RX_RING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) R_ADDRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) R_ADDRH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) R_LAFL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) R_LAFH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) R_MDIO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TX_TIMEOUT (400 * HZ / 1000) /* Transmission timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ARC_EMAC_NAPI_WEIGHT 40 /* Workload for NAPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EMAC_BUFFER_SIZE 1536 /* EMAC buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * struct arc_emac_bd - EMAC buffer descriptor (BD).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @info: Contains status information on the buffer itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @data: 32-bit byte addressable pointer to the packet data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct arc_emac_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) __le32 info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) dma_addr_t data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Number of Rx/Tx BD's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define RX_BD_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TX_BD_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define RX_RING_SZ (RX_BD_NUM * sizeof(struct arc_emac_bd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TX_RING_SZ (TX_BD_NUM * sizeof(struct arc_emac_bd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * struct buffer_state - Stores Rx/Tx buffer state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @sk_buff: Pointer to socket buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @addr: Start address of DMA-mapped memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @len: Length of DMA-mapped memory region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct buffer_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) DEFINE_DMA_UNMAP_ADDR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) DEFINE_DMA_UNMAP_LEN(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct arc_emac_mdio_bus_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int msec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * struct arc_emac_priv - Storage of EMAC's private information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @dev: Pointer to the current device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @phy_dev: Pointer to attached PHY device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @bus: Pointer to the current MII bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @regs: Base address of EMAC memory-mapped control registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @napi: Structure for NAPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @rxbd: Pointer to Rx BD ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @txbd: Pointer to Tx BD ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @rxbd_dma: DMA handle for Rx BD ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @txbd_dma: DMA handle for Tx BD ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @rx_buff: Storage for Rx buffers states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @tx_buff: Storage for Tx buffers states.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @txbd_curr: Index of Tx BD to use on the next "ndo_start_xmit".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @txbd_dirty: Index of Tx BD to free on the next Tx interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @last_rx_bd: Index of the last Rx BD we've got from EMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @link: PHY's last seen link state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @duplex: PHY's last set duplex mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @speed: PHY's last set speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct arc_emac_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) const char *drv_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) void (*set_mac_speed)(void *priv, unsigned int speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct arc_emac_mdio_bus_data bus_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct arc_emac_bd *rxbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct arc_emac_bd *txbd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dma_addr_t rxbd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dma_addr_t txbd_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct buffer_state rx_buff[RX_BD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct buffer_state tx_buff[TX_BD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned int txbd_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int txbd_dirty;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int last_rx_bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) unsigned int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned int rx_missed_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * arc_reg_set - Sets EMAC register with provided value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @priv: Pointer to ARC EMAC private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @reg: Register offset from base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @value: Value to set in register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static inline void arc_reg_set(struct arc_emac_priv *priv, int reg, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) iowrite32(value, priv->regs + reg * sizeof(int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * arc_reg_get - Gets value of specified EMAC register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @priv: Pointer to ARC EMAC private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @reg: Register offset from base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * returns: Value of requested register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static inline unsigned int arc_reg_get(struct arc_emac_priv *priv, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ioread32(priv->regs + reg * sizeof(int));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * arc_reg_or - Applies mask to specified EMAC register - ("reg" | "mask").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @priv: Pointer to ARC EMAC private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @reg: Register offset from base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @mask: Mask to apply to specified register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * This function reads initial register value, then applies provided mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * to it and then writes register back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline void arc_reg_or(struct arc_emac_priv *priv, int reg, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int value = arc_reg_get(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) arc_reg_set(priv, reg, value | mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * arc_reg_clr - Applies mask to specified EMAC register - ("reg" & ~"mask").
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @priv: Pointer to ARC EMAC private data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @reg: Register offset from base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @mask: Mask to apply to specified register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * This function reads initial register value, then applies provided mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * to it and then writes register back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned int value = arc_reg_get(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) arc_reg_set(priv, reg, value & ~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) int arc_mdio_probe(struct arc_emac_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) int arc_mdio_remove(struct arc_emac_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int arc_emac_probe(struct net_device *ndev, int interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int arc_emac_remove(struct net_device *ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #endif /* ARC_EMAC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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