^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mace.h - definitions for the registers in the Am79C940 MACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (Medium Access Control for Ethernet) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1996 Paul Mackerras.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define REG(x) volatile unsigned char x; char x ## _pad[15]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct mace {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) REG(rcvfifo); /* receive FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) REG(xmtfifo); /* transmit FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) REG(xmtfc); /* transmit frame control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) REG(xmtfs); /* transmit frame status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) REG(xmtrc); /* transmit retry count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) REG(rcvfc); /* receive frame control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) REG(rcvfs); /* receive frame status (4 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) REG(fifofc); /* FIFO frame count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) REG(ir); /* interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) REG(imr); /* interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) REG(pr); /* poll register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) REG(biucc); /* bus interface unit config control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) REG(fifocc); /* FIFO configuration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) REG(maccc); /* medium access control config control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) REG(plscc); /* phys layer signalling config control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) REG(phycc); /* physical configuration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) REG(chipid_lo); /* chip ID, lsb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) REG(chipid_hi); /* chip ID, msb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) REG(iac); /* internal address config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) REG(reg19);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) REG(ladrf); /* logical address filter (8 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) REG(padr); /* physical address (6 bytes) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) REG(reg22);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) REG(reg23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) REG(mpc); /* missed packet count (clears when read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) REG(reg25);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) REG(rntpc); /* runt packet count (clears when read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) REG(rcvcc); /* recv collision count (clears when read) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) REG(reg28);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) REG(utr); /* user test reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) REG(reg30);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) REG(reg31);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Bits in XMTFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define DRTRY 0x80 /* don't retry transmission after collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DXMTFCS 0x08 /* don't append FCS to transmitted frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define AUTO_PAD_XMIT 0x01 /* auto-pad short packets on transmission */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define XMTSV 0x80 /* transmit status (i.e. XMTFS) valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define UFLO 0x40 /* underflow - xmit fifo ran dry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LCOL 0x20 /* late collision (transmission aborted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MORE 0x10 /* 2 or more retries needed to xmit frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ONE 0x08 /* 1 retry needed to xmit frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DEFER 0x04 /* MACE had to defer xmission (enet busy) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LCAR 0x02 /* loss of carrier (transmission aborted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RTRY 0x01 /* too many retries (transmission aborted) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EXDEF 0x80 /* had to defer for excessive time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define RETRY_MASK 0x0f /* number of retries (0 - 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Bits in RCVFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LLRCV 0x08 /* low latency receive: early DMA request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define M_RBAR 0x04 /* sets function of EAM/R pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define AUTO_STRIP_RCV 0x01 /* auto-strip short LLC frames on recv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * Bits in RCVFS. After a frame is received, four bytes of status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * are automatically read from this register and appended to the frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * data in memory. These are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * Byte 0 and 1: message byte count and frame status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Byte 2: runt packet count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Byte 3: receive collision count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define RS_OFLO 0x8000 /* receive FIFO overflowed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define RS_CLSN 0x4000 /* received frame suffered (late) collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define RS_FRAMERR 0x2000 /* framing error flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define RS_FCSERR 0x1000 /* frame had FCS error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define RS_COUNT 0x0fff /* mask for byte count field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Bits (fields) in FIFOFC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define RCVFC_SH 4 /* receive frame count in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define RCVFC_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XMTFC_SH 0 /* transmit frame count in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define XMTFC_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Bits in IR and IMR. The IR clears itself when read.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * Setting a bit in the IMR will disable the corresponding interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define JABBER 0x80 /* jabber error - 10baseT xmission too long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BABBLE 0x40 /* babble - xmitter xmitting for too long */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CERR 0x20 /* collision err - no SQE test (heartbeat) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RCVCCO 0x10 /* RCVCC overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define RNTPCO 0x08 /* RNTPC overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MPCO 0x04 /* MPC overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RCVINT 0x02 /* receive interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define XMTINT 0x01 /* transmitter interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Bits in PR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define XMTSV 0x80 /* XMTFS valid (same as in XMTFS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TDTREQ 0x40 /* set when xmit fifo is requesting data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define RDTREQ 0x20 /* set when recv fifo requests data xfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Bits in BIUCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BSWP 0x40 /* byte swap, i.e. big-endian bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define XMTSP_4 0x00 /* start xmitting when 4 bytes in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define XMTSP_16 0x10 /* start xmitting when 16 bytes in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define XMTSP_64 0x20 /* start xmitting when 64 bytes in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define XMTSP_112 0x30 /* start xmitting when 112 bytes in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SWRST 0x01 /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Bits in FIFOCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define XMTFW_8 0x00 /* xmit fifo watermark = 8 words free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define XMTFW_16 0x40 /* 16 words free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define XMTFW_32 0x80 /* 32 words free */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RCVFW_16 0x00 /* recv fifo watermark = 16 bytes avail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RCVFW_32 0x10 /* 32 bytes avail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RCVFW_64 0x20 /* 64 bytes avail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define XMTFWU 0x08 /* xmit fifo watermark update enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RCVFWU 0x04 /* recv fifo watermark update enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define XMTBRST 0x02 /* enable transmit burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RCVBRST 0x01 /* enable receive burst mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Bits in MACCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PROM 0x80 /* promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DXMT2PD 0x40 /* disable xmit two-part deferral algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EMBA 0x20 /* enable modified backoff algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DRCVPA 0x08 /* disable receiving physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define DRCVBC 0x04 /* disable receiving broadcasts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ENXMT 0x02 /* enable transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ENRCV 0x01 /* enable receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Bits in PLSCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define XMTSEL 0x08 /* select DO+/DO- state when idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PORTSEL_AUI 0x00 /* select AUI port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PORTSEL_10T 0x02 /* select 10Base-T port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PORTSEL_DAI 0x04 /* select DAI port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PORTSEL_GPSI 0x06 /* select GPSI port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ENPLSIO 0x01 /* enable optional PLS I/O pins */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Bits in PHYCC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LNKFL 0x80 /* reports 10Base-T link failure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define DLNKTST 0x40 /* disable 10Base-T link test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REVPOL 0x20 /* 10Base-T receiver polarity reversed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define DAPC 0x10 /* disable auto receiver polarity correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LRT 0x08 /* low receive threshold for long links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ASEL 0x04 /* auto-select AUI or 10Base-T port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define RWAKE 0x02 /* remote wake function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AWAKE 0x01 /* auto wake function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Bits in IAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ADDRCHG 0x80 /* request address change */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PHYADDR 0x04 /* access physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LOGADDR 0x02 /* access multicast filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* Bits in UTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define RTRE 0x80 /* reserved test register enable. DON'T SET. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define RTRD 0x40 /* reserved test register disable. Sticky */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RPAC 0x20 /* accept runt packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FCOLL 0x10 /* force collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define RCVFCSE 0x08 /* receive FCS enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define LOOP_NONE 0x00 /* no loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define LOOP_EXT 0x02 /* external loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define LOOP_INT 0x04 /* internal loopback, excludes MENDEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define LOOP_MENDEC 0x06 /* internal loopback, includes MENDEC */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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