^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * mace.h - definitions for the registers in the "Big Mac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Ethernet controller found in PowerMac G3 models.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 1998 Randy Gobbel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* The "Big MAC" appears to have some parts in common with the Sun "Happy Meal"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * (HME) controller. See sunhme.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* global status and control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define XIFC 0x000 /* low-level interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) # define TxOutputEnable 0x0001 /* output driver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) # define XIFLoopback 0x0002 /* Loopback-mode XIF enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) # define MIILoopback 0x0004 /* Loopback-mode MII enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) # define MIILoopbackBits 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) # define MIIBuffDisable 0x0008 /* MII receive buffer disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) # define SQETestEnable 0x0010 /* SQE test enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) # define SQETimeWindow 0x03e0 /* SQE time window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) # define XIFLanceMode 0x0010 /* Lance mode enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) # define XIFLanceIPG0 0x03e0 /* Lance mode IPG0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TXFIFOCSR 0x100 /* transmit FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) # define TxFIFOEnable 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TXTH 0x110 /* transmit threshold */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) # define TxThreshold 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define RXFIFOCSR 0x120 /* receive FIFO control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) # define RxFIFOEnable 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MEMADD 0x130 /* memory address, unknown function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MEMDATAHI 0x140 /* memory data high, presently unused in driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MEMDATALO 0x150 /* memory data low, presently unused in driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define XCVRIF 0x160 /* transceiver interface control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) # define COLActiveLow 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) # define SerialMode 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) # define ClkBit 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) # define LinkStatus 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CHIPID 0x170 /* chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIFCSR 0x180 /* ??? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SROMCSR 0x190 /* SROM control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) # define ChipSelect 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) # define Clk 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TXPNTR 0x1a0 /* transmit pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define RXPNTR 0x1b0 /* receive pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define STATUS 0x200 /* status--reading this clears it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define INTDISABLE 0x210 /* interrupt enable/disable control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* bits below are the same in both STATUS and INTDISABLE registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) # define FrameReceived 0x00000001 /* Received a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) # define RxFrameCntExp 0x00000002 /* Receive frame counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) # define RxAlignCntExp 0x00000004 /* Align-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) # define RxCRCCntExp 0x00000008 /* CRC-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) # define RxLenCntExp 0x00000010 /* Length-error counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) # define RxOverFlow 0x00000020 /* Receive FIFO overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) # define RxCodeViolation 0x00000040 /* Code-violation counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) # define SQETestError 0x00000080 /* Test error in XIF for SQE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) # define FrameSent 0x00000100 /* Transmitted a frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) # define TxUnderrun 0x00000200 /* Transmit FIFO underrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) # define TxMaxSizeError 0x00000400 /* Max-packet size error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) # define TxNormalCollExp 0x00000800 /* Normal-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) # define TxExcessCollExp 0x00001000 /* Excess-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) # define TxLateCollExp 0x00002000 /* Late-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) # define TxNetworkCollExp 0x00004000 /* First-collision counter expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) # define TxDeferTimerExp 0x00008000 /* Defer-timer expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) # define RxFIFOToHost 0x00010000 /* Data moved from FIFO to host */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) # define RxNoDescriptors 0x00020000 /* No more receive descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) # define RxDMAError 0x00040000 /* Error during receive DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) # define RxDMALateErr 0x00080000 /* Receive DMA, data late */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) # define RxParityErr 0x00100000 /* Parity error during receive DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) # define RxTagError 0x00200000 /* Tag error during receive DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) # define TxEOPError 0x00400000 /* Tx descriptor did not have EOP set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) # define MIFIntrEvent 0x00800000 /* MIF is signaling an interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) # define TxHostToFIFO 0x01000000 /* Data moved from host to FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) # define TxFIFOAllSent 0x02000000 /* Transmitted all packets in FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) # define TxDMAError 0x04000000 /* Error during transmit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) # define TxDMALateError 0x08000000 /* Late error during transmit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) # define TxParityError 0x10000000 /* Parity error during transmit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) # define TxTagError 0x20000000 /* Tag error during transmit DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) # define PIOError 0x40000000 /* PIO access got an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) # define PIOParityError 0x80000000 /* PIO access got a parity error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) # define DisableAll 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) # define EnableAll 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* # define NormalIntEvents ~(FrameReceived | FrameSent | TxUnderrun) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) # define EnableNormal ~(FrameReceived | FrameSent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) # define EnableErrors (FrameReceived | FrameSent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) # define RxErrorMask (RxFrameCntExp | RxAlignCntExp | RxCRCCntExp | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) RxLenCntExp | RxOverFlow | RxCodeViolation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) # define TxErrorMask (TxUnderrun | TxMaxSizeError | TxExcessCollExp | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) TxLateCollExp | TxNetworkCollExp | TxDeferTimerExp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* transmit control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TXRST 0x420 /* transmit reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) # define TxResetBit 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TXCFG 0x430 /* transmit configuration control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) # define TxMACEnable 0x0001 /* output driver enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) # define TxSlowMode 0x0020 /* enable slow mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) # define TxIgnoreColl 0x0040 /* ignore transmit collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) # define TxNoFCS 0x0080 /* do not emit FCS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) # define TxNoBackoff 0x0100 /* no backoff in case of collisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) # define TxFullDuplex 0x0200 /* enable full-duplex */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) # define TxNeverGiveUp 0x0400 /* don't give up on transmits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IPG1 0x440 /* Inter-packet gap 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IPG2 0x450 /* Inter-packet gap 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ALIMIT 0x460 /* Transmit attempt limit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SLOT 0x470 /* Transmit slot time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PALEN 0x480 /* Size of transmit preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PAPAT 0x490 /* Pattern for transmit preamble */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TXSFD 0x4a0 /* Transmit frame delimiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define JAM 0x4b0 /* Jam size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TXMAX 0x4c0 /* Transmit max pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TXMIN 0x4d0 /* Transmit min pkt size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PAREG 0x4e0 /* Count of transmit peak attempts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DCNT 0x4f0 /* Transmit defer timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define NCCNT 0x500 /* Transmit normal-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define NTCNT 0x510 /* Transmit first-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EXCNT 0x520 /* Transmit excess-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LTCNT 0x530 /* Transmit late-collision counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define RSEED 0x540 /* Transmit random number seed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TXSM 0x550 /* Transmit state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* receive control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define RXRST 0x620 /* receive reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) # define RxResetValue 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define RXCFG 0x630 /* receive configuration control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) # define RxMACEnable 0x0001 /* receiver overall enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) # define RxCFGReserved 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) # define RxPadStripEnab 0x0020 /* enable pad byte stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) # define RxPromiscEnable 0x0040 /* turn on promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) # define RxNoErrCheck 0x0080 /* disable receive error checking */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) # define RxCRCNoStrip 0x0100 /* disable auto-CRC-stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) # define RxRejectOwnPackets 0x0200 /* don't receive our own packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) # define RxGrpPromisck 0x0400 /* enable group promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) # define RxHashFilterEnable 0x0800 /* enable hash filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) # define RxAddrFilterEnable 0x1000 /* enable address filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define RXMAX 0x640 /* Max receive packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define RXMIN 0x650 /* Min receive packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MADD2 0x660 /* our enet address, high part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MADD1 0x670 /* our enet address, middle part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MADD0 0x680 /* our enet address, low part */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define FRCNT 0x690 /* receive frame counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LECNT 0x6a0 /* Receive excess length error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AECNT 0x6b0 /* Receive misaligned error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define FECNT 0x6c0 /* Receive CRC error counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define RXSM 0x6d0 /* Receive state machine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define RXCV 0x6e0 /* Receive code violation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BHASH3 0x700 /* multicast hash register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BHASH2 0x710 /* multicast hash register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BHASH1 0x720 /* multicast hash register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BHASH0 0x730 /* multicast hash register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AFR2 0x740 /* address filtering setup? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AFR1 0x750 /* address filtering setup? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AFR0 0x760 /* address filtering setup? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define AFCR 0x770 /* address filter compare register? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) # define EnableAllCompares 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* bits in XIFC */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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