^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* am7990 (lance) definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This is an extension to the Linux operating system, and is covered by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * same GNU General Public License that covers that work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Michael Hipp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * email: mhipp@student.uni-tuebingen.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * sources: (mail me or ask archie if you need them)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * crynwr-packet-driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Control and Status Register 0 (CSR0) bit definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * (R=Readable) (W=Writeable) (S=Set on write) (C-Clear on write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CSR0_ERR 0x8000 /* Error summary (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CSR0_BABL 0x4000 /* Babble transmitter timeout error (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CSR0_CERR 0x2000 /* Collision Error (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CSR0_MISS 0x1000 /* Missed packet (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CSR0_MERR 0x0800 /* Memory Error (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CSR0_RINT 0x0400 /* Receiver Interrupt (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CSR0_TINT 0x0200 /* Transmit Interrupt (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CSR0_IDON 0x0100 /* Initialization Done (RC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CSR0_INTR 0x0080 /* Interrupt Flag (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CSR0_INEA 0x0040 /* Interrupt Enable (RW) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CSR0_RXON 0x0020 /* Receiver on (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CSR0_TXON 0x0010 /* Transmitter on (R) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CSR0_TDMD 0x0008 /* Transmit Demand (RS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CSR0_STOP 0x0004 /* Stop (RS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CSR0_STRT 0x0002 /* Start (RS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CSR0_INIT 0x0001 /* Initialize (RS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CSR0_CLRALL 0x7f00 /* mask for all clearable bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Initialization Block Mode operation Bit Definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define M_PROM 0x8000 /* Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define M_INTL 0x0040 /* Internal Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define M_DRTY 0x0020 /* Disable Retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define M_COLL 0x0010 /* Force Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define M_DTCR 0x0008 /* Disable Transmit CRC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define M_LOOP 0x0004 /* Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define M_DTX 0x0002 /* Disable the Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define M_DRX 0x0001 /* Disable the Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Receive message descriptor bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define RCV_OWN 0x80 /* owner bit 0 = host, 1 = lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define RCV_ERR 0x40 /* Error Summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define RCV_FRAM 0x20 /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define RCV_OFLO 0x10 /* Overflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define RCV_CRC 0x08 /* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define RCV_BUF_ERR 0x04 /* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define RCV_START 0x02 /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define RCV_END 0x01 /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * Transmit message descriptor bit definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define XMIT_OWN 0x80 /* owner bit 0 = host, 1 = lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define XMIT_ERR 0x40 /* Error Summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define XMIT_RETRY 0x10 /* more the 1 retry needed to Xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XMIT_1_RETRY 0x08 /* one retry needed to Xmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XMIT_DEF 0x04 /* Deferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XMIT_START 0x02 /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XMIT_END 0x01 /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * transmit status (2) (valid if XMIT_ERR == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define XMIT_TDRMASK 0x03ff /* time-domain-reflectometer-value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define XMIT_RTRY 0x0400 /* Failed after 16 retransmissions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define XMIT_LCAR 0x0800 /* Loss of Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XMIT_LCOL 0x1000 /* Late collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XMIT_RESERV 0x2000 /* Reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XMIT_UFLO 0x4000 /* Underflow (late memory) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XMIT_BUFF 0x8000 /* Buffering error (no ENP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned short mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned char eaddr[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned char filter[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* bit 29-31: number of rmd's (power of 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 rrp; /* receive ring pointer (align 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* bit 29-31: number of tmd's (power of 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 trp; /* transmit ring pointer (align 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct rmd { /* Receive Message Descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) volatile u32 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) volatile unsigned char dummy[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) volatile unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) volatile short blen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) volatile unsigned short mlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct tmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) volatile u32 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) volatile unsigned char dummy[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) volatile unsigned char status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) } u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) volatile unsigned short blen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) volatile unsigned short status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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