^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * ni6510 (am7990 'lance' chip) driver for Linux-net-3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BETAcode v0.71 (96/09/29) for 2.0.0 (or later)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * copyrights (c) 1994,1995,1996 by M.Hipp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * This driver can handle the old ni6510 board and the newer ni6510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * EtherBlaster. (probably it also works with every full NE2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * compatible card)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * driver probes: io: 0x360,0x300,0x320,0x340 / dma: 3,5,6,7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * This is an extension to the Linux operating system, and is covered by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * same GNU General Public License that covers the Linux-kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * comments/bugs/suggestions can be sent to:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Michael Hipp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * email: hippm@informatik.uni-tuebingen.de
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * sources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * some things are from the 'ni6510-packet-driver for dos by Russ Nelson'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * and from the original drivers by D.Becker
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * known problems:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * - on some PCI boards (including my own) the card/board/ISA-bridge has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * problems with bus master DMA. This results in lotsa overruns.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * It may help to '#define RCV_PARANOIA_CHECK' or try to #undef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * the XMT and RCV_VIA_SKB option .. this reduces driver performance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Or just play with your BIOS options to optimize ISA-DMA access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * Maybe you also wanna play with the LOW_PERFORAMCE and MID_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * defines -> please report me your experience then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - Harald reported for ASUS SP3G mainboards, that you should use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * the 'optimal settings' from the user's manual on page 3-12!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * credits:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * thanx to Jason Sullivan for sending me a ni6510 card!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * lot of debug runs with ASUS SP3G Boards (Intel Saturn) by Harald Koenig
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * simple performance test: (486DX-33/Ni6510-EB receives from 486DX4-100/Ni6510-EB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * average: FTP -> 8384421 bytes received in 8.5 seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * (no RCV_VIA_SKB,no XMT_VIA_SKB,PARANOIA_CHECK,4 XMIT BUFS, 8 RCV_BUFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * peak: FTP -> 8384421 bytes received in 7.5 seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * (RCV_VIA_SKB,XMT_VIA_SKB,no PARANOIA_CHECK,1(!) XMIT BUF, 16 RCV BUFFS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * 99.Jun.8: added support for /proc/net/dev byte count for xosview (HK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * 96.Sept.29: virt_to_bus stuff added for new memory modell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * 96.April.29: Added Harald Koenig's Patches (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * 96.April.13: enhanced error handling .. more tests (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * 96.April.5/6: a lot of performance tests. Got it stable now (hopefully) (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * 96.April.1: (no joke ;) .. added EtherBlaster and Module support (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * 96.Feb.19: fixed a few bugs .. cleanups .. tested for 1.3.66 (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * hopefully no more 16MB limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * 95.Nov.18: multicast tweaked (AC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * 94.Aug.22: changes in xmit_intr (ack more than one xmitted-packet), ni65_send_packet (p->lock) (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * 94.July.16: fixed bugs in recv_skb and skb-alloc stuff (MH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include "ni65.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * the current setting allows an acceptable performance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * for 'RCV_PARANOIA_CHECK' read the 'known problems' part in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * the header of this file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * 'invert' the defines for max. performance. This may cause DMA problems
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * on some boards (e.g on my ASUS SP3G)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #undef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #undef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define RCV_PARANOIA_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MID_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #if defined( LOW_PERFORMANCE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static int isa0=7,isa1=7,csr80=0x0c10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #elif defined( MID_PERFORMANCE )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int isa0=5,isa1=5,csr80=0x2810;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #else /* high performance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int isa0=4,isa1=4,csr80=0x0017;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * a few card/vendor specific defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define NI65_ID0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define NI65_ID1 0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define NI65_EB_ID0 0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define NI65_EB_ID1 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define NE2100_ID0 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define NE2100_ID1 0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PORT p->cmdr_addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * buffer configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define RMDNUM 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define RMDNUMMASK 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define RMDNUM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define RMDNUMMASK 0x60000000 /* log2(RMDNUM)<<29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TMDNUM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TMDNUMMASK 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TMDNUM 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TMDNUMMASK 0x40000000 /* log2(TMDNUM)<<29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* slightly oversized */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define R_BUF_SIZE 1544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define T_BUF_SIZE 1544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * lance register defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define L_DATAREG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define L_ADDRREG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define L_RESET 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define L_CONFIG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define L_BUSIF 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * to access the lance/am7990-regs, you have to write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * reg-number into L_ADDRREG, then you can access it using L_DATAREG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CSR0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CSR1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CSR2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CSR3 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define INIT_RING_BEFORE_START 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define FULL_RESET_ON_ERROR 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);inw(PORT+L_ADDRREG); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_ADDRREG),\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) inw(PORT+L_DATAREG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define writedatareg(val) {outw(val,PORT+L_DATAREG);inw(PORT+L_DATAREG);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define writedatareg(val) { writereg(val,CSR0); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define writereg(val,reg) {outw(reg,PORT+L_ADDRREG);outw(val,PORT+L_DATAREG);}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define readreg(reg) (outw(reg,PORT+L_ADDRREG),inw(PORT+L_DATAREG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define writedatareg(val) { writereg(val,CSR0); }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static unsigned char ni_vendor[] = { 0x02,0x07,0x01 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) static struct card {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) unsigned char id0,id1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) short id_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) short total_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) short cmd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) short addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned char *vendor_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) char *cardname;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned long config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } cards[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) .id0 = NI65_ID0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) .id1 = NI65_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) .id_offset = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) .total_size = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) .cmd_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) .addr_offset = 0x8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) .vendor_id = ni_vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) .cardname = "ni6510",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) .config = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) .id0 = NI65_EB_ID0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .id1 = NI65_EB_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .id_offset = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) .total_size = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .cmd_offset = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .addr_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) .vendor_id = ni_vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) .cardname = "ni6510 EtherBlaster",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) .config = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) .id0 = NE2100_ID0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) .id1 = NE2100_ID1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) .id_offset = 0x0e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .total_size = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .cmd_offset = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) .addr_offset = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .vendor_id = NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .cardname = "generic NE2100",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) .config = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define NUM_CARDS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct priv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct rmd rmdhead[RMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct tmd tmdhead[TMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct init_block ib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) int rmdnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) int tmdnum,tmdlast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #ifdef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct sk_buff *recv_skb[RMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) void *recvbounce[RMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct sk_buff *tmd_skb[TMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) void *tmdbounce[TMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int tmdbouncenum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) int lock,xmit_queued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) void *self;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int cmdr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int cardno;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) int features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spinlock_t ring_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) static int ni65_probe1(struct net_device *dev,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static irqreturn_t ni65_interrupt(int irq, void * dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void ni65_recv_intr(struct net_device *dev,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static void ni65_xmit_intr(struct net_device *dev,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static int ni65_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int ni65_lance_reinit(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static void ni65_init_lance(struct priv *p,unsigned char*,int,int);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static netdev_tx_t ni65_send_packet(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static void ni65_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static int ni65_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static int ni65_alloc_buffer(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void ni65_free_buffer(struct priv *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static void set_multicast_list(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static int irqtab[] __initdata = { 9,12,15,5 }; /* irq config-translate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static int dmatab[] __initdata = { 0,3,5,6,7 }; /* dma config-translate and autodetect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static int debuglevel = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * set 'performance' registers .. we must STOP lance for that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) static void ni65_set_performance(struct priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) writereg(CSR0_STOP | CSR0_CLRALL,CSR0); /* STOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if( !(cards[p->cardno].config & 0x02) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) outw(80,PORT+L_ADDRREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if(inw(PORT+L_ADDRREG) != 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writereg( (csr80 & 0x3fff) ,80); /* FIFO watermarks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) outw(0,PORT+L_ADDRREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) outw((short)isa0,PORT+L_BUSIF); /* write ISA 0: DMA_R : isa0 * 50ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) outw(1,PORT+L_ADDRREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) outw((short)isa1,PORT+L_BUSIF); /* write ISA 1: DMA_W : isa1 * 50ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) outw(CSR0,PORT+L_ADDRREG); /* switch back to CSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * open interface (up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static int ni65_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) int irqval = request_irq(dev->irq, ni65_interrupt,0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) cards[p->cardno].cardname,dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (irqval) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) printk(KERN_ERR "%s: unable to get IRQ %d (irqval=%d).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev->name,dev->irq, irqval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if(ni65_lance_reinit(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) free_irq(dev->irq,dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * close interface (down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static int ni65_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) outw(inw(PORT+L_RESET),PORT+L_RESET); /* that's the hard way */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) for(i=0;i<TMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if(p->tmd_skb[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_kfree_skb(p->tmd_skb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) p->tmd_skb[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) free_irq(dev->irq,dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static void cleanup_card(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) disable_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) free_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) release_region(dev->base_addr, cards[p->cardno].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /* set: io,irq,dma or set it when calling insmod */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) static int io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) static int dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * Probe The Card (not the lance-chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct net_device * __init ni65_probe(int unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct net_device *dev = alloc_etherdev(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static const int ports[] = { 0x360, 0x300, 0x320, 0x340, 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) const int *port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (unit >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) sprintf(dev->name, "eth%d", unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) netdev_boot_setup_check(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) irq = dev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dma = dev->dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev->base_addr = io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (dev->base_addr > 0x1ff) { /* Check a single specified location. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) err = ni65_probe1(dev, dev->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) } else if (dev->base_addr > 0) { /* Don't probe at all. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) err = -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) for (port = ports; *port && ni65_probe1(dev, *port); port++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!*port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) err = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) goto out1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) out1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) cleanup_card(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) return ERR_PTR(err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) static const struct net_device_ops ni65_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) .ndo_open = ni65_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) .ndo_stop = ni65_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) .ndo_start_xmit = ni65_send_packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) .ndo_tx_timeout = ni65_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) .ndo_set_rx_mode = set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * this is the real card probe ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static int __init ni65_probe1(struct net_device *dev,int ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) int i,j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) struct priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev->dma = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) for(i=0;i<NUM_CARDS;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if(!request_region(ioaddr, cards[i].total_size, cards[i].cardname))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if(cards[i].id_offset >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) if(inb(ioaddr+cards[i].id_offset+0) != cards[i].id0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) inb(ioaddr+cards[i].id_offset+1) != cards[i].id1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) release_region(ioaddr, cards[i].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if(cards[i].vendor_id) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) for(j=0;j<3;j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if(inb(ioaddr+cards[i].addr_offset+j) != cards[i].vendor_id[j])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) release_region(ioaddr, cards[i].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if(i == NUM_CARDS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for(j=0;j<6;j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dev->dev_addr[j] = inb(ioaddr+cards[i].addr_offset+j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) if( (j=ni65_alloc_buffer(dev)) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) release_region(ioaddr, cards[i].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) return j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) p->cmdr_addr = ioaddr + cards[i].cmd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) p->cardno = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) spin_lock_init(&p->ring_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) printk(KERN_INFO "%s: %s found at %#3x, ", dev->name, cards[p->cardno].cardname , ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if( (j=readreg(CSR0)) != 0x4) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) printk("failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) printk(KERN_ERR "%s: Can't RESET card: %04x\n", dev->name, j);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) release_region(ioaddr, cards[p->cardno].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) outw(88,PORT+L_ADDRREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if(inw(PORT+L_ADDRREG) == 88) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) unsigned long v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) v = inw(PORT+L_DATAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) v <<= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) outw(89,PORT+L_ADDRREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) v |= inw(PORT+L_DATAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) printk("Version %#08lx, ",v);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) p->features = INIT_RING_BEFORE_START;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) printk("ancient LANCE, ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) p->features = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if(test_bit(0,&cards[i].config)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dev->irq = irqtab[(inw(ioaddr+L_CONFIG)>>2)&3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dev->dma = dmatab[inw(ioaddr+L_CONFIG)&3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) printk("IRQ %d (from card), DMA %d (from card).\n",dev->irq,dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) if(dev->dma == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* 'stuck test' from lance.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) unsigned long dma_channels =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ((inb(DMA1_STAT_REG) >> 4) & 0x0f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) | (inb(DMA2_STAT_REG) & 0xf0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for(i=1;i<5;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int dma = dmatab[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if(test_bit(dma,&dma_channels) || request_dma(dma,"ni6510"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) flags=claim_dma_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) disable_dma(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) set_dma_mode(dma,DMA_MODE_CASCADE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) enable_dma(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) release_dma_lock(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) ni65_init_lance(p,dev->dev_addr,0,0); /* trigger memory access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) flags=claim_dma_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) disable_dma(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) free_dma(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) release_dma_lock(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if(readreg(CSR0) & CSR0_IDON)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if(i == 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) printk("failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) printk(KERN_ERR "%s: Can't detect DMA channel!\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) release_region(ioaddr, cards[p->cardno].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev->dma = dmatab[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) printk("DMA %d (autodetected), ",dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) printk("DMA %d (assigned), ",dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) if(dev->irq < 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) unsigned long irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ni65_init_lance(p,dev->dev_addr,0,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) irq_mask = probe_irq_on();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) writereg(CSR0_INIT|CSR0_INEA,CSR0); /* trigger interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) msleep(20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev->irq = probe_irq_off(irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) if(!dev->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) printk("Failed to detect IRQ line!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) release_region(ioaddr, cards[p->cardno].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) printk("IRQ %d (autodetected).\n",dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) printk("IRQ %d (assigned).\n",dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if(request_dma(dev->dma, cards[p->cardno].cardname ) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) printk(KERN_ERR "%s: Can't request dma-channel %d\n",dev->name,(int) dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) release_region(ioaddr, cards[p->cardno].total_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev->base_addr = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev->netdev_ops = &ni65_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) dev->watchdog_timeo = HZ/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return 0; /* everything is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) * set lance register and trigger init
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) static void ni65_init_lance(struct priv *p,unsigned char *daddr,int filter,int mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) u32 pib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) writereg(CSR0_CLRALL|CSR0_STOP,CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) for(i=0;i<6;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) p->ib.eaddr[i] = daddr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) for(i=0;i<8;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) p->ib.filter[i] = filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) p->ib.mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) p->ib.trp = (u32) isa_virt_to_bus(p->tmdhead) | TMDNUMMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) p->ib.rrp = (u32) isa_virt_to_bus(p->rmdhead) | RMDNUMMASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) writereg(0,CSR3); /* busmaster/no word-swap */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pib = (u32) isa_virt_to_bus(&p->ib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) writereg(pib & 0xffff,CSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) writereg(pib >> 16,CSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) writereg(CSR0_INIT,CSR0); /* this changes L_ADDRREG to CSR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) for(i=0;i<32;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) mdelay(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if(inw(PORT+L_DATAREG) & (CSR0_IDON | CSR0_MERR) )
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break; /* init ok ? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * allocate memory area and check the 16MB border
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static void *ni65_alloc_mem(struct net_device *dev,char *what,int size,int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct sk_buff *skb=NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) void *ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if(type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ret = skb = alloc_skb(2+16+size,GFP_KERNEL|GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if(!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) printk(KERN_WARNING "%s: unable to allocate %s memory.\n",dev->name,what);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) skb_reserve(skb,2+16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) skb_put(skb,R_BUF_SIZE); /* grab the whole space .. (not necessary) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) ptr = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) ret = ptr = kmalloc(T_BUF_SIZE,GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if(!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if( (u32) virt_to_phys(ptr+size) > 0x1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) printk(KERN_WARNING "%s: unable to allocate %s memory in lower 16MB!\n",dev->name,what);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if(type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) kfree(ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * allocate all memory structures .. send/recv buffers etc ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) static int ni65_alloc_buffer(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) unsigned char *ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * we need 8-aligned memory ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ptr = ni65_alloc_mem(dev,"BUFFER",sizeof(struct priv)+8,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if(!ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) p = dev->ml_priv = (struct priv *) (((unsigned long) ptr + 7) & ~0x7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) memset((char *)p, 0, sizeof(struct priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) p->self = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) for(i=0;i<TMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) p->tmd_skb[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) p->tmdbounce[i] = ni65_alloc_mem(dev,"XMIT",T_BUF_SIZE,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if(!p->tmdbounce[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for(i=0;i<RMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) #ifdef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) p->recv_skb[i] = ni65_alloc_mem(dev,"RECV",R_BUF_SIZE,1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if(!p->recv_skb[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) p->recvbounce[i] = ni65_alloc_mem(dev,"RECV",R_BUF_SIZE,0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if(!p->recvbounce[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ni65_free_buffer(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) return 0; /* everything is OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) * free buffers and private struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static void ni65_free_buffer(struct priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if(!p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) for(i=0;i<TMDNUM;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) kfree(p->tmdbounce[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dev_kfree_skb(p->tmd_skb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) for(i=0;i<RMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #ifdef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_kfree_skb(p->recv_skb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) kfree(p->recvbounce[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) kfree(p->self);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * stop and (re)start lance .. e.g after an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) static void ni65_stop_start(struct net_device *dev,struct priv *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int csr0 = CSR0_INEA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) writedatareg(CSR0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if(debuglevel > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) printk(KERN_DEBUG "ni65_stop_start\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) if(p->features & INIT_RING_BEFORE_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct sk_buff *skb_save[TMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) unsigned long buffer[TMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) short blen[TMDNUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if(p->xmit_queued) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) while(1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) if((p->tmdhead[p->tmdlast].u.s.status & XMIT_OWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) p->tmdlast = (p->tmdlast + 1) & (TMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) if(p->tmdlast == p->tmdnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) for(i=0;i<TMDNUM;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct tmd *tmdp = p->tmdhead + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) skb_save[i] = p->tmd_skb[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) buffer[i] = (u32) isa_bus_to_virt(tmdp->u.buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) blen[i] = tmdp->blen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) tmdp->u.s.status = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) for(i=0;i<RMDNUM;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct rmd *rmdp = p->rmdhead + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) rmdp->u.s.status = RCV_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) p->tmdnum = p->xmit_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writedatareg(CSR0_STRT | csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) for(i=0;i<TMDNUM;i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) int num = (i + p->tmdlast) & (TMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) p->tmdhead[i].u.buffer = (u32) isa_virt_to_bus((char *)buffer[num]); /* status is part of buffer field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) p->tmdhead[i].blen = blen[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if(p->tmdhead[i].u.s.status & XMIT_OWN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) p->tmdnum = (p->tmdnum + 1) & (TMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) p->xmit_queued = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) writedatareg(CSR0_TDMD | CSR0_INEA | csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) p->tmd_skb[i] = skb_save[num];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) p->rmdnum = p->tmdlast = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if(!p->lock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) if (p->tmdnum || !p->xmit_queued)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) writedatareg(CSR0_STRT | csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * init lance (write init-values .. init-buffers) (open-helper)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int ni65_lance_reinit(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) p->lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) p->xmit_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) flags=claim_dma_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) disable_dma(dev->dma); /* I've never worked with dma, but we do it like the packetdriver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) set_dma_mode(dev->dma,DMA_MODE_CASCADE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) enable_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) release_dma_lock(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) outw(inw(PORT+L_RESET),PORT+L_RESET); /* first: reset the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) if( (i=readreg(CSR0) ) != 0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) printk(KERN_ERR "%s: can't RESET %s card: %04x\n",dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) cards[p->cardno].cardname,(int) i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) flags=claim_dma_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) disable_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) release_dma_lock(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) p->rmdnum = p->tmdnum = p->tmdlast = p->tmdbouncenum = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) for(i=0;i<TMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct tmd *tmdp = p->tmdhead + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if(p->tmd_skb[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_kfree_skb(p->tmd_skb[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) p->tmd_skb[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) tmdp->u.buffer = 0x0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) tmdp->u.s.status = XMIT_START | XMIT_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) tmdp->blen = tmdp->status2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for(i=0;i<RMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) struct rmd *rmdp = p->rmdhead + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #ifdef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) rmdp->u.buffer = (u32) isa_virt_to_bus(p->recv_skb[i]->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) rmdp->u.buffer = (u32) isa_virt_to_bus(p->recvbounce[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rmdp->blen = -(R_BUF_SIZE-8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) rmdp->mlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rmdp->u.s.status = RCV_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if(dev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ni65_init_lance(p,dev->dev_addr,0x00,M_PROM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) else if (netdev_mc_count(dev) || dev->flags & IFF_ALLMULTI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) ni65_init_lance(p,dev->dev_addr,0xff,0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) ni65_init_lance(p,dev->dev_addr,0x00,0x00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * ni65_set_lance_mem() sets L_ADDRREG to CSR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * NOW, WE WILL NEVER CHANGE THE L_ADDRREG, CSR0 IS ALWAYS SELECTED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) if(inw(PORT+L_DATAREG) & CSR0_IDON) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) ni65_set_performance(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* init OK: start lance , enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) writedatareg(CSR0_CLRALL | CSR0_INEA | CSR0_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) return 1; /* ->OK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) printk(KERN_ERR "%s: can't init lance, status: %04x\n",dev->name,(int) inw(PORT+L_DATAREG));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) flags=claim_dma_lock();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) disable_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) release_dma_lock(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) return 0; /* ->Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) * interrupt handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static irqreturn_t ni65_interrupt(int irq, void * dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) int csr0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct priv *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) int bcnt = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) spin_lock(&p->ring_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) while(--bcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) csr0 = inw(PORT+L_DATAREG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) writedatareg( (csr0 & CSR0_CLRALL) ); /* ack interrupts, disable int. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) writedatareg( (csr0 & CSR0_CLRALL) | CSR0_INEA ); /* ack interrupts, interrupts enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if(!(csr0 & (CSR0_ERR | CSR0_RINT | CSR0_TINT)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if(csr0 & CSR0_RINT) /* RECV-int? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) ni65_recv_intr(dev,csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if(csr0 & CSR0_TINT) /* XMIT-int? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) ni65_xmit_intr(dev,csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if(csr0 & CSR0_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if(debuglevel > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) printk(KERN_ERR "%s: general error: %04x.\n",dev->name,csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if(csr0 & CSR0_BABL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) if(csr0 & CSR0_MISS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) for(i=0;i<RMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) printk("%02x ",p->rmdhead[i].u.s.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if(csr0 & CSR0_MERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if(debuglevel > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) printk(KERN_ERR "%s: Ooops .. memory error: %04x.\n",dev->name,csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) ni65_stop_start(dev,p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) #ifdef RCV_PARANOIA_CHECK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) for(j=0;j<RMDNUM;j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) int i, num2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) for(i=RMDNUM-1;i>0;i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) num2 = (p->rmdnum + i) & (RMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if(!(p->rmdhead[num2].u.s.status & RCV_OWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) if(i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) int k, num1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) for(k=0;k<RMDNUM;k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) num1 = (p->rmdnum + k) & (RMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if(!(p->rmdhead[num1].u.s.status & RCV_OWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) if(!k)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) if(debuglevel > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) char buf[256],*buf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) buf1 = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) for(k=0;k<RMDNUM;k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) sprintf(buf1,"%02x ",(p->rmdhead[k].u.s.status)); /* & RCV_OWN) ); */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) buf1 += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) *buf1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) printk(KERN_ERR "%s: Ooops, receive ring corrupted %2d %2d | %s\n",dev->name,p->rmdnum,i,buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) p->rmdnum = num1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ni65_recv_intr(dev,csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) if((p->rmdhead[num2].u.s.status & RCV_OWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) break; /* ok, we are 'in sync' again */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if( (csr0 & (CSR0_RXON | CSR0_TXON)) != (CSR0_RXON | CSR0_TXON) ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) printk(KERN_DEBUG "%s: RX or TX was offline -> restart\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) ni65_stop_start(dev,p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) writedatareg(CSR0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) spin_unlock(&p->ring_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * We have received an Xmit-Interrupt ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * send a new packet if necessary
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) static void ni65_xmit_intr(struct net_device *dev,int csr0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) while(p->xmit_queued)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct tmd *tmdp = p->tmdhead + p->tmdlast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) int tmdstat = tmdp->u.s.status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) if(tmdstat & XMIT_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if(tmdstat & XMIT_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if(tmdp->status2 & XMIT_TDRMASK && debuglevel > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) printk(KERN_ERR "%s: tdr-problems (e.g. no resistor)\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* checking some errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) if(tmdp->status2 & XMIT_RTRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) if(tmdp->status2 & XMIT_LCAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if(tmdp->status2 & (XMIT_BUFF | XMIT_UFLO )) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) /* this stops the xmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if(debuglevel > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) printk(KERN_ERR "%s: Xmit FIFO/BUFF error\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if(p->features & INIT_RING_BEFORE_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) tmdp->u.s.status = XMIT_OWN | XMIT_START | XMIT_END; /* test: resend this frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ni65_stop_start(dev,p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) break; /* no more Xmit processing .. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) ni65_stop_start(dev,p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) if(debuglevel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) printk(KERN_ERR "%s: xmit-error: %04x %02x-%04x\n",dev->name,csr0,(int) tmdstat,(int) tmdp->status2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if(!(csr0 & CSR0_BABL)) /* don't count errors twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) tmdp->status2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) dev->stats.tx_bytes -= (short)(tmdp->blen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if(p->tmd_skb[p->tmdlast]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_consume_skb_irq(p->tmd_skb[p->tmdlast]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) p->tmd_skb[p->tmdlast] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) p->tmdlast = (p->tmdlast + 1) & (TMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) if(p->tmdlast == p->tmdnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) p->xmit_queued = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) * We have received a packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) static void ni65_recv_intr(struct net_device *dev,int csr0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct rmd *rmdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) int rmdstat,len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) int cnt=0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) rmdp = p->rmdhead + p->rmdnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) while(!( (rmdstat = rmdp->u.s.status) & RCV_OWN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) cnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if( (rmdstat & (RCV_START | RCV_END | RCV_ERR)) != (RCV_START | RCV_END) ) /* error or oversized? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if(!(rmdstat & RCV_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) if(rmdstat & RCV_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) printk(KERN_ERR "%s: recv, packet too long: %d\n",dev->name,rmdp->mlen & 0x0fff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if(debuglevel > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) printk(KERN_ERR "%s: receive-error: %04x, lance-status: %04x/%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dev->name,(int) rmdstat,csr0,(int) inw(PORT+L_DATAREG) );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) if(rmdstat & RCV_FRAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if(rmdstat & RCV_OFLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if(rmdstat & RCV_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) if(rmdstat & RCV_BUF_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if(!(csr0 & CSR0_MISS)) /* don't count errors twice */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) else if( (len = (rmdp->mlen & 0x0fff) - 4) >= 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) #ifdef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct sk_buff *skb = alloc_skb(R_BUF_SIZE+2+16,GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) skb_reserve(skb,16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct sk_buff *skb = netdev_alloc_skb(dev, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if(skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) skb_reserve(skb,2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) #ifdef RCV_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if( (unsigned long) (skb->data + R_BUF_SIZE) > 0x1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) skb_put(skb,len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) skb_copy_to_linear_data(skb, (unsigned char *)(p->recv_skb[p->rmdnum]->data),len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct sk_buff *skb1 = p->recv_skb[p->rmdnum];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) skb_put(skb,R_BUF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) p->recv_skb[p->rmdnum] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) rmdp->u.buffer = (u32) isa_virt_to_bus(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) skb = skb1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) skb_trim(skb,len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) skb_put(skb,len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) skb_copy_to_linear_data(skb, (unsigned char *) p->recvbounce[p->rmdnum],len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) skb->protocol=eth_type_trans(skb,dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) printk(KERN_ERR "%s: can't alloc new sk_buff\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) printk(KERN_INFO "%s: received runt packet\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) rmdp->blen = -(R_BUF_SIZE-8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) rmdp->mlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) rmdp->u.s.status = RCV_OWN; /* change owner */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) p->rmdnum = (p->rmdnum + 1) & (RMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) rmdp = p->rmdhead + p->rmdnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * kick xmitter ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static void ni65_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) printk(KERN_ERR "%s: xmitter timed out, try to restart!\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) for(i=0;i<TMDNUM;i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) printk("%02x ",p->tmdhead[i].u.s.status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) ni65_lance_reinit(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) * Send a packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) static netdev_tx_t ni65_send_packet(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) struct priv *p = dev->ml_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) if (test_and_set_bit(0, (void*)&p->lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) printk(KERN_ERR "%s: Queue was locked.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) short len = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) struct tmd *tmdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if( (unsigned long) (skb->data + skb->len) > 0x1000000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) skb_copy_from_linear_data(skb, p->tmdbounce[p->tmdbouncenum],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) skb->len > T_BUF_SIZE ? T_BUF_SIZE :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (len > skb->len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) memset((char *)p->tmdbounce[p->tmdbouncenum]+skb->len, 0, len-skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) dev_kfree_skb (skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) spin_lock_irqsave(&p->ring_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) tmdp = p->tmdhead + p->tmdnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) tmdp->u.buffer = (u32) isa_virt_to_bus(p->tmdbounce[p->tmdbouncenum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) p->tmdbouncenum = (p->tmdbouncenum + 1) & (TMDNUM - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) #ifdef XMT_VIA_SKB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) spin_lock_irqsave(&p->ring_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) tmdp = p->tmdhead + p->tmdnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) tmdp->u.buffer = (u32) isa_virt_to_bus(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) p->tmd_skb[p->tmdnum] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) tmdp->blen = -len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) tmdp->u.s.status = XMIT_OWN | XMIT_START | XMIT_END;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) writedatareg(CSR0_TDMD | CSR0_INEA); /* enable xmit & interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) p->xmit_queued = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) p->tmdnum = (p->tmdnum + 1) & (TMDNUM-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if(p->tmdnum != p->tmdlast)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) p->lock = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) spin_unlock_irqrestore(&p->ring_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) static void set_multicast_list(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if(!ni65_lance_reinit(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) printk(KERN_ERR "%s: Can't switch card into MC mode!\n",dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) static struct net_device *dev_ni65;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) module_param_hw(irq, int, irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) module_param_hw(io, int, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) module_param_hw(dma, int, dma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) MODULE_PARM_DESC(irq, "ni6510 IRQ number (ignored for some cards)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) MODULE_PARM_DESC(io, "ni6510 I/O base address");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) MODULE_PARM_DESC(dma, "ni6510 ISA DMA channel (ignored for some cards)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) int __init init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) dev_ni65 = ni65_probe(-1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) return PTR_ERR_OR_ZERO(dev_ni65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) void __exit cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) unregister_netdev(dev_ni65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) cleanup_card(dev_ni65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) free_netdev(dev_ni65);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) #endif /* MODULE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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