^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Lance ethernet driver for the MIPS processor based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * DECstation family
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * adopted from sunlance.c by Richard van den Berg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (C) 2002, 2003, 2005, 2006 Maciej W. Rozycki
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * additional sources:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * - PMAD-AA TURBOchannel Ethernet Module Functional Specification,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Revision 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * v0.001: The kernel accepts the code and it shows the hardware address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * v0.002: Removed most sparc stuff, left only some module and dma stuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * v0.003: Enhanced base address calculation from proposals by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Harald Koerfgen and Thomas Riemer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * v0.004: lance-regs is pointing at the right addresses, added prom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * check. First start of address mapping and DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * v0.005: started to play around with LANCE-DMA. This driver will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * work for non IOASIC lances. HK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * v0.006: added pointer arrays to lance_private and setup routine for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * them in dec_lance_init. HK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * v0.007: Big shit. The LANCE seems to use a different DMA mechanism to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * access the init block. This looks like one (short) word at a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * time, but the smallest amount the IOASIC can transfer is a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * (long) word. So we have a 2-2 padding here. Changed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * lance_init_block accordingly. The 16-16 padding for the buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * seems to be correct. HK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * v0.008: mods to make PMAX_LANCE work. 01/09/1999 triemer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * v0.009: Module support fixes, multiple interfaces support, various
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * bits. macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * v0.010: Fixes for the PMAD mapping of the LANCE buffer and for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * PMAX requirement to only use halfword accesses to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * buffer. macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * v0.011: Converted the PMAD to the driver model. macro
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/if_ether.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/stddef.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/tc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <asm/addrspace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <asm/dec/interrupts.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <asm/dec/ioasic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm/dec/ioasic_addrs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <asm/dec/kn01.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <asm/dec/machtype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <asm/dec/system.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "declance.c: v0.011 by Linux MIPS DECstation task force\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_AUTHOR("Linux MIPS DECstation task force");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_DESCRIPTION("DEC LANCE (DECstation onboard, PMAD-xx) driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define __unused __attribute__ ((unused))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * card types
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ASIC_LANCE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PMAD_LANCE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PMAX_LANCE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LE_CSR0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LE_CSR1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LE_CSR2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LE_CSR3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LE_MO_PROM 0x8000 /* Enable promiscuous mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LE_C0_ERR 0x8000 /* Error: set if BAB, SQE, MISS or ME is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LE_C0_BABL 0x4000 /* BAB: Babble: tx timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LE_C0_CERR 0x2000 /* SQE: Signal quality error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LE_C0_MISS 0x1000 /* MISS: Missed a packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LE_C0_MERR 0x0800 /* ME: Memory error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LE_C0_RINT 0x0400 /* Received interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LE_C0_TINT 0x0200 /* Transmitter Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LE_C0_IDON 0x0100 /* IFIN: Init finished. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LE_C0_INTR 0x0080 /* Interrupt or error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LE_C0_INEA 0x0040 /* Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LE_C0_RXON 0x0020 /* Receiver on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LE_C0_TXON 0x0010 /* Transmitter on */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LE_C0_TDMD 0x0008 /* Transmitter demand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LE_C0_STOP 0x0004 /* Stop the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define LE_C0_STRT 0x0002 /* Start the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LE_C0_INIT 0x0001 /* Init the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define LE_C3_BSWP 0x4 /* SWAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LE_C3_ACON 0x2 /* ALE Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LE_C3_BCON 0x1 /* Byte control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Receive message descriptor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LE_R1_OWN 0x8000 /* Who owns the entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LE_R1_ERR 0x4000 /* Error: if FRA, OFL, CRC or BUF is set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LE_R1_FRA 0x2000 /* FRA: Frame error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LE_R1_OFL 0x1000 /* OFL: Frame overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LE_R1_CRC 0x0800 /* CRC error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LE_R1_BUF 0x0400 /* BUF: Buffer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LE_R1_SOP 0x0200 /* Start of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LE_R1_EOP 0x0100 /* End of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LE_R1_POK 0x0300 /* Packet is complete: SOP + EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Transmit message descriptor 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LE_T1_OWN 0x8000 /* Lance owns the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LE_T1_ERR 0x4000 /* Error summary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LE_T1_EMORE 0x1000 /* Error: more than one retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LE_T1_EONE 0x0800 /* Error: one retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define LE_T1_EDEF 0x0400 /* Error: deferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define LE_T1_SOP 0x0200 /* Start of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define LE_T1_EOP 0x0100 /* End of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define LE_T1_POK 0x0300 /* Packet is complete: SOP + EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LE_T3_BUF 0x8000 /* Buffer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LE_T3_UFL 0x4000 /* Error underflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LE_T3_LCOL 0x1000 /* Error late collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LE_T3_CLOS 0x0800 /* Error carrier loss */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LE_T3_RTY 0x0400 /* Error retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Define: 2^4 Tx buffers and 2^4 Rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #ifndef LANCE_LOG_TX_BUFFERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LANCE_LOG_TX_BUFFERS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LANCE_LOG_RX_BUFFERS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TX_RING_SIZE (1 << (LANCE_LOG_TX_BUFFERS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define RX_RING_SIZE (1 << (LANCE_LOG_RX_BUFFERS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PKT_BUF_SZ 1536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define RX_BUFF_SIZE PKT_BUF_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TX_BUFF_SIZE PKT_BUF_SZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #undef TEST_HITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ZERO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * The DS2100/3100 have a linear 64 kB buffer which supports halfword
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * accesses only. Each halfword of the buffer is word-aligned in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * CPU address space.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * The PMAD-AA has a 128 kB buffer on-board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * The IOASIC LANCE devices use a shared memory region. This region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * as seen from the CPU is (max) 128 kB long and has to be on an 128 kB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * boundary. The LANCE sees this as a 64 kB long continuous memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * region.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * The LANCE's DMA address is used as an index in this buffer and DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * takes place in bursts of eight 16-bit words which are packed into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * four 32-bit words by the IOASIC. This leads to a strange padding:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * 16 bytes of valid data followed by a 16 byte gap :-(.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct lance_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned short rmd0; /* low address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned short rmd1; /* high address of packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) and descriptor bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) short length; /* 2s complement (negative!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) of buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) unsigned short mblength; /* actual number of bytes received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct lance_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) unsigned short tmd0; /* low address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) unsigned short tmd1; /* high address of packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) and descriptor bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) short length; /* 2s complement (negative!)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) of buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) unsigned short misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* First part of the LANCE initialization block, described in databook. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct lance_init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) unsigned short mode; /* pre-set mode (reg. 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned short phys_addr[3]; /* physical ethernet address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned short filter[4]; /* multicast filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Receive and transmit ring base, along with extra bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) unsigned short rx_ptr; /* receive descriptor addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) unsigned short rx_len; /* receive len and high addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) unsigned short tx_ptr; /* transmit descriptor addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) unsigned short tx_len; /* transmit len and high addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) short gap[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* The buffer descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct lance_rx_desc brx_ring[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct lance_tx_desc btx_ring[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define BUF_OFFSET_CPU sizeof(struct lance_init_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define BUF_OFFSET_LNC sizeof(struct lance_init_block)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define shift_off(off, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) (type == ASIC_LANCE || type == PMAX_LANCE ? off << 1 : off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define lib_off(rt, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) shift_off(offsetof(struct lance_init_block, rt), type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define lib_ptr(ib, rt, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ((volatile u16 *)((u8 *)(ib) + lib_off(rt, type)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define rds_off(rt, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) shift_off(offsetof(struct lance_rx_desc, rt), type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define rds_ptr(rd, rt, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ((volatile u16 *)((u8 *)(rd) + rds_off(rt, type)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define tds_off(rt, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) shift_off(offsetof(struct lance_tx_desc, rt), type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define tds_ptr(td, rt, type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ((volatile u16 *)((u8 *)(td) + tds_off(rt, type)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct lance_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct net_device *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int dma_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) volatile struct lance_regs *ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) int rx_new, tx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int rx_old, tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned short busmaster_regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct timer_list multicast_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* Pointers to the ring buffers as seen from the CPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) char *rx_buf_ptr_cpu[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) char *tx_buf_ptr_cpu[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* Pointers to the ring buffers as seen from the LANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) uint rx_buf_ptr_lnc[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) uint tx_buf_ptr_lnc[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TX_BUFFS_AVAIL ((lp->tx_old<=lp->tx_new)?\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) lp->tx_old+TX_RING_MOD_MASK-lp->tx_new:\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) lp->tx_old - lp->tx_new-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* The lance control ports are at an absolute address, machine and tc-slot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * dependent.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * DECstations do only 32-bit access and the LANCE uses 16 bit addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * so we have to give the structure an extra member making rap pointing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * at the right address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct lance_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) volatile unsigned short rdp; /* register data port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned short pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) volatile unsigned short rap; /* register address port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int dec_lance_debug = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static struct tc_driver dec_lance_tc_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) static struct net_device *root_lance_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline void writereg(volatile unsigned short *regptr, short value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) *regptr = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Load the CSR registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static void load_csrs(struct lance_private *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) uint leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* The address space as seen from the LANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * begins at address 0. HK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) leptr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) writereg(&ll->rap, LE_CSR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) writereg(&ll->rdp, (leptr & 0xFFFF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writereg(&ll->rap, LE_CSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) writereg(&ll->rdp, leptr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) writereg(&ll->rap, LE_CSR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) writereg(&ll->rdp, lp->busmaster_regval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* Point back to csr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * Our specialized copy routines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void cp_to_buf(const int type, void *to, const void *from, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) unsigned short *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) const unsigned short *fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned short clen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned char *rtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) const unsigned char *rfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (type == PMAD_LANCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) memcpy(to, from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) } else if (type == PMAX_LANCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) clen = len >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) tp = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) fp = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) tp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) clen = len & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) rtp = (unsigned char *)tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) rfp = (const unsigned char *)fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) *rtp++ = *rfp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * copy 16 Byte chunks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) clen = len >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) tp = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) fp = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) tp += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * do the rest, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) clen = len & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) rtp = (unsigned char *)tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) rfp = (const unsigned char *)fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) *rtp++ = *rfp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) static void cp_from_buf(const int type, void *to, const void *from, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned short *tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) const unsigned short *fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned short clen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned char *rtp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) const unsigned char *rfp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (type == PMAD_LANCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) memcpy(to, from, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) } else if (type == PMAX_LANCE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) clen = len >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) tp = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) fp = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) clen = len & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) rtp = (unsigned char *)tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) rfp = (const unsigned char *)fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) *rtp++ = *rfp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * copy 16 Byte chunks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) clen = len >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) tp = to;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) fp = from;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) *tp++ = *fp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) fp += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * do the rest, if any.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) clen = len & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) rtp = (unsigned char *)tp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) rfp = (const unsigned char *)fp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) while (clen--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) *rtp++ = *rfp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /* Setup the Lance Rx and Tx rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void lance_init_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) uint leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* Lock out other processes while setting up hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) lp->rx_new = lp->tx_new = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) lp->rx_old = lp->tx_old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* Copy the ethernet address to the lance init block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * XXX bit 0 of the physical address registers has to be zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) *lib_ptr(ib, phys_addr[0], lp->type) = (dev->dev_addr[1] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev->dev_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) *lib_ptr(ib, phys_addr[1], lp->type) = (dev->dev_addr[3] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) dev->dev_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) *lib_ptr(ib, phys_addr[2], lp->type) = (dev->dev_addr[5] << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev->dev_addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Setup the initialization block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Setup rx descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) leptr = offsetof(struct lance_init_block, brx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) *lib_ptr(ib, rx_len, lp->type) = (LANCE_LOG_RX_BUFFERS << 13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) (leptr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) *lib_ptr(ib, rx_ptr, lp->type) = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) printk("RX ptr: %8.8x(%8.8x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) leptr, (uint)lib_off(brx_ring, lp->type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) /* Setup tx descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) leptr = offsetof(struct lance_init_block, btx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) *lib_ptr(ib, tx_len, lp->type) = (LANCE_LOG_TX_BUFFERS << 13) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (leptr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) *lib_ptr(ib, tx_ptr, lp->type) = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) if (ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) printk("TX ptr: %8.8x(%8.8x)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) leptr, (uint)lib_off(btx_ring, lp->type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) printk("TX rings:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Setup the Tx ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) leptr = lp->tx_buf_ptr_lnc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *lib_ptr(ib, btx_ring[i].tmd0, lp->type) = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *lib_ptr(ib, btx_ring[i].tmd1, lp->type) = (leptr >> 16) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) *lib_ptr(ib, btx_ring[i].length, lp->type) = 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* The ones required by tmd2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) *lib_ptr(ib, btx_ring[i].misc, lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (i < 3 && ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) printk("%d: %8.8x(%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) i, leptr, lp->tx_buf_ptr_cpu[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) /* Setup the Rx ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) printk("RX rings:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) leptr = lp->rx_buf_ptr_lnc[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) *lib_ptr(ib, brx_ring[i].rmd0, lp->type) = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *lib_ptr(ib, brx_ring[i].rmd1, lp->type) = ((leptr >> 16) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) LE_R1_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) *lib_ptr(ib, brx_ring[i].length, lp->type) = -RX_BUFF_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) *lib_ptr(ib, brx_ring[i].mblength, lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (i < 3 && ZERO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) printk("%d: %8.8x(%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) i, leptr, lp->rx_buf_ptr_cpu[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static int init_restart_lance(struct lance_private *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) writereg(&ll->rdp, LE_C0_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Wait for the lance to complete initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (i = 0; (i < 100) && !(ll->rdp & LE_C0_IDON); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if ((i == 100) || (ll->rdp & LE_C0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) printk("LANCE unopened after %d ticks, csr0=%4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) i, ll->rdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if ((ll->rdp & LE_C0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) printk("LANCE unopened after %d ticks, csr0=%4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) i, ll->rdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) writereg(&ll->rdp, LE_C0_IDON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writereg(&ll->rdp, LE_C0_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) writereg(&ll->rdp, LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) static int lance_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) volatile u16 *rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) unsigned short bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) int entry, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #ifdef TEST_HITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) printk("[");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (i == lp->rx_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) printk("%s", *lib_ptr(ib, brx_ring[i].rmd1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) lp->type) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) LE_R1_OWN ? "_" : "X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) printk("%s", *lib_ptr(ib, brx_ring[i].rmd1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) lp->type) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) LE_R1_OWN ? "." : "1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) printk("]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) for (rd = lib_ptr(ib, brx_ring[lp->rx_new], lp->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) !((bits = *rds_ptr(rd, rmd1, lp->type)) & LE_R1_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) rd = lib_ptr(ib, brx_ring[lp->rx_new], lp->type)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) entry = lp->rx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* We got an incomplete frame? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if ((bits & LE_R1_POK) != LE_R1_POK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else if (bits & LE_R1_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* Count only the end frame as a rx error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * not the beginning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (bits & LE_R1_BUF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (bits & LE_R1_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (bits & LE_R1_OFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (bits & LE_R1_FRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) if (bits & LE_R1_EOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) len = (*rds_ptr(rd, mblength, lp->type) & 0xfff) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) skb = netdev_alloc_skb(dev, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) *rds_ptr(rd, mblength, lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) *rds_ptr(rd, rmd1, lp->type) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) ((lp->rx_buf_ptr_lnc[entry] >> 16) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 0xff) | LE_R1_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) lp->rx_new = (entry + 1) & RX_RING_MOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) skb_reserve(skb, 2); /* 16 byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) skb_put(skb, len); /* make room */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cp_from_buf(lp->type, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) lp->rx_buf_ptr_cpu[entry], len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /* Return the packet to the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) *rds_ptr(rd, mblength, lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) *rds_ptr(rd, length, lp->type) = -RX_BUFF_SIZE | 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *rds_ptr(rd, rmd1, lp->type) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ((lp->rx_buf_ptr_lnc[entry] >> 16) & 0xff) | LE_R1_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) lp->rx_new = (entry + 1) & RX_RING_MOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) static void lance_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) volatile u16 *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) j = lp->tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spin_lock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) for (i = j; i != lp->tx_new; i = j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) td = lib_ptr(ib, btx_ring[i], lp->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* If we hit a packet not owned by us, stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (*tds_ptr(td, tmd1, lp->type) & LE_T1_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (*tds_ptr(td, tmd1, lp->type) & LE_T1_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) status = *tds_ptr(td, misc, lp->type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (status & LE_T3_RTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (status & LE_T3_LCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) if (status & LE_T3_CLOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) printk("%s: Carrier Lost\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* Stop the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* Buffer errors and underflows turn off the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) * transmitter, restart the adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (status & (LE_T3_BUF | LE_T3_UFL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) printk("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Stop the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } else if ((*tds_ptr(td, tmd1, lp->type) & LE_T1_POK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) LE_T1_POK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * So we don't count the packet more than once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) *tds_ptr(td, tmd1, lp->type) &= ~(LE_T1_POK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /* One collision before packet was sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (*tds_ptr(td, tmd1, lp->type) & LE_T1_EONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* More than one collision, be optimistic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (*tds_ptr(td, tmd1, lp->type) & LE_T1_EMORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev->stats.collisions += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) j = (j + 1) & TX_RING_MOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) lp->tx_old = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (netif_queue_stopped(dev) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) TX_BUFFS_AVAIL > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) spin_unlock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static irqreturn_t lance_dma_merr_int(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) printk(KERN_ERR "%s: DMA error\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static irqreturn_t lance_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) int csr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) csr0 = ll->rdp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Acknowledge all the interrupt sources ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) writereg(&ll->rdp, csr0 & (LE_C0_INTR | LE_C0_TINT | LE_C0_RINT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) if ((csr0 & LE_C0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Clear the error condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) writereg(&ll->rdp, LE_C0_BABL | LE_C0_ERR | LE_C0_MISS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) LE_C0_CERR | LE_C0_MERR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) if (csr0 & LE_C0_RINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) lance_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) if (csr0 & LE_C0_TINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) lance_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (csr0 & LE_C0_BABL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) if (csr0 & LE_C0_MISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) if (csr0 & LE_C0_MERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) printk("%s: Memory error, status %04x\n", dev->name, csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) writereg(&ll->rdp, LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) writereg(&ll->rdp, LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static int lance_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) /* Stop the Lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /* Set mode and clear multicast filter only at device open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * so that lance_init_ring() called at any error will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * forget multicast filters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) * BTW it is common bug in all lance drivers! --ANK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) *lib_ptr(ib, mode, lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *lib_ptr(ib, filter[0], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) *lib_ptr(ib, filter[1], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) *lib_ptr(ib, filter[2], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) *lib_ptr(ib, filter[3], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) /* Associate IRQ with lance_interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (request_irq(dev->irq, lance_interrupt, 0, "lance", dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) printk("%s: Can't get IRQ %d\n", dev->name, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (lp->dma_irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (request_irq(lp->dma_irq, lance_dma_merr_int, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "lance error", dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) printk("%s: Can't get DMA IRQ %d\n", dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) lp->dma_irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) spin_lock_irqsave(&ioasic_ssr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) fast_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* Enable I/O ASIC LANCE DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) ioasic_write(IO_REG_SSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) ioasic_read(IO_REG_SSR) | IO_SSR_LANCE_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) fast_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) spin_unlock_irqrestore(&ioasic_ssr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) status = init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int lance_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) del_timer_sync(&lp->multicast_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Stop the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (lp->dma_irq >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) spin_lock_irqsave(&ioasic_ssr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) fast_mb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) /* Disable I/O ASIC LANCE DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) ioasic_write(IO_REG_SSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) ioasic_read(IO_REG_SSR) & ~IO_SSR_LANCE_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) fast_iob();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) spin_unlock_irqrestore(&ioasic_ssr_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) free_irq(lp->dma_irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static inline int lance_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /* Stop the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) status = init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) static void lance_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) printk(KERN_ERR "%s: transmit timed out, status %04x, reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dev->name, ll->rdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) lance_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static netdev_tx_t lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) int entry, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) len = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (len < ETH_ZLEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (skb_padto(skb, ETH_ZLEN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) len = ETH_ZLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev->stats.tx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) spin_lock_irqsave(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) entry = lp->tx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) *lib_ptr(ib, btx_ring[entry].length, lp->type) = (-len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) *lib_ptr(ib, btx_ring[entry].misc, lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) cp_to_buf(lp->type, lp->tx_buf_ptr_cpu[entry], skb->data, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* Now, give the packet to the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) *lib_ptr(ib, btx_ring[entry].tmd1, lp->type) =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) ((lp->tx_buf_ptr_lnc[entry] >> 16) & 0xff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) (LE_T1_POK | LE_T1_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) lp->tx_new = (entry + 1) & TX_RING_MOD_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (TX_BUFFS_AVAIL <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Kick the lance: transmit now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) writereg(&ll->rdp, LE_C0_INEA | LE_C0_TDMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) spin_unlock_irqrestore(&lp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) static void lance_load_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* set all multicast bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) *lib_ptr(ib, filter[0], lp->type) = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) *lib_ptr(ib, filter[1], lp->type) = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) *lib_ptr(ib, filter[2], lp->type) = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) *lib_ptr(ib, filter[3], lp->type) = 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* clear the multicast filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) *lib_ptr(ib, filter[0], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) *lib_ptr(ib, filter[1], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) *lib_ptr(ib, filter[2], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) *lib_ptr(ib, filter[3], lp->type) = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /* Add addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) crc = ether_crc_le(ETH_ALEN, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) crc = crc >> 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) *lib_ptr(ib, filter[crc >> 4], lp->type) |= 1 << (crc & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static void lance_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) volatile u16 *ib = (volatile u16 *)dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) volatile struct lance_regs *ll = lp->ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!netif_running(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (lp->tx_old != lp->tx_new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) mod_timer(&lp->multicast_timer, jiffies + 4 * HZ/100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) writereg(&ll->rap, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writereg(&ll->rdp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) *lib_ptr(ib, mode, lp->type) |= LE_MO_PROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) *lib_ptr(ib, mode, lp->type) &= ~LE_MO_PROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) lance_load_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) static void lance_set_multicast_retry(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) struct lance_private *lp = from_timer(lp, t, multicast_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) struct net_device *dev = lp->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) lance_set_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) static const struct net_device_ops lance_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) .ndo_open = lance_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) .ndo_stop = lance_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) .ndo_start_xmit = lance_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) .ndo_tx_timeout = lance_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) .ndo_set_rx_mode = lance_set_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int dec_lance_probe(struct device *bdev, const int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static unsigned version_printed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) static const char fmt[] = "declance%d";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) char name[10];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) struct lance_private *lp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) volatile struct lance_regs *ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) resource_size_t start = 0, len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) unsigned long esar_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) unsigned char *esar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) const char *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (dec_lance_debug && version_printed++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) printk(version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (bdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) snprintf(name, sizeof(name), "%s", dev_name(bdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) dev = root_lance_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) while (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev = lp->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) snprintf(name, sizeof(name), fmt, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) dev = alloc_etherdev(sizeof(struct lance_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * alloc_etherdev ensures the data structures used by the LANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) * are aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) spin_lock_init(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) lp->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case ASIC_LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) dev->base_addr = CKSEG1ADDR(dec_kn_slot_base + IOASIC_LANCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) /* buffer space for the on-board LANCE shared memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * FIXME: ugly hack!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) dev->mem_start = CKSEG1ADDR(0x00020000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) dev->mem_end = dev->mem_start + 0x00020000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev->irq = dec_interrupt[DEC_IRQ_LANCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) esar_base = CKSEG1ADDR(dec_kn_slot_base + IOASIC_ESAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* Workaround crash with booting KN04 2.1k from Disk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) memset((void *)dev->mem_start, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) dev->mem_end - dev->mem_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * setup the pointer arrays, this sucks [tm] :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) lp->rx_buf_ptr_cpu[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) 2 * i * RX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) lp->rx_buf_ptr_lnc[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) (BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) lp->tx_buf_ptr_cpu[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) 2 * RX_RING_SIZE * RX_BUFF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) 2 * i * TX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) lp->tx_buf_ptr_lnc[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) (BUF_OFFSET_LNC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) RX_RING_SIZE * RX_BUFF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) i * TX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) /* Setup I/O ASIC LANCE DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) lp->dma_irq = dec_interrupt[DEC_IRQ_LANCE_MERR];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) ioasic_write(IO_REG_LANCE_DMA_P,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) CPHYSADDR(dev->mem_start) << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) #ifdef CONFIG_TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) case PMAD_LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) dev_set_drvdata(bdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) start = to_tc_dev(bdev)->resource.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) len = to_tc_dev(bdev)->resource.end - start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) if (!request_mem_region(start, len, dev_name(bdev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "%s: Unable to reserve MMIO resource\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) dev_name(bdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) goto err_out_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dev->mem_start = CKSEG1ADDR(start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) dev->mem_end = dev->mem_start + 0x100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) dev->base_addr = dev->mem_start + 0x100000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) dev->irq = to_tc_dev(bdev)->interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) esar_base = dev->mem_start + 0x1c0002;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) lp->dma_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) lp->rx_buf_ptr_cpu[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) (char *)(dev->mem_start + BUF_OFFSET_CPU +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) i * RX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) lp->rx_buf_ptr_lnc[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) (BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) lp->tx_buf_ptr_cpu[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) (char *)(dev->mem_start + BUF_OFFSET_CPU +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) RX_RING_SIZE * RX_BUFF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) i * TX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) lp->tx_buf_ptr_lnc[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) (BUF_OFFSET_LNC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) RX_RING_SIZE * RX_BUFF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) i * TX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) case PMAX_LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev->irq = dec_interrupt[DEC_IRQ_LANCE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) dev->base_addr = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dev->mem_start = CKSEG1ADDR(KN01_SLOT_BASE + KN01_LANCE_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) dev->mem_end = dev->mem_start + KN01_SLOT_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) esar_base = CKSEG1ADDR(KN01_SLOT_BASE + KN01_ESAR + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) lp->dma_irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) * setup the pointer arrays, this sucks [tm] :-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) lp->rx_buf_ptr_cpu[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) 2 * i * RX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) lp->rx_buf_ptr_lnc[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) (BUF_OFFSET_LNC + i * RX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) lp->tx_buf_ptr_cpu[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) (char *)(dev->mem_start + 2 * BUF_OFFSET_CPU +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) 2 * RX_RING_SIZE * RX_BUFF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) 2 * i * TX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) lp->tx_buf_ptr_lnc[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) (BUF_OFFSET_LNC +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) RX_RING_SIZE * RX_BUFF_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) i * TX_BUFF_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) printk(KERN_ERR "%s: declance_init called with unknown type\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) goto err_out_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ll = (struct lance_regs *) dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) esar = (unsigned char *) esar_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) /* prom checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) /* First, check for test pattern */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (esar[0x60] != 0xff && esar[0x64] != 0x00 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) esar[0x68] != 0x55 && esar[0x6c] != 0xaa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "%s: Ethernet station address prom not found!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) goto err_out_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* Check the prom contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) for (i = 0; i < 8; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (esar[i * 4] != esar[0x3c - i * 4] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) esar[i * 4] != esar[0x40 + i * 4] &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) esar[0x3c - i * 4] != esar[0x40 + i * 4]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) printk(KERN_ERR "%s: Something is wrong with the "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) "ethernet station address prom!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) goto err_out_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) /* Copy the ethernet address to the device structure, later to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) * lance initialization block so the lance gets it every time it's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) * (re)initialized.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) case ASIC_LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) desc = "IOASIC onboard LANCE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) case PMAD_LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) desc = "PMAD-AA";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) case PMAX_LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) desc = "PMAX onboard LANCE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) dev->dev_addr[i] = esar[i * 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) printk("%s: %s, addr = %pM, irq = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) name, desc, dev->dev_addr, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dev->netdev_ops = &lance_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) dev->watchdog_timeo = 5*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) /* lp->ll is the location of the registers for lance card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) lp->ll = ll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) /* busmaster_regval (CSR3) should be zero according to the PMAD-AA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) * specification.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) lp->busmaster_regval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) dev->dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) /* We cannot sleep if the chip is busy during a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) * multicast list update event, because such events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) * can occur from interrupts (ex. IPv6). So we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) * use a timer to try again later when necessary. -DaveM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) lp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) timer_setup(&lp->multicast_timer, lance_set_multicast_retry, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) printk(KERN_ERR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) "%s: Unable to register netdev, aborting.\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) goto err_out_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!bdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) lp->next = root_lance_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) root_lance_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) printk("%s: registered as %s.\n", name, dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) err_out_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (bdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) release_mem_region(start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) err_out_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* Find all the lance cards on the system and initialize them */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) static int __init dec_lance_platform_probe(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (dec_interrupt[DEC_IRQ_LANCE] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) if (dec_interrupt[DEC_IRQ_LANCE_MERR] >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) if (dec_lance_probe(NULL, ASIC_LANCE) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) } else if (!TURBOCHANNEL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (dec_lance_probe(NULL, PMAX_LANCE) >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return (count > 0) ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static void __exit dec_lance_platform_remove(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) while (root_lance_dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) struct net_device *dev = root_lance_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) root_lance_dev = lp->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) #ifdef CONFIG_TC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) static int dec_lance_tc_probe(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static int dec_lance_tc_remove(struct device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static const struct tc_device_id dec_lance_tc_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) { "DEC ", "PMAD-AA " },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) MODULE_DEVICE_TABLE(tc, dec_lance_tc_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) static struct tc_driver dec_lance_tc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) .id_table = dec_lance_tc_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) .name = "declance",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) .bus = &tc_bus_type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) .probe = dec_lance_tc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) .remove = dec_lance_tc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) static int dec_lance_tc_probe(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) int status = dec_lance_probe(dev, PMAD_LANCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) get_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static void dec_lance_remove(struct device *bdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct net_device *dev = dev_get_drvdata(bdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) resource_size_t start, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) start = to_tc_dev(bdev)->resource.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) len = to_tc_dev(bdev)->resource.end - start + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) release_mem_region(start, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int dec_lance_tc_remove(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) put_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) dec_lance_remove(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) static int __init dec_lance_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) status = tc_register_driver(&dec_lance_tc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dec_lance_platform_probe();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static void __exit dec_lance_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) dec_lance_platform_remove();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) tc_unregister_driver(&dec_lance_tc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) module_init(dec_lance_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) module_exit(dec_lance_exit);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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