^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Amiga Linux/m68k Ariadne Ethernet Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * © Copyright 1995 by Geert Uytterhoeven (geert@linux-m68k.org)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Peter De Schrijver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (Peter.DeSchrijver@linux.cc.kuleuven.ac.be)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * ----------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * This program is based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * lance.c: An AMD LANCE ethernet driver for linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Written 1993-94 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * Advanced Micro Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Publication #16907, Rev. B, Amendment/0, May 1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * MC68230: Parallel Interface/Timer (PI/T)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * Motorola Semiconductors, December, 1983
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * ----------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * License. See the file COPYING in the main directory of the Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * distribution for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * ----------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The Ariadne is a Zorro-II board made by Village Tronic. It contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * - an Am79C960 PCnet-ISA Single-Chip Ethernet Controller with both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * - an MC68230 Parallel Interface/Timer configured as 2 parallel ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * Am79C960 PCnet-ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct Am79C960 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) volatile u_short AddressPROM[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* IEEE Address PROM (Unused in the Ariadne) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) volatile u_short RDP; /* Register Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) volatile u_short RAP; /* Register Address Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) volatile u_short Reset; /* Reset Chip on Read Access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) volatile u_short IDP; /* ISACSR Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * Am79C960 Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * Only registers marked with a `-' are intended for network software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSR0 0x0000 /* - PCnet-ISA Controller Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSR1 0x0100 /* - IADR[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSR2 0x0200 /* - IADR[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSR4 0x0400 /* - Test and Features Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CSR6 0x0600 /* RCV/XMT Descriptor Table Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSR8 0x0800 /* - Logical Address Filter, LADRF[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CSR9 0x0900 /* - Logical Address Filter, LADRF[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CSR10 0x0a00 /* - Logical Address Filter, LADRF[47:32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CSR11 0x0b00 /* - Logical Address Filter, LADRF[63:48] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CSR12 0x0c00 /* - Physical Address Register, PADR[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CSR13 0x0d00 /* - Physical Address Register, PADR[31:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CSR14 0x0e00 /* - Physical Address Register, PADR[47:32] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CSR15 0x0f00 /* - Mode Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CSR16 0x1000 /* Initialization Block Address Lower */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CSR17 0x1100 /* Initialization Block Address Upper */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CSR18 0x1200 /* Current Receive Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CSR19 0x1300 /* Current Receive Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CSR20 0x1400 /* Current Transmit Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CSR21 0x1500 /* Current Transmit Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CSR22 0x1600 /* Next Receive Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CSR23 0x1700 /* Next Receive Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CSR24 0x1800 /* - Base Address of Receive Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CSR25 0x1900 /* - Base Address of Receive Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CSR26 0x1a00 /* Next Receive Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CSR27 0x1b00 /* Next Receive Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CSR28 0x1c00 /* Current Receive Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CSR29 0x1d00 /* Current Receive Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CSR30 0x1e00 /* - Base Address of Transmit Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CSR31 0x1f00 /* - Base Address of transmit Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CSR32 0x2000 /* Next Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CSR33 0x2100 /* Next Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CSR34 0x2200 /* Current Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CSR35 0x2300 /* Current Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CSR36 0x2400 /* Next Next Receive Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CSR37 0x2500 /* Next Next Receive Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CSR38 0x2600 /* Next Next Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CSR39 0x2700 /* Next Next Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CSR40 0x2800 /* Current Receive Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CSR41 0x2900 /* Current Receive Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CSR42 0x2a00 /* Current Transmit Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CSR43 0x2b00 /* Current Transmit Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CSR44 0x2c00 /* Next Receive Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CSR45 0x2d00 /* Next Receive Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CSR46 0x2e00 /* Poll Time Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CSR47 0x2f00 /* Polling Interval */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CSR48 0x3000 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CSR49 0x3100 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CSR50 0x3200 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CSR51 0x3300 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CSR52 0x3400 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CSR53 0x3500 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CSR54 0x3600 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CSR55 0x3700 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CSR56 0x3800 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CSR57 0x3900 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CSR58 0x3a00 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CSR59 0x3b00 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CSR60 0x3c00 /* Previous Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CSR61 0x3d00 /* Previous Transmit Descriptor Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CSR62 0x3e00 /* Previous Transmit Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CSR63 0x3f00 /* Previous Transmit Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CSR64 0x4000 /* Next Transmit Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CSR65 0x4100 /* Next Transmit Buffer Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CSR66 0x4200 /* Next Transmit Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CSR67 0x4300 /* Next Transmit Status and Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CSR68 0x4400 /* Transmit Status Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CSR69 0x4500 /* Transmit Status Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CSR70 0x4600 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CSR71 0x4700 /* Temporary Storage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CSR72 0x4800 /* Receive Ring Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CSR74 0x4a00 /* Transmit Ring Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CSR76 0x4c00 /* - Receive Ring Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CSR78 0x4e00 /* - Transmit Ring Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CSR80 0x5000 /* - Burst and FIFO Threshold Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CSR82 0x5200 /* - Bus Activity Timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CSR84 0x5400 /* DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CSR85 0x5500 /* DMA Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CSR86 0x5600 /* Buffer Byte Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CSR88 0x5800 /* - Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CSR89 0x5900 /* - Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CSR92 0x5c00 /* Ring Length Conversion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CSR94 0x5e00 /* Transmit Time Domain Reflectometry Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CSR96 0x6000 /* Bus Interface Scratch Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CSR97 0x6100 /* Bus Interface Scratch Register 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CSR98 0x6200 /* Bus Interface Scratch Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CSR99 0x6300 /* Bus Interface Scratch Register 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CSR104 0x6800 /* SWAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CSR105 0x6900 /* SWAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CSR108 0x6c00 /* Buffer Management Scratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CSR109 0x6d00 /* Buffer Management Scratch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CSR112 0x7000 /* - Missed Frame Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CSR114 0x7200 /* - Receive Collision Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CSR124 0x7c00 /* - Buffer Management Unit Test */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * Am79C960 ISA Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ISACSR0 0x0000 /* Master Mode Read Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ISACSR1 0x0100 /* Master Mode Write Active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ISACSR2 0x0200 /* Miscellaneous Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ISACSR4 0x0400 /* LED0 Status (Link Integrity) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ISACSR5 0x0500 /* LED1 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ISACSR6 0x0600 /* LED2 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ISACSR7 0x0700 /* LED3 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Bit definitions for CSR0 (PCnet-ISA Controller Status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ERR 0x0080 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define BABL 0x0040 /* Babble: Transmitted too many bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CERR 0x0020 /* No Heartbeat (10BASE-T) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MISS 0x0010 /* Missed Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MERR 0x0008 /* Memory Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define RINT 0x0004 /* Receive Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TINT 0x0002 /* Transmit Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IDON 0x0001 /* Initialization Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define INTR 0x8000 /* Interrupt Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define INEA 0x4000 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define RXON 0x2000 /* Receive On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TXON 0x1000 /* Transmit On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TDMD 0x0800 /* Transmit Demand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define STOP 0x0400 /* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define STRT 0x0200 /* Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define INIT 0x0100 /* Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define BABLM 0x0040 /* Babble Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MISSM 0x0010 /* Missed Frame Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MERRM 0x0008 /* Memory Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define RINTM 0x0004 /* Receive Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TINTM 0x0002 /* Transmit Interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IDONM 0x0001 /* Initialization Done Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define DXMT2PD 0x1000 /* Disable Transmit Two Part Deferral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EMBA 0x0800 /* Enable Modified Back-off Algorithm */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Bit definitions for CSR4 (Test and Features Control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ENTST 0x0080 /* Enable Test Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DMAPLUS 0x0040 /* Disable Burst Transaction Counter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TIMER 0x0020 /* Timer Enable Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DPOLL 0x0010 /* Disable Transmit Polling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define APAD_XMT 0x0008 /* Auto Pad Transmit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define ASTRP_RCV 0x0004 /* Auto Pad Stripping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MFCO 0x0002 /* Missed Frame Counter Overflow Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MFCOM 0x0001 /* Missed Frame Counter Overflow Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define RCVCCO 0x2000 /* Receive Collision Counter Overflow Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define RCVCCOM 0x1000 /* Receive Collision Counter Overflow Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TXSTRT 0x0800 /* Transmit Start Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TXSTRTM 0x0400 /* Transmit Start Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define JAB 0x0200 /* Jabber Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define JABM 0x0100 /* Jabber Error Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * Bit definitions for CSR15 (Mode Register)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PROM 0x0080 /* Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DRCVBC 0x0040 /* Disable Receive Broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DRCVPA 0x0020 /* Disable Receive Physical Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DLNKTST 0x0010 /* Disable Link Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DAPC 0x0008 /* Disable Automatic Polarity Correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MENDECL 0x0004 /* MENDEC Loopback Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define LRTTSEL 0x0002 /* Low Receive Threshold/Transmit Mode Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PORTSEL1 0x0001 /* Port Select Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PORTSEL2 0x8000 /* Port Select Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define INTL 0x4000 /* Internal Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define DRTY 0x2000 /* Disable Retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define FCOLL 0x1000 /* Force Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define DXMTFCS 0x0800 /* Disable Transmit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define LOOP 0x0400 /* Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define DTX 0x0200 /* Disable Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define DRX 0x0100 /* Disable Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * Bit definitions for ISACSR2 (Miscellaneous Configuration)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ASEL 0x0200 /* Media Interface Port Auto Select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * Bit definitions for ISACSR5-7 (LED1-3 Status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * These values are already swap()ed!!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define LEDOUT 0x0080 /* Current LED Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define PSE 0x8000 /* Pulse Stretcher Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define XMTE 0x1000 /* Enable Transmit Status Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define RVPOLE 0x0800 /* Enable Receive Polarity Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define RCVE 0x0400 /* Enable Receive Status Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define JABE 0x0200 /* Enable Jabber Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define COLE 0x0100 /* Enable Collision Signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * Receive Descriptor Ring Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct RDRE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) volatile u_short RMD0; /* LADR[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) volatile u_short RMD1; /* HADR[23:16] | Receive Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) volatile u_short RMD2; /* Buffer Byte Count (two's complement) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) volatile u_short RMD3; /* Message Byte Count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * Transmit Descriptor Ring Entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct TDRE {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) volatile u_short TMD0; /* LADR[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) volatile u_short TMD1; /* HADR[23:16] | Transmit Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) volatile u_short TMD2; /* Buffer Byte Count (two's complement) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) volatile u_short TMD3; /* Error Flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * Receive Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define RF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RF_ERR 0x0040 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define RF_FRAM 0x0020 /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define RF_OFLO 0x0010 /* Overflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define RF_CRC 0x0008 /* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define RF_BUFF 0x0004 /* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define RF_STP 0x0002 /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define RF_ENP 0x0001 /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * Transmit Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TF_OWN 0x0080 /* PCnet-ISA controller owns the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TF_ERR 0x0040 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TF_ADD_FCS 0x0020 /* Controls FCS Generation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TF_MORE 0x0010 /* More than one retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TF_ONE 0x0008 /* One retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TF_DEF 0x0004 /* Deferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TF_STP 0x0002 /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TF_ENP 0x0001 /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Error Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EF_BUFF 0x0080 /* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EF_UFLO 0x0040 /* Underflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EF_LCOL 0x0010 /* Late Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define EF_LCAR 0x0008 /* Loss of Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define EF_RTRY 0x0004 /* Retry Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define EF_TDR 0xff03 /* Time Domain Reflectometry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * MC68230 Parallel Interface/Timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct MC68230 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) volatile u_char PGCR; /* Port General Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u_char Pad1[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) volatile u_char PSRR; /* Port Service Request Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u_char Pad2[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) volatile u_char PADDR; /* Port A Data Direction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) u_char Pad3[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) volatile u_char PBDDR; /* Port B Data Direction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) u_char Pad4[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) volatile u_char PCDDR; /* Port C Data Direction Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) u_char Pad5[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) volatile u_char PIVR; /* Port Interrupt Vector Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u_char Pad6[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) volatile u_char PACR; /* Port A Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u_char Pad7[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) volatile u_char PBCR; /* Port B Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u_char Pad8[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) volatile u_char PADR; /* Port A Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u_char Pad9[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) volatile u_char PBDR; /* Port B Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u_char Pad10[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) volatile u_char PAAR; /* Port A Alternate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u_char Pad11[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) volatile u_char PBAR; /* Port B Alternate Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u_char Pad12[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) volatile u_char PCDR; /* Port C Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u_char Pad13[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) volatile u_char PSR; /* Port Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u_char Pad14[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) volatile u_char TCR; /* Timer Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) u_char Pad15[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) volatile u_char TIVR; /* Timer Interrupt Vector Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) u_char Pad16[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) volatile u_char CPRH; /* Counter Preload Register (High) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) u_char Pad17[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) volatile u_char CPRM; /* Counter Preload Register (Mid) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u_char Pad18[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) volatile u_char CPRL; /* Counter Preload Register (Low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) u_char Pad19[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) volatile u_char CNTRH; /* Count Register (High) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u_char Pad20[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) volatile u_char CNTRM; /* Count Register (Mid) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u_char Pad21[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) volatile u_char CNTRL; /* Count Register (Low) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) u_char Pad22[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) volatile u_char TSR; /* Timer Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u_char Pad23[11];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * Ariadne Expansion Board Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define ARIADNE_LANCE 0x360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define ARIADNE_PIT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define ARIADNE_BOOTPROM 0x4000 /* I guess it's here :-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define ARIADNE_BOOTPROM_SIZE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define ARIADNE_RAM 0x8000 /* Always access WORDs!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define ARIADNE_RAM_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags
| Donate