^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Advanced Micro Devices Inc. AMD8111E Linux Network Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2003 Advanced Micro Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Module Name:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) amd8111e.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Abstract:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) AMD8111 based 10/100 Ethernet Controller driver definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Environment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Kernel Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Revision History:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 3.0.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Initial Revision.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 3.0.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #ifndef _AMD811E_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define _AMD811E_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Command style register access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Offset for Memory Mapped Registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* 32 bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ASF_STAT 0x00 /* ASF status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CHIPID 0x04 /* Chip ID register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIB_DATA 0x10 /* MIB data register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIB_ADDR 0x14 /* MIB address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define STAT0 0x30 /* Status0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define INT0 0x38 /* Interrupt0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define INTEN0 0x40 /* Interrupt0 enable register*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CMD0 0x48 /* Command0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CMD2 0x50 /* Command2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CMD3 0x54 /* Command3 resiter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CMD7 0x64 /* Command7 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CTRL1 0x6C /* Control1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CTRL2 0x70 /* Control2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define XMT_RING_LIMIT 0x7C /* Transmit ring limit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define AUTOPOLL0 0x88 /* Auto-poll0 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define AUTOPOLL1 0x8A /* Auto-poll1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define AUTOPOLL2 0x8C /* Auto-poll2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define AUTOPOLL3 0x8E /* Auto-poll3 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define AUTOPOLL4 0x90 /* Auto-poll4 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define AUTOPOLL5 0x92 /* Auto-poll5 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define AP_VALUE 0x98 /* Auto-poll value register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DLY_INT_A 0xA8 /* Group A delayed interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DLY_INT_B 0xAC /* Group B delayed interrupt register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define FLOW_CONTROL 0xC8 /* Flow control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_ACCESS 0xD0 /* PHY access register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define STVAL 0xD8 /* Software timer value register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define XMT_RING_BASE_ADDR0 0x100 /* Transmit ring0 base addr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define XMT_RING_BASE_ADDR1 0x108 /* Transmit ring1 base addr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define XMT_RING_BASE_ADDR2 0x110 /* Transmit ring2 base addr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define XMT_RING_BASE_ADDR3 0x118 /* Transmit ring2 base addr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define RCV_RING_BASE_ADDR0 0x120 /* Transmit ring0 base addr register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PMAT0 0x190 /* OnNow pattern register0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PMAT1 0x194 /* OnNow pattern register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* 16bit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define XMT_RING_LEN0 0x140 /* Transmit Ring0 length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define XMT_RING_LEN1 0x144 /* Transmit Ring1 length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define XMT_RING_LEN2 0x148 /* Transmit Ring2 length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define XMT_RING_LEN3 0x14C /* Transmit Ring3 length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define RCV_RING_LEN0 0x150 /* Receive Ring0 length register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SRAM_SIZE 0x178 /* SRAM size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SRAM_BOUNDARY 0x17A /* SRAM boundary register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* 48bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define PADR 0x160 /* Physical address register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IFS1 0x18C /* Inter-frame spacing Part1 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IFS 0x18D /* Inter-frame spacing register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IPG 0x18E /* Inter-frame gap register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* 64bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LADRF 0x168 /* Logical address filter register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* Register Bit Definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ASF_INIT_DONE = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) ASF_INIT_PRESENT = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }STAT_ASF_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) MIB_CMD_ACTIVE = (1 << 15 ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) MIB_RD_CMD = (1 << 13 ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) MIB_CLEAR = (1 << 12 ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) MIB_ADDRESS = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) (1 << 4) | (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }MIB_ADDR_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) PMAT_DET = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) MP_DET = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) LC_DET = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) SPEED_MASK = (1 << 9)|(1 << 8)|(1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) FULL_DPLX = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) LINK_STATS = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) AUTONEG_COMPLETE = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MIIPD = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) RX_SUSPENDED = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) TX_SUSPENDED = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) RUNNING = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }STAT0_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PHY_SPEED_10 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PHY_SPEED_100 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* INT0 0x38, 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) INTR = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PCSINT = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) LCINT = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) APINT5 = (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) APINT4 = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) APINT3 = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) TINT_SUM = (1 << 23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) APINT2 = (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) APINT1 = (1 << 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) APINT0 = (1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MIIPDTINT = (1 << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MCCINT = (1 << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MREINT = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) RINT_SUM = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) SPNDINT = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MPINT = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) SINT = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) TINT3 = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) TINT2 = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) TINT1 = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) TINT0 = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) UINT = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) STINT = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) RINT0 = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }INT0_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) VAL3 = (1 << 31), /* VAL bit for byte 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) VAL2 = (1 << 23), /* VAL bit for byte 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) VAL1 = (1 << 15), /* VAL bit for byte 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) VAL0 = (1 << 7), /* VAL bit for byte 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }VAL_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* VAL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) LCINTEN = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) APINT5EN = (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) APINT4EN = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) APINT3EN = (1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* VAL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) APINT2EN = (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) APINT1EN = (1 << 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) APINT0EN = (1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MIIPDTINTEN = (1 << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) MCCIINTEN = (1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MCCINTEN = (1 << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) MREINTEN = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* VAL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) SPNDINTEN = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) MPINTEN = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TINTEN3 = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) SINTEN = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) TINTEN2 = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) TINTEN1 = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) TINTEN0 = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* VAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) STINTEN = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) RINTEN0 = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) INTEN0_CLEAR = 0x1F7F7F1F, /* Command style register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) }INTEN0_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* VAL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) RDMD0 = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* VAL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) TDMD3 = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) TDMD2 = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) TDMD1 = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) TDMD0 = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* VAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) UINTCMD = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) RX_FAST_SPND = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) TX_FAST_SPND = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) RX_SPND = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) TX_SPND = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) INTREN = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) RUN = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CMD0_CLEAR = 0x000F0F7F, /* Command style register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }CMD0_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* VAL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CONDUIT_MODE = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* VAL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) RPA = (1 << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) DRCVPA = (1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) DRCVBC = (1 << 17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) PROM = (1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* VAL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ASTRP_RCV = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) RCV_DROP0 = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) EMBA = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) DXMT2PD = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) LTINTEN = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) DXMTFCS = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* VAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) APAD_XMT = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) DRTY = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) INLOOP = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) EXLOOP = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) REX_RTRY = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) REX_UFLO = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) REX_LCOL = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) CMD2_CLEAR = 0x3F7F3F7F, /* Command style register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }CMD2_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* VAL3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ASF_INIT_DONE_ALIAS = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* VAL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) JUMBO = (1 << 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) VSIZE = (1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) VLONLY = (1 << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) VL_TAG_DEL = (1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* VAL1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) EN_PMGR = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) INTLEVEL = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FORCE_FULL_DUPLEX = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) FORCE_LINK_STATUS = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) APEP = (1 << 10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) MPPLBA = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* VAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) RESET_PHY_PULSE = (1 << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) RESET_PHY = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PHY_RST_POL = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }CMD3_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) /* VAL0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PMAT_SAVE_MATCH = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) PMAT_MODE = (1 << 3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) MPEN_SW = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) LCMODE_SW = (1 << 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) CMD7_CLEAR = 0x0000001B /* Command style register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }CMD7_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) RESET_PHY_WIDTH = (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) XMTSP_MASK = (1 << 9) | (1 << 8), /* 9:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) XMTSP_128 = (1 << 9), /* 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) XMTSP_64 = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CACHE_ALIGN = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) BURST_LIMIT_MASK = (0xF << 0 ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CTRL1_DEFAULT = 0x00010111,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }CTRL1_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) FMDC_MASK = (1 << 9)|(1 << 8), /* 9:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) XPHYRST = (1 << 7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) XPHYANE = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) XPHYFD = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) XPHYSP = (1 << 4) | (1 << 3), /* 4:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) APDW_MASK = (1 << 2) | (1 << 1) | (1 << 0), /* 2:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }CTRL2_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* XMT_RING_LIMIT 0x7C, 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) XMT_RING2_LIMIT = (0xFF << 16), /* 23:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) XMT_RING1_LIMIT = (0xFF << 8), /* 15:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) XMT_RING0_LIMIT = (0xFF << 0), /* 7:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }XMT_RING_LIMIT_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) AP_REG0_EN = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) AP_REG0_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) AP_PHY0_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }AUTOPOLL0_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* AUTOPOLL1 0x8A, 16bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) AP_REG1_EN = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) AP_REG1_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) AP_PRE_SUP1 = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) AP_PHY1_DFLT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) AP_PHY1_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) }AUTOPOLL1_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) AP_REG2_EN = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) AP_REG2_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) AP_PRE_SUP2 = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) AP_PHY2_DFLT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) AP_PHY2_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }AUTOPOLL2_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) AP_REG3_EN = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) AP_REG3_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) AP_PRE_SUP3 = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) AP_PHY3_DFLT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) AP_PHY3_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }AUTOPOLL3_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) AP_REG4_EN = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) AP_REG4_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) AP_PRE_SUP4 = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) AP_PHY4_DFLT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) AP_PHY4_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }AUTOPOLL4_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) AP_REG5_EN = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) AP_REG5_ADDR_MASK = (0xF << 8) |(1 << 12),/* 12:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) AP_PRE_SUP5 = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) AP_PHY5_DFLT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) AP_PHY5_ADDR_MASK = (0xF << 0) |(1 << 4),/* 4:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) }AUTOPOLL5_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* AP_VALUE 0x98, 32bit ragister */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) AP_VAL_ACTIVE = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) AP_VAL_RD_CMD = ( 1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) AP_ADDR = (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) AP_VAL = (0xF << 0) | (0xF << 4) |( 0xF << 8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) (0xF << 12), /* 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }AP_VALUE_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) DLY_INT_A_R3 = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) DLY_INT_A_R2 = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) DLY_INT_A_R1 = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) DLY_INT_A_R0 = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) DLY_INT_A_T3 = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) DLY_INT_A_T2 = (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) DLY_INT_A_T1 = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DLY_INT_A_T0 = ( 1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) EVENT_COUNT_A = (0xF << 16) | (0x1 << 20),/* 20:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) MAX_DELAY_TIME_A = (0xF << 0) | (0xF << 4) | (1 << 8)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) (1 << 9) | (1 << 10), /* 10:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }DLY_INT_A_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) DLY_INT_B_R3 = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) DLY_INT_B_R2 = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DLY_INT_B_R1 = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DLY_INT_B_R0 = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) DLY_INT_B_T3 = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) DLY_INT_B_T2 = (1 << 26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) DLY_INT_B_T1 = (1 << 25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) DLY_INT_B_T0 = ( 1 << 24),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) EVENT_COUNT_B = (0xF << 16) | (0x1 << 20),/* 20:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) MAX_DELAY_TIME_B = (0xF << 0) | (0xF << 4) | (1 << 8)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) (1 << 9) | (1 << 10), /* 10:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }DLY_INT_B_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* FLOW_CONTROL 0xC8, 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) PAUSE_LEN_CHG = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) FTPE = (1 << 22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) FRPE = (1 << 21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) NAPA = (1 << 20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) NPA = (1 << 19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) FIXP = ( 1 << 18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) FCCMD = ( 1 << 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) PAUSE_LEN = (0xF << 0) | (0xF << 4) |( 0xF << 8) | (0xF << 12), /* 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) }FLOW_CONTROL_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* PHY_ ACCESS 0xD0, 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) PHY_CMD_ACTIVE = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) PHY_WR_CMD = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) PHY_RD_CMD = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) PHY_RD_ERR = (1 << 28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) PHY_PRE_SUP = (1 << 27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) PHY_ADDR = (1 << 21) | (1 << 22) | (1 << 23)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) (1 << 24) |(1 << 25),/* 25:21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) PHY_REG_ADDR = (1 << 16) | (1 << 17) | (1 << 18)| (1 << 19) | (1 << 20),/* 20:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) PHY_DATA = (0xF << 0)|(0xF << 4) |(0xF << 8)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) (0xF << 12),/* 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }PHY_ACCESS_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* PMAT0 0x190, 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) PMR_ACTIVE = (1 << 31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) PMR_WR_CMD = (1 << 30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) PMR_RD_CMD = (1 << 29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) PMR_BANK = (1 <<28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) PMR_ADDR = (0xF << 16)|(1 << 20)|(1 << 21)|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) (1 << 22),/* 22:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) PMR_B4 = (0xF << 0) | (0xF << 4),/* 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }PMAT0_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* PMAT1 0x194, 32bit register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) PMR_B3 = (0xF << 24) | (0xF <<28),/* 31:24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) PMR_B2 = (0xF << 16) |(0xF << 20),/* 23:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) PMR_B1 = (0xF << 8) | (0xF <<12), /* 15:8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) PMR_B0 = (0xF << 0)|(0xF << 4),/* 7:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }PMAT1_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* MIB counter definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /************************************************************************/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define rcv_miss_pkts 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define rcv_octets 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define rcv_broadcast_pkts 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define rcv_multicast_pkts 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define rcv_undersize_pkts 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define rcv_oversize_pkts 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define rcv_fragments 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define rcv_jabbers 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define rcv_unicast_pkts 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define rcv_alignment_errors 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define rcv_fcs_errors 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define rcv_good_octets 0x0B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define rcv_mac_ctrl 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define rcv_flow_ctrl 0x0D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define rcv_pkts_64_octets 0x0E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define rcv_pkts_65to127_octets 0x0F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define rcv_pkts_128to255_octets 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define rcv_pkts_256to511_octets 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define rcv_pkts_512to1023_octets 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define rcv_pkts_1024to1518_octets 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define rcv_unsupported_opcode 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define rcv_symbol_errors 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define rcv_drop_pkts_ring1 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define rcv_drop_pkts_ring2 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define rcv_drop_pkts_ring3 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define rcv_drop_pkts_ring4 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define rcv_jumbo_pkts 0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define xmt_underrun_pkts 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define xmt_octets 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define xmt_packets 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define xmt_broadcast_pkts 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define xmt_multicast_pkts 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define xmt_collisions 0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define xmt_unicast_pkts 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define xmt_one_collision 0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define xmt_multiple_collision 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define xmt_deferred_transmit 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define xmt_late_collision 0x2A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define xmt_excessive_defer 0x2B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define xmt_loss_carrier 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define xmt_excessive_collision 0x2D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define xmt_back_pressure 0x2E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define xmt_flow_ctrl 0x2F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define xmt_pkts_64_octets 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define xmt_pkts_65to127_octets 0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define xmt_pkts_128to255_octets 0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define xmt_pkts_256to511_octets 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define xmt_pkts_512to1023_octets 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define xmt_pkts_1024to1518_octet 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define xmt_oversize_pkts 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define xmt_jumbo_pkts 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* Driver definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define PCI_VENDOR_ID_AMD 0x1022
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define PCI_DEVICE_ID_AMD8111E_7462 0x7462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MAX_UNITS 8 /* Maximum number of devices possible */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define NUM_TX_BUFFERS 32 /* Number of transmit buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define NUM_RX_BUFFERS 32 /* Number of receive buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define TX_BUFF_MOD_MASK 31 /* (NUM_TX_BUFFERS -1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define RX_BUFF_MOD_MASK 31 /* (NUM_RX_BUFFERS -1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define NUM_TX_RING_DR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define NUM_RX_RING_DR 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define TX_RING_DR_MOD_MASK 31 /* (NUM_TX_RING_DR -1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define RX_RING_DR_MOD_MASK 31 /* (NUM_RX_RING_DR -1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define MAX_FILTER_SIZE 64 /* Maximum multicast address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define AMD8111E_MIN_MTU 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define AMD8111E_MAX_MTU 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define PKT_BUFF_SZ 1536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define MIN_PKT_LEN 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define AMD8111E_TX_TIMEOUT (3 * HZ)/* 3 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SOFT_TIMER_FREQ 0xBEBC /* 0.5 sec */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define DELAY_TIMER_CONV 50 /* msec to 10 usec conversion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) Only 500 usec resolution */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define OPTION_VLAN_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define OPTION_JUMBO_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define OPTION_MULTICAST_ENABLE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define OPTION_WOL_ENABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define OPTION_WAKE_MAGIC_ENABLE 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define OPTION_WAKE_PHY_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define OPTION_INTR_COAL_ENABLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define OPTION_DYN_IPG_ENABLE 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define PHY_REG_ADDR_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) /* ipg parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define DEFAULT_IPG 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define IFS1_DELTA 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define IPG_CONVERGE_JIFFIES (HZ/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define IPG_STABLE_TIME 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define MIN_IPG 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define MAX_IPG 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define IPG_STEP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define CSTATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define SSTATE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* Assume contoller gets data 10 times the maximum processing time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define REPEAT_CNT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* amd8111e descriptor flag definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) OWN_BIT = (1 << 15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ADD_FCS_BIT = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) LTINT_BIT = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) STP_BIT = (1 << 9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ENP_BIT = (1 << 8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) KILL_BIT = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) TCC_VLAN_INSERT = (1 << 1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) TCC_VLAN_REPLACE = (1 << 1) |( 1<< 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) }TX_FLAG_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ERR_BIT = (1 << 14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) FRAM_BIT = (1 << 13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) OFLO_BIT = (1 << 12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) CRC_BIT = (1 << 11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) PAM_BIT = (1 << 6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) LAFM_BIT = (1 << 5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) BAM_BIT = (1 << 4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) TT_VLAN_TAGGED = (1 << 3) |(1 << 2),/* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) TT_PRTY_TAGGED = (1 << 3),/* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }RX_FLAG_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #define RESET_RX_FLAGS 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define TT_MASK 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) #define TCC_MASK 0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /* driver ioctl parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define AMD8111E_REG_DUMP_LEN 13*sizeof(u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* amd8111e descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct amd8111e_tx_dr{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) __le16 buff_count; /* Size of the buffer pointed by this descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) __le16 tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __le16 tag_ctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __le16 tag_ctrl_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) __le32 buff_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) struct amd8111e_rx_dr{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) __le32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) __le16 msg_count; /* Received message len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) __le16 tag_ctrl_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) __le16 buff_count; /* Len of the buffer pointed by descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) __le16 rx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) __le32 buff_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct amd8111e_link_config{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define SPEED_INVALID 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DUPLEX_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define AUTONEG_INVALID 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) unsigned long orig_phy_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u16 speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u8 duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) u8 autoneg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u8 reserved; /* 32bit alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) enum coal_type{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) NO_COALESCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) LOW_COALESCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MEDIUM_COALESCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) HIGH_COALESCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) enum coal_mode{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) RX_INTR_COAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) TX_INTR_COAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) DISABLE_COAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ENABLE_COAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) #define MAX_TIMEOUT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define MAX_EVENT_COUNT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) struct amd8111e_coalesce_conf{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) unsigned int rx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) unsigned int rx_event_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned long rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) unsigned long rx_prev_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) unsigned long rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) unsigned long rx_prev_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) unsigned int rx_coal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) unsigned int tx_timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned int tx_event_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) unsigned long tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned long tx_prev_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned long tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned long tx_prev_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) unsigned int tx_coal_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct ipg_info{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) unsigned int ipg_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) unsigned int ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned int current_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) unsigned int col_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int diff_col_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) unsigned int timer_tick;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) unsigned int prev_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct timer_list ipg_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) struct amd8111e_priv{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct amd8111e_tx_dr* tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct amd8111e_rx_dr* rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dma_addr_t tx_ring_dma_addr; /* tx descriptor ring base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dma_addr_t rx_ring_dma_addr; /* rx descriptor ring base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct pci_dev *pci_dev; /* Ptr to the associated pci_dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) struct net_device* amd8111e_net_dev; /* ptr to associated net_device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) /* Transmit and receive skbs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) /* Transmit and receive dma mapped addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* Reg memory mapped address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) void __iomem *mmio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) spinlock_t lock; /* Guard lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) unsigned long rx_idx, tx_idx; /* The next free ring entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) unsigned long tx_complete_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned long tx_ring_complete_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) unsigned long tx_ring_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) unsigned int rx_buff_len; /* Buffer length of rx buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int options; /* Options enabled/disabled for the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) unsigned long ext_phy_option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) int ext_phy_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 ext_phy_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) struct amd8111e_link_config link_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) int pm_cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct net_device *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) int mii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) struct mii_if_info mii_if;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) char opened;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) unsigned int drv_rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct amd8111e_coalesce_conf coal_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct ipg_info ipg_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) BUG? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) #define amd8111e_writeq(_UlData,_memMap) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) writel(*(u32*)(&_UlData), _memMap); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* maps the external speed options to internal value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) SPEED_AUTONEG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) SPEED10_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) SPEED10_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) SPEED100_HALF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) SPEED100_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }EXT_PHY_OPTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int card_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int speed_duplex[MAX_UNITS] = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static bool coalesce[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = true };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) static bool dynamic_ipg[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = false };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static unsigned int chip_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) #endif /* _AMD8111E_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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