^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/net/ethernet/amd/am79c961a.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _LINUX_am79c961a_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _LINUX_am79c961a_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* use 0 for production, 1 for verification, >2 for debug. debug flags: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DEBUG_TX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DEBUG_RX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DEBUG_INT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DEBUG_IC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #ifndef NET_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define NET_DEBUG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define NET_UID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define NET_RDP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NET_RAP 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define NET_RESET 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define NET_IDP 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * RAP registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CSR0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CSR0_INIT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CSR0_STRT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CSR0_STOP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CSR0_TDMD 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CSR0_TXON 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CSR0_RXON 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CSR0_IENA 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CSR0_INTR 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CSR0_IDON 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CSR0_TINT 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CSR0_RINT 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CSR0_MERR 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CSR0_MISS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CSR0_CERR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CSR0_BABL 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CSR0_ERR 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CSR3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CSR3_EMBA 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CSR3_DXMT2PD 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CSR3_LAPPEN 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CSR3_DXSUFLO 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CSR3_IDONM 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CSR3_TINTM 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CSR3_RINTM 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CSR3_MERRM 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CSR3_MISSM 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CSR3_BABLM 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CSR3_MASKALL 0x5F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CSR4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CSR4_JABM 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CSR4_JAB 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CSR4_TXSTRTM 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CSR4_TXSTRT 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CSR4_RCVCCOM 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CSR4_RCVCCO 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CSR4_MFCOM 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CSR4_MFCO 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CSR4_ASTRP_RCV 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CSR4_APAD_XMIT 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CTRL1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CTRL1_SPND 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LADRL 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LADRM1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LADRM2 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LADRH 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PADRL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PADRM 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PADRH 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MODE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MODE_DISRX 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MODE_DISTX 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MODE_LOOP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MODE_DTCRC 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MODE_COLL 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MODE_DRETRY 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MODE_INTLOOP 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MODE_PORT_AUI 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MODE_PORT_10BT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MODE_DRXPA 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MODE_DRXBA 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MODE_PROMISC 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define BASERXL 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define BASERXH 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define BASETXL 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BASETXH 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define POLLINT 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SIZERXR 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SIZETXR 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CSR_MFC 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define RMD_ENP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define RMD_STP 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define RMD_CRC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define RMD_FRAM 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RMD_ERR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define RMD_OWN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TMD_ENP 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TMD_STP 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TMD_MORE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TMD_ERR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TMD_OWN 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TST_RTRY 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TST_LCAR 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TST_LCOL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TST_UFLO 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TST_BUFF 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ISALED0 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ISALED0_LNKST 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dev_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned long rxbuffer[RX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long txbuffer[TX_BUFFERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned char txhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned char txtail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned char rxhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned char rxtail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned long rxhdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned long txhdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) spinlock_t chip_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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