^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * linux/drivers/net/ethernet/amd/am79c961a.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * by Russell King <rmk@arm.linux.org.uk> 1995-2001.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Derived from various things including skeleton.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * This is a special driver for the am79c961A Lance chip used in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Intel (formally Digital Equipment Corp) EBSA110 platform. Please
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * note that this can not be built as a module (it doesn't make sense).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <mach/hardware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TX_BUFFERS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define RX_BUFFERS 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include "am79c961a.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) am79c961_interrupt (int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) static unsigned int net_debug = NET_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "am79c961 ethernet driver (C) 1995-2001 Russell King v0.04\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* --------------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #ifdef __arm__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) static void write_rreg(u_long base, u_int reg, u_int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "strh %1, [%2] @ NET_RAP\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "strh %0, [%2, #-4] @ NET_RDP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline unsigned short read_rreg(u_long base_addr, u_int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned short v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) "strh %1, [%2] @ NET_RAP\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "ldrh %0, [%2, #-4] @ NET_RDP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) : "=r" (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) : "r" (reg), "r" (ISAIO_BASE + 0x0464));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) static inline void write_ireg(u_long base, u_int reg, u_int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) "strh %1, [%2] @ NET_RAP\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "strh %0, [%2, #8] @ NET_IDP"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) : "r" (val), "r" (reg), "r" (ISAIO_BASE + 0x0464));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static inline unsigned short read_ireg(u_long base_addr, u_int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u_short v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) "strh %1, [%2] @ NAT_RAP\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) "ldrh %0, [%2, #8] @ NET_IDP\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) : "=r" (v)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) : "r" (reg), "r" (ISAIO_BASE + 0x0464));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define am_writeword(dev,off,val) __raw_writew(val, ISAMEM_BASE + ((off) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define am_readword(dev,off) __raw_readw(ISAMEM_BASE + ((off) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) am_writebuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) offset = ISAMEM_BASE + (offset << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) length = (length + 1) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if ((int)buf & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) asm volatile("strh %2, [%0], #4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) : "=&r" (offset) : "0" (offset), "r" (buf[0] | (buf[1] << 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) buf += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) length -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) while (length > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) register unsigned int tmp asm("r2"), tmp2 asm("r3");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) "ldmia %0!, {%1, %2}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) : "+r" (buf), "=&r" (tmp), "=&r" (tmp2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) length -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) "strh %1, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) "mov %1, %1, lsr #16\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) "strh %1, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) "strh %2, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) "mov %2, %2, lsr #16\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) "strh %2, [%0], #4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) : "+r" (offset), "=&r" (tmp), "=&r" (tmp2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) while (length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) asm volatile("strh %2, [%0], #4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) : "=&r" (offset) : "0" (offset), "r" (buf[0] | (buf[1] << 8)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) buf += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) length -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) am_readbuffer(struct net_device *dev, u_int offset, unsigned char *buf, unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) offset = ISAMEM_BASE + (offset << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) length = (length + 1) & ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) if ((int)buf & 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) "ldrh %2, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) "strb %2, [%1], #1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) "mov %2, %2, lsr #8\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) "strb %2, [%1], #1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) : "=&r" (offset), "=&r" (buf), "=r" (tmp): "0" (offset), "1" (buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) length -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) while (length > 8) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) register unsigned int tmp asm("r2"), tmp2 asm("r3"), tmp3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) "ldrh %2, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) "ldrh %4, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) "ldrh %3, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) "orr %2, %2, %4, lsl #16\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) "ldrh %4, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) "orr %3, %3, %4, lsl #16\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) "stmia %1!, {%2, %3}"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) : "=&r" (offset), "=&r" (buf), "=r" (tmp), "=r" (tmp2), "=r" (tmp3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) : "0" (offset), "1" (buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) length -= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) while (length > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) asm volatile(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) "ldrh %2, [%0], #4\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) "strb %2, [%1], #1\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) "mov %2, %2, lsr #8\n\t"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) "strb %2, [%1], #1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) : "=&r" (offset), "=&r" (buf), "=r" (tmp) : "0" (offset), "1" (buf));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) length -= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #error Not compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) am79c961_ramtest(struct net_device *dev, unsigned int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) unsigned char *buffer = kmalloc (65536, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) int i, error = 0, errorcount = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (!buffer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) memset (buffer, val, 65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) am_writebuffer(dev, 0, buffer, 65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) memset (buffer, val ^ 255, 65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) am_readbuffer(dev, 0, buffer, 65536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) for (i = 0; i < 65536; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (buffer[i] != val && !error) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) printk ("%s: buffer error (%02X %02X) %05X - ", dev->name, val, buffer[i], i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) error = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) errorcount ++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) } else if (error && buffer[i] == val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) printk ("%05X\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) printk ("10000\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) kfree (buffer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return errorcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) static void am79c961_mc_hash(char *addr, u16 *hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int idx, bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) crc = ether_crc_le(ETH_ALEN, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) idx = crc >> 30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) bit = (crc >> 26) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) hash[idx] |= 1 << bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static unsigned int am79c961_get_rx_mode(struct net_device *dev, u16 *hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int mode = MODE_PORT_10BT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) mode |= MODE_PROMISC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) memset(hash, 0xff, 4 * sizeof(*hash));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) } else if (dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) memset(hash, 0xff, 4 * sizeof(*hash));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) memset(hash, 0, 4 * sizeof(*hash));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) netdev_for_each_mc_addr(ha, dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) am79c961_mc_hash(ha->addr, hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) am79c961_init_for_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) unsigned char *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u_int hdr_addr, first_free_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u16 multi_hash[4], mode = am79c961_get_rx_mode(dev, multi_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * Stop the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) spin_lock_irqsave(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) write_rreg (dev->base_addr, CSR0, CSR0_BABL|CSR0_CERR|CSR0_MISS|CSR0_MERR|CSR0_TINT|CSR0_RINT|CSR0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) spin_unlock_irqrestore(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) write_ireg (dev->base_addr, 5, 0x00a0); /* Receive address LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) write_ireg (dev->base_addr, 6, 0x0081); /* Collision LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) write_ireg (dev->base_addr, 7, 0x0090); /* XMIT LED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) write_ireg (dev->base_addr, 2, 0x0000); /* MODE register selects media */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) for (i = LADRL; i <= LADRH; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) write_rreg (dev->base_addr, i, multi_hash[i - LADRL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) for (i = PADRL, p = dev->dev_addr; i <= PADRH; i++, p += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) write_rreg (dev->base_addr, i, p[0] | (p[1] << 8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) write_rreg (dev->base_addr, MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) write_rreg (dev->base_addr, POLLINT, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) write_rreg (dev->base_addr, SIZERXR, -RX_BUFFERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) write_rreg (dev->base_addr, SIZETXR, -TX_BUFFERS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) first_free_addr = RX_BUFFERS * 8 + TX_BUFFERS * 8 + 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) hdr_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) priv->rxhead = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) priv->rxtail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) priv->rxhdr = hdr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) for (i = 0; i < RX_BUFFERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) priv->rxbuffer[i] = first_free_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) am_writeword (dev, hdr_addr, first_free_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) am_writeword (dev, hdr_addr + 2, RMD_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) am_writeword (dev, hdr_addr + 4, (-1600));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) am_writeword (dev, hdr_addr + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) first_free_addr += 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) hdr_addr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) priv->txhead = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) priv->txtail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) priv->txhdr = hdr_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) for (i = 0; i < TX_BUFFERS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) priv->txbuffer[i] = first_free_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) am_writeword (dev, hdr_addr, first_free_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) am_writeword (dev, hdr_addr + 2, TMD_STP|TMD_ENP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) am_writeword (dev, hdr_addr + 4, 0xf000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) am_writeword (dev, hdr_addr + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) first_free_addr += 1600;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) hdr_addr += 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) write_rreg (dev->base_addr, BASERXL, priv->rxhdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) write_rreg (dev->base_addr, BASERXH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) write_rreg (dev->base_addr, BASETXL, priv->txhdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) write_rreg (dev->base_addr, BASERXH, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) write_rreg (dev->base_addr, CSR0, CSR0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) write_rreg (dev->base_addr, CSR4, CSR4_APAD_XMIT|CSR4_MFCOM|CSR4_RCVCCOM|CSR4_TXSTRTM|CSR4_JABM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) write_rreg (dev->base_addr, CSR0, CSR0_IENA|CSR0_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static void am79c961_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct dev_priv *priv = from_timer(priv, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct net_device *dev = priv->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) unsigned int lnkstat, carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) spin_lock_irqsave(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) lnkstat = read_ireg(dev->base_addr, ISALED0) & ISALED0_LNKST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock_irqrestore(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) carrier = netif_carrier_ok(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (lnkstat && !carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) printk("%s: link up\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) } else if (!lnkstat && carrier) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) printk("%s: link down\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) mod_timer(&priv->timer, jiffies + msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Open/initialize the board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) am79c961_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) ret = request_irq(dev->irq, am79c961_interrupt, 0, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) am79c961_init_for_open(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) priv->timer.expires = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) add_timer(&priv->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * The inverse routine to am79c961_open().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) am79c961_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) del_timer_sync(&priv->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) spin_lock_irqsave(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) write_rreg (dev->base_addr, CSR0, CSR0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) spin_unlock_irqrestore(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) free_irq (dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) * Set or clear promiscuous/multicast mode filter for this adapter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static void am79c961_setmulticastlist (struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u16 multi_hash[4], mode = am79c961_get_rx_mode(dev, multi_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int i, stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) spin_lock_irqsave(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) stopped = read_rreg(dev->base_addr, CSR0) & CSR0_STOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (!stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * Put the chip into suspend mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) write_rreg(dev->base_addr, CTRL1, CTRL1_SPND);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * Spin waiting for chip to report suspend mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) while ((read_rreg(dev->base_addr, CTRL1) & CTRL1_SPND) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spin_unlock_irqrestore(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) nop();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) spin_lock_irqsave(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Update the multicast hash table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) for (i = 0; i < ARRAY_SIZE(multi_hash); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) write_rreg(dev->base_addr, i + LADRL, multi_hash[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Write the mode register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) write_rreg(dev->base_addr, MODE, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * Put the chip back into running mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) write_rreg(dev->base_addr, CTRL1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_unlock_irqrestore(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) static void am79c961_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) printk(KERN_WARNING "%s: transmit timed out, network cable problem?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * ought to do some setup of the tx side here
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * Transmit a packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) am79c961_sendpacket(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int hdraddr, bufaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) head = priv->txhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) hdraddr = priv->txhdr + (head << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) bufaddr = priv->txbuffer[head];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) head += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (head >= TX_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) am_writebuffer (dev, bufaddr, skb->data, skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) am_writeword (dev, hdraddr + 4, -skb->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) am_writeword (dev, hdraddr + 2, TMD_OWN|TMD_STP|TMD_ENP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) priv->txhead = head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_lock_irqsave(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) write_rreg (dev->base_addr, CSR0, CSR0_TDMD|CSR0_IENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) spin_unlock_irqrestore(&priv->chip_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) * If the next packet is owned by the ethernet device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) * then the tx ring is full and we can't add another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (am_readword(dev, priv->txhdr + (priv->txhead << 3) + 2) & TMD_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * If we have a good packet(s), get it/them out of the buffers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) am79c961_rx(struct net_device *dev, struct dev_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u_int hdraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u_int pktaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u_int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) hdraddr = priv->rxhdr + (priv->rxtail << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) pktaddr = priv->rxbuffer[priv->rxtail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) status = am_readword (dev, hdraddr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (status & RMD_OWN) /* do we own it? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) priv->rxtail ++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) if (priv->rxtail >= RX_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) priv->rxtail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if ((status & (RMD_ERR|RMD_STP|RMD_ENP)) != (RMD_STP|RMD_ENP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) am_writeword (dev, hdraddr + 2, RMD_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (status & RMD_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (status & RMD_FRAM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) if (status & RMD_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) } else if (status & RMD_STP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) len = am_readword(dev, hdraddr + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) skb = netdev_alloc_skb(dev, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if (skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) skb_reserve(skb, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) am_readbuffer(dev, pktaddr, skb_put(skb, len), len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) am_writeword(dev, hdraddr + 2, RMD_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) am_writeword (dev, hdraddr + 2, RMD_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) } while (1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * Update stats for the transmitted packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) am79c961_tx(struct net_device *dev, struct dev_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) short len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u_int hdraddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u_int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) hdraddr = priv->txhdr + (priv->txtail << 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) status = am_readword (dev, hdraddr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (status & TMD_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) priv->txtail ++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (priv->txtail >= TX_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) priv->txtail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (status & TMD_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u_int status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) status2 = am_readword (dev, hdraddr + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * Clear the error byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) am_writeword (dev, hdraddr + 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (status2 & TST_RTRY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev->stats.collisions += 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) if (status2 & TST_LCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (status2 & TST_LCAR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) if (status2 & TST_UFLO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) len = am_readword (dev, hdraddr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev->stats.tx_bytes += -len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } while (priv->txtail != priv->txhead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) am79c961_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct net_device *dev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u_int status, n = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) status = read_rreg(dev->base_addr, CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) write_rreg(dev->base_addr, CSR0, status &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) (CSR0_IENA|CSR0_TINT|CSR0_RINT|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) CSR0_MERR|CSR0_MISS|CSR0_CERR|CSR0_BABL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (status & CSR0_RINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) am79c961_rx(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (status & CSR0_TINT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) am79c961_tx(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (status & CSR0_MISS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) if (status & CSR0_CERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) mod_timer(&priv->timer, jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } while (--n && status & (CSR0_RINT | CSR0_TINT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) static void am79c961_poll_controller(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) am79c961_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * Initialise the chip. Note that we always expect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * to be entered with interrupts enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) am79c961_hw_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct dev_priv *priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) spin_lock_irq(&priv->chip_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) write_rreg (dev->base_addr, CSR0, CSR0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) write_rreg (dev->base_addr, CSR3, CSR3_MASKALL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) spin_unlock_irq(&priv->chip_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) am79c961_ramtest(dev, 0x66);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) am79c961_ramtest(dev, 0x99);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void __init am79c961_banner(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) static unsigned version_printed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (net_debug && version_printed++ == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) printk(KERN_INFO "%s", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static const struct net_device_ops am79c961_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .ndo_open = am79c961_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) .ndo_stop = am79c961_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) .ndo_start_xmit = am79c961_sendpacket,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) .ndo_set_rx_mode = am79c961_setmulticastlist,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) .ndo_tx_timeout = am79c961_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) .ndo_poll_controller = am79c961_poll_controller,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int am79c961_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct dev_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) res = platform_get_resource(pdev, IORESOURCE_IO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dev = alloc_etherdev(sizeof(struct dev_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) priv = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * Fixed address and IRQ lines here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * The PNP initialisation should have been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * done by the ether bootp loader.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dev->base_addr = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) ret = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) goto nodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev->irq = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (!request_region(dev->base_addr, 0x18, dev->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) goto nodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * Reset the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) inb(dev->base_addr + NET_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * Check the manufacturer part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * ether address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) if (inb(dev->base_addr) != 0x08 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) inb(dev->base_addr + 2) != 0x00 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) inb(dev->base_addr + 4) != 0x2b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) dev->dev_addr[i] = inb(dev->base_addr + i * 2) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) am79c961_banner();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spin_lock_init(&priv->chip_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) priv->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) timer_setup(&priv->timer, am79c961_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) if (am79c961_hw_init(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) dev->netdev_ops = &am79c961_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ret = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (ret == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) printk(KERN_INFO "%s: ether address %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) dev->name, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) release_region(dev->base_addr, 0x18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) nodev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static struct platform_driver am79c961_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .probe = am79c961_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .name = "am79c961",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int __init am79c961_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return platform_driver_register(&am79c961_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) __initcall(am79c961_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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