^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Amiga Linux/68k A2065 Ethernet Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * (C) Copyright 1995 by Geert Uytterhoeven <geert@linux-m68k.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This program is based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * ariadne.?: Amiga Linux/68k Ariadne Ethernet Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * (C) Copyright 1995 by Geert Uytterhoeven,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Peter De Schrijver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * lance.c: An AMD LANCE ethernet driver for linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Written 1993-94 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * Am79C960: PCnet(tm)-ISA Single-Chip Ethernet Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Advanced Micro Devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Publication #16907, Rev. B, Amendment/0, May 1994
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * License. See the file COPYING in the main directory of the Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * distribution for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * ---------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * The A2065 is a Zorro-II board made by Commodore/Ameristar. It contains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - an Am7990 Local Area Network Controller for Ethernet (LANCE) with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * both 10BASE-2 (thin coax) and AUI (DB-15) connectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Am7990 Local Area Network Controller for Ethernet (LANCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct lance_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) unsigned short rdp; /* Register Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) unsigned short rap; /* Register Address Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * Am7990 Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define LE_CSR0 0x0000 /* LANCE Controller Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define LE_CSR1 0x0001 /* IADR[15:0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define LE_CSR2 0x0002 /* IADR[23:16] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LE_CSR3 0x0003 /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * Bit definitions for CSR0 (LANCE Controller Status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LE_C0_ERR 0x8000 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define LE_C0_BABL 0x4000 /* Babble: Transmitted too many bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LE_C0_MISS 0x1000 /* Missed Frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LE_C0_MERR 0x0800 /* Memory Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LE_C0_RINT 0x0400 /* Receive Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LE_C0_TINT 0x0200 /* Transmit Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LE_C0_IDON 0x0100 /* Initialization Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LE_C0_INTR 0x0080 /* Interrupt Flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define LE_C0_INEA 0x0040 /* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define LE_C0_RXON 0x0020 /* Receive On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LE_C0_TXON 0x0010 /* Transmit On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LE_C0_TDMD 0x0008 /* Transmit Demand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LE_C0_STOP 0x0004 /* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LE_C0_STRT 0x0002 /* Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LE_C0_INIT 0x0001 /* Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Bit definitions for CSR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define LE_C3_BSWP 0x0004 /* Byte Swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) (on for big endian byte order) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define LE_C3_ACON 0x0002 /* ALE Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) (on for active low ALE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LE_C3_BCON 0x0001 /* Byte Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Mode Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LE_MO_PROM 0x8000 /* Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LE_MO_INTL 0x0040 /* Internal Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LE_MO_DRTY 0x0020 /* Disable Retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LE_MO_FCOLL 0x0010 /* Force Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LE_MO_DXMTFCS 0x0008 /* Disable Transmit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LE_MO_LOOP 0x0004 /* Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LE_MO_DTX 0x0002 /* Disable Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LE_MO_DRX 0x0001 /* Disable Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct lance_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned short rmd0; /* low address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned char rmd1_bits; /* descriptor bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned char rmd1_hadr; /* high address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) short length; /* This length is 2s complement (negative)!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * Buffer length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned short mblength; /* Aactual number of bytes received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct lance_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned short tmd0; /* low address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned char tmd1_bits; /* descriptor bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned char tmd1_hadr; /* high address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) short length; /* Length is 2s complement (negative)! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned short misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Receive Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LE_R1_OWN 0x80 /* LANCE owns the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LE_R1_ERR 0x40 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LE_R1_FRA 0x20 /* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LE_R1_OFL 0x10 /* Overflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LE_R1_CRC 0x08 /* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LE_R1_BUF 0x04 /* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LE_R1_SOP 0x02 /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LE_R1_EOP 0x01 /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LE_R1_POK 0x03 /* Packet is complete: SOP + EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * Transmit Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LE_T1_OWN 0x80 /* LANCE owns the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LE_T1_ERR 0x40 /* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LE_T1_RES 0x20 /* Reserved,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) LANCE writes this with a zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LE_T1_EMORE 0x10 /* More than one retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LE_T1_EONE 0x08 /* One retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LE_T1_EDEF 0x04 /* Deferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LE_T1_SOP 0x02 /* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LE_T1_EOP 0x01 /* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define LE_T1_POK 0x03 /* Packet is complete: SOP + EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Error Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LE_T3_BUF 0x8000 /* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LE_T3_UFL 0x4000 /* Underflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LE_T3_LCOL 0x1000 /* Late Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LE_T3_CLOS 0x0800 /* Loss of Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define LE_T3_RTY 0x0400 /* Retry Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define LE_T3_TDR 0x03ff /* Time Domain Reflectometry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * A2065 Expansion Board Structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define A2065_LANCE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define A2065_RAM 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define A2065_RAM_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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