Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * 7990.h -- LANCE ethernet IC generic routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This is an attempt to separate out the bits of various ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * drivers that are common because they all use the AMD 7990 LANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * (Local Area Network Controller for Ethernet) chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Most of this stuff was obtained by looking at other LANCE drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #ifndef _7990_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define _7990_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) /* The lance only has two register locations. We communicate mostly via memory. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define LANCE_RDP	0	/* Register Data Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define LANCE_RAP	2	/* Register Address Port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* Transmit/receive ring definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  * We allow the specific drivers to override these defaults if they want to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  * NB: according to lance.c, increasing the number of buffers is a waste
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  * of space and reduces the chance that an upper layer will be able to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  * reorder queued Tx packets based on priority. [Clearly there is a minimum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * limit too: too small and we drop rx packets and can't tx at full speed.]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * 4+4 seems to be the usual setting; the atarilance driver uses 3 and 5.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* Blast! This won't work. The problem is that we can't specify a default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * setting because that would cause the lance_init_block struct to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * too long (and overflow the RAM on shared-memory cards like the HP LANCE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #ifndef LANCE_LOG_TX_BUFFERS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define LANCE_LOG_TX_BUFFERS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define LANCE_LOG_RX_BUFFERS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TX_RING_SIZE		(1 << LANCE_LOG_TX_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RX_RING_SIZE		(1 << LANCE_LOG_RX_BUFFERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TX_RING_MOD_MASK	(TX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RX_RING_MOD_MASK	(RX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TX_RING_LEN_BITS	((LANCE_LOG_TX_BUFFERS) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RX_RING_LEN_BITS	((LANCE_LOG_RX_BUFFERS) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PKT_BUFF_SIZE		(1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RX_BUFF_SIZE		PKT_BUFF_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TX_BUFF_SIZE		PKT_BUFF_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* Each receive buffer is described by a receive message descriptor (RMD) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) struct lance_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	volatile unsigned short rmd0;	    /* low address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	volatile unsigned char  rmd1_bits;  /* descriptor bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	volatile unsigned char  rmd1_hadr;  /* high address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	volatile short    length;	    /* This length is 2s complement (negative)!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 					     * Buffer length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	volatile unsigned short mblength;   /* Actual number of bytes received */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* Ditto for TMD: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) struct lance_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	volatile unsigned short tmd0;	    /* low address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	volatile unsigned char  tmd1_bits;  /* descriptor bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	volatile unsigned char  tmd1_hadr;  /* high address of packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	volatile short    length;	    /* Length is 2s complement (negative)! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	volatile unsigned short misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) /* There are three memory structures accessed by the LANCE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69)  * the initialization block, the receive and transmit descriptor rings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70)  * and the data buffers themselves. In fact we might as well put the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71)  * init block,the Tx and Rx rings and the buffers together in memory:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) struct lance_init_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	volatile unsigned short mode;		/* Pre-set mode (reg. 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	volatile unsigned char phys_addr[6];	/* Physical ethernet address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	volatile unsigned filter[2];		/* Multicast filter (64 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* Receive and transmit ring base, along with extra bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	volatile unsigned short rx_ptr;		/* receive descriptor addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	volatile unsigned short rx_len;		/* receive len and high addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	volatile unsigned short tx_ptr;		/* transmit descriptor addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	volatile unsigned short tx_len;		/* transmit len and high addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* The Tx and Rx ring entries must be aligned on 8-byte boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * This will be true if this whole struct is 8-byte aligned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	volatile struct lance_tx_desc btx_ring[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	volatile struct lance_rx_desc brx_ring[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	volatile char tx_buf[TX_RING_SIZE][TX_BUFF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	volatile char rx_buf[RX_RING_SIZE][RX_BUFF_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	/* we use this just to make the struct big enough that we can move its startaddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * in order to force alignment to an eight byte boundary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* This is where we keep all the stuff the driver needs to know about.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98)  * I'm definitely unhappy about the mechanism for allowing specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99)  * drivers to add things...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct lance_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	unsigned long base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	volatile struct lance_init_block *init_block; /* CPU address of RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	volatile struct lance_init_block *lance_init_block; /* LANCE address of RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	int rx_new, tx_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	int rx_old, tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	int lance_log_rx_bufs, lance_log_tx_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	int rx_ring_mod_mask, tx_ring_mod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	int tpe;			/* TPE is selected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	int auto_select;		/* cable-selection is by carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	unsigned short busmaster_regval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned int irq;		/* IRQ to register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	/* This is because the HP LANCE is disgusting and you have to check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	 * a DIO-specific register every time you read/write the LANCE regs :-<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	 * [could we get away with making these some sort of macro?]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	void (*writerap)(void *, unsigned short);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	void (*writerdp)(void *, unsigned short);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	unsigned short (*readrdp)(void *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	spinlock_t devlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	char tx_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)  *		Am7990 Control and Status Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LE_CSR0		0x0000	/* LANCE Controller Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define LE_CSR1		0x0001	/* IADR[15:0] (bit0==0 ie word aligned) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LE_CSR2		0x0002	/* IADR[23:16] (high bits reserved) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define LE_CSR3		0x0003	/* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)  *		Bit definitions for CSR0 (LANCE Controller Status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LE_C0_ERR	0x8000	/* Error = BABL | CERR | MISS | MERR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LE_C0_BABL	0x4000	/* Babble: Transmitted too many bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define LE_C0_CERR	0x2000	/* No Heartbeat (10BASE-T) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define LE_C0_MISS	0x1000	/* Missed Frame (no rx buffer to put it in) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define LE_C0_MERR	0x0800	/* Memory Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define LE_C0_RINT	0x0400	/* Receive Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define LE_C0_TINT	0x0200	/* Transmit Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define LE_C0_IDON	0x0100	/* Initialization Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define LE_C0_INTR	0x0080	/* Interrupt Flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 				   = BABL | MISS | MERR | RINT | TINT | IDON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define LE_C0_INEA	0x0040	/* Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define LE_C0_RXON	0x0020	/* Receive On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define LE_C0_TXON	0x0010	/* Transmit On */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LE_C0_TDMD	0x0008	/* Transmit Demand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LE_C0_STOP	0x0004	/* Stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LE_C0_STRT	0x0002	/* Start */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LE_C0_INIT	0x0001	/* Initialize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  *		Bit definitions for CSR3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LE_C3_BSWP	0x0004	/* Byte Swap (on for big endian byte order) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define LE_C3_ACON	0x0002	/* ALE Control (on for active low ALE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define LE_C3_BCON	0x0001	/* Byte Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  *		Mode Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define LE_MO_PROM	0x8000	/* Promiscuous Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* these next ones 0x4000 -- 0x0080 are not available on the LANCE 7990,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * but they are in NetBSD's am7990.h, presumably for backwards-compatible chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define LE_MO_DRCVBC	0x4000	/* disable receive broadcast */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define LE_MO_DRCVPA	0x2000	/* disable physical address detection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define LE_MO_DLNKTST	0x1000	/* disable link status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LE_MO_DAPC	0x0800	/* disable automatic polarity correction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define LE_MO_MENDECL	0x0400	/* MENDEC loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define LE_MO_LRTTSEL	0x0200	/* lower RX threshold / TX mode selection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define LE_MO_PSEL1	0x0100	/* port selection bit1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define LE_MO_PSEL0	0x0080	/* port selection bit0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* and this one is from the C-LANCE data sheet... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define LE_MO_EMBA	0x0080	/* Enable Modified Backoff Algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 				   (C-LANCE, not original LANCE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define LE_MO_INTL	0x0040	/* Internal Loopback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define LE_MO_DRTY	0x0020	/* Disable Retry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define LE_MO_FCOLL	0x0010	/* Force Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define LE_MO_DXMTFCS	0x0008	/* Disable Transmit CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define LE_MO_LOOP	0x0004	/* Loopback Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define LE_MO_DTX	0x0002	/* Disable Transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define LE_MO_DRX	0x0001	/* Disable Receiver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)  *		Receive Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define LE_R1_OWN	0x80	/* LANCE owns the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define LE_R1_ERR	0x40	/* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define LE_R1_FRA	0x20	/* Framing Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define LE_R1_OFL	0x10	/* Overflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define LE_R1_CRC	0x08	/* CRC Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define LE_R1_BUF	0x04	/* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define LE_R1_SOP	0x02	/* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define LE_R1_EOP	0x01	/* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define LE_R1_POK	0x03	/* Packet is complete: SOP + EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  *		Transmit Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define LE_T1_OWN	0x80	/* LANCE owns the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define LE_T1_ERR	0x40	/* Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define LE_T1_RES	0x20	/* Reserved, LANCE writes this with a zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define LE_T1_EMORE	0x10	/* More than one retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define LE_T1_EONE	0x08	/* One retry needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define LE_T1_EDEF	0x04	/* Deferred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define LE_T1_SOP	0x02	/* Start of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define LE_T1_EOP	0x01	/* End of Packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define LE_T1_POK	0x03	/* Packet is complete: SOP + EOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)  *		Error Flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define LE_T3_BUF	0x8000	/* Buffer Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define LE_T3_UFL	0x4000	/* Underflow Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define LE_T3_LCOL	0x1000	/* Late Collision */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define LE_T3_CLOS	0x0800	/* Loss of Carrier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define LE_T3_RTY	0x0400	/* Retry Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define LE_T3_TDR	0x03ff	/* Time Domain Reflectometry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* Miscellaneous useful macros */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TX_BUFFS_AVAIL ((lp->tx_old <= lp->tx_new) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 			lp->tx_old + lp->tx_ring_mod_mask - lp->tx_new : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 			lp->tx_old - lp->tx_new - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* The LANCE only uses 24 bit addresses. This does the obvious thing. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define LANCE_ADDR(x) ((int)(x) & ~0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* Now the prototypes we export */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) int lance_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int lance_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) netdev_tx_t lance_start_xmit(struct sk_buff *skb, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) void lance_set_multicast(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) void lance_tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) void lance_poll(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif /* ndef _7990_H */