^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 7990.c -- LANCE ethernet IC generic routines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This is an attempt to separate out the bits of various ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * drivers that are common because they all use the AMD 7990 LANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (Local Area Network Controller for Ethernet) chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (C) 05/1998 Peter Maydell <pmaydell@chiark.greenend.org.uk>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Most of this stuff was obtained by looking at other LANCE drivers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * in particular a2065.[ch]. The AMD C-LANCE datasheet was also helpful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * NB: this was made easy by the fact that Jes Sorensen had cleaned up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * most of a2025 and sunlance with the aim of merging them, so the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * common code was pretty obvious.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/fcntl.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/route.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/pgtable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Used for the temporal inet entries and routing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/socket.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #ifdef CONFIG_HP300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <asm/blinken.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "7990.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define WRITERAP(lp, x) out_be16(lp->base + LANCE_RAP, (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define WRITERDP(lp, x) out_be16(lp->base + LANCE_RDP, (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define READRDP(lp) in_be16(lp->base + LANCE_RDP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #if IS_ENABLED(CONFIG_HPLANCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #include "hplance.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #undef WRITERAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #undef WRITERDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #undef READRDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #if IS_ENABLED(CONFIG_MVME147_NET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Lossage Factor Nine, Mr Sulu. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define WRITERAP(lp, x) (lp->writerap(lp, x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define WRITERDP(lp, x) (lp->writerdp(lp, x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define READRDP(lp) (lp->readrdp(lp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* These inlines can be used if only CONFIG_HPLANCE is defined */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static inline void WRITERAP(struct lance_private *lp, __u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) out_be16(lp->base + HPLANCE_REGOFF + LANCE_RAP, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static inline void WRITERDP(struct lance_private *lp, __u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) out_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) static inline __u16 READRDP(struct lance_private *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) __u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) value = in_be16(lp->base + HPLANCE_REGOFF + LANCE_RDP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) } while ((in_8(lp->base + HPLANCE_STATUS) & LE_ACK) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* IS_ENABLED(CONFIG_HPLANCE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* debugging output macros, various flavours */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* #define TEST_HITS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #ifdef UNDEF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define PRINT_RINGS() \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) int t; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) for (t = 0; t < RX_RING_SIZE; t++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) printk("R%d: @(%02X %04X) len %04X, mblen %04X, bits %02X\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) t, ib->brx_ring[t].rmd1_hadr, ib->brx_ring[t].rmd0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) ib->brx_ring[t].length, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) ib->brx_ring[t].mblength, ib->brx_ring[t].rmd1_bits); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) for (t = 0; t < TX_RING_SIZE; t++) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) printk("T%d: @(%02X %04X) len %04X, misc %04X, bits %02X\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) t, ib->btx_ring[t].tmd1_hadr, ib->btx_ring[t].tmd0, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ib->btx_ring[t].length, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) ib->btx_ring[t].misc, ib->btx_ring[t].tmd1_bits); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PRINT_RINGS()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Load the CSR registers. The LANCE has to be STOPped when we do this! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void load_csrs(struct lance_private *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) volatile struct lance_init_block *aib = lp->lance_init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) leptr = LANCE_ADDR(aib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) WRITERAP(lp, LE_CSR1); /* load address of init block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) WRITERDP(lp, leptr & 0xFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) WRITERAP(lp, LE_CSR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) WRITERDP(lp, leptr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) WRITERAP(lp, LE_CSR3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) WRITERDP(lp, lp->busmaster_regval); /* set byteswap/ALEctrl/byte ctrl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Point back to csr0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* #define to 0 or 1 appropriately */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DEBUG_IRING 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Set up the Lance Rx and Tx rings and the init block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) static void lance_init_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) volatile struct lance_init_block *ib = lp->init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) volatile struct lance_init_block *aib; /* for LANCE_ADDR computations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) aib = lp->lance_init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) lp->rx_new = lp->tx_new = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) lp->rx_old = lp->tx_old = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ib->mode = LE_MO_PROM; /* normal, enable Tx & Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Copy the ethernet address to the lance init block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Notice that we do a byteswap if we're big endian.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * [I think this is the right criterion; at least, sunlance,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * a2065 and atarilance do the byteswap and lance.c (PC) doesn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * However, the datasheet says that the BSWAP bit doesn't affect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * the init block, so surely it should be low byte first for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * everybody? Um.]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * We could define the ib->physaddr as three 16bit values and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * use (addr[1] << 8) | addr[0] & co, but this is more efficient.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #ifdef __BIG_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ib->phys_addr[0] = dev->dev_addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ib->phys_addr[1] = dev->dev_addr[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ib->phys_addr[2] = dev->dev_addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ib->phys_addr[3] = dev->dev_addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ib->phys_addr[4] = dev->dev_addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) ib->phys_addr[5] = dev->dev_addr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ib->phys_addr[i] = dev->dev_addr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (DEBUG_IRING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) printk("TX rings:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) lp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Setup the Tx ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 0; i < (1 << lp->lance_log_tx_bufs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) leptr = LANCE_ADDR(&aib->tx_buf[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) ib->btx_ring[i].tmd0 = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) ib->btx_ring[i].tmd1_hadr = leptr >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) ib->btx_ring[i].tmd1_bits = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) ib->btx_ring[i].length = 0xf000; /* The ones required by tmd2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ib->btx_ring[i].misc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (DEBUG_IRING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) printk("%d: 0x%8.8x\n", i, leptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Setup the Rx ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) if (DEBUG_IRING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) printk("RX rings:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) for (i = 0; i < (1 << lp->lance_log_rx_bufs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) leptr = LANCE_ADDR(&aib->rx_buf[i][0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) ib->brx_ring[i].rmd0 = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) ib->brx_ring[i].rmd1_hadr = leptr >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ib->brx_ring[i].rmd1_bits = LE_R1_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* 0xf000 == bits that must be one (reserved, presumably) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) ib->brx_ring[i].length = -RX_BUFF_SIZE | 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ib->brx_ring[i].mblength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (DEBUG_IRING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) printk("%d: 0x%8.8x\n", i, leptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* Setup the initialization block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /* Setup rx descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) leptr = LANCE_ADDR(&aib->brx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ib->rx_len = (lp->lance_log_rx_bufs << 13) | (leptr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ib->rx_ptr = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) if (DEBUG_IRING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) printk("RX ptr: %8.8x\n", leptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* Setup tx descriptor pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) leptr = LANCE_ADDR(&aib->btx_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ib->tx_len = (lp->lance_log_tx_bufs << 13) | (leptr >> 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) ib->tx_ptr = leptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) if (DEBUG_IRING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) printk("TX ptr: %8.8x\n", leptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Clear the multicast filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ib->filter[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ib->filter[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) PRINT_RINGS();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* LANCE must be STOPped before we do this, too... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static int init_restart_lance(struct lance_private *lp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) WRITERDP(lp, LE_C0_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Need a hook here for sunlance ledma stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Wait for the lance to complete initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) for (i = 0; (i < 100) && !(READRDP(lp) & (LE_C0_ERR | LE_C0_IDON)); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) barrier();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if ((i == 100) || (READRDP(lp) & LE_C0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) printk("LANCE unopened after %d ticks, csr0=%4.4x.\n", i, READRDP(lp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Clear IDON by writing a "1", enable interrupts and start lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) WRITERDP(lp, LE_C0_IDON);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) WRITERDP(lp, LE_C0_INEA | LE_C0_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) static int lance_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Stop the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) WRITERDP(lp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) status = init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #ifdef DEBUG_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) printk("Lance restart=%d\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static int lance_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) volatile struct lance_init_block *ib = lp->init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) volatile struct lance_rx_desc *rd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) unsigned char bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #ifdef TEST_HITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #ifdef TEST_HITS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) printk("[");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) if (i == lp->rx_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) printk("%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) ib->brx_ring[i].rmd1_bits & LE_R1_OWN ? "_" : "X");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) printk("%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) ib->brx_ring[i].rmd1_bits & LE_R1_OWN ? "." : "1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) printk("]");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #ifdef CONFIG_HP300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) blinken_leds(0x40, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) WRITERDP(lp, LE_C0_RINT | LE_C0_INEA); /* ack Rx int, reenable ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) for (rd = &ib->brx_ring[lp->rx_new]; /* For each Rx ring we own... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) !((bits = rd->rmd1_bits) & LE_R1_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) rd = &ib->brx_ring[lp->rx_new]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* We got an incomplete frame? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if ((bits & LE_R1_POK) != LE_R1_POK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) } else if (bits & LE_R1_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Count only the end frame as a rx error,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * not the beginning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (bits & LE_R1_BUF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dev->stats.rx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (bits & LE_R1_CRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (bits & LE_R1_OFL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) if (bits & LE_R1_FRA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (bits & LE_R1_EOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) int len = (rd->mblength & 0xfff) - 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct sk_buff *skb = netdev_alloc_skb(dev, len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) if (!skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) rd->mblength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) rd->rmd1_bits = LE_R1_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) skb_reserve(skb, 2); /* 16 byte align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) skb_put(skb, len); /* make room */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) skb_copy_to_linear_data(skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) (unsigned char *)&(ib->rx_buf[lp->rx_new][0]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev->stats.rx_bytes += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Return the packet to the pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) rd->mblength = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) rd->rmd1_bits = LE_R1_OWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) lp->rx_new = (lp->rx_new + 1) & lp->rx_ring_mod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) static int lance_tx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) volatile struct lance_init_block *ib = lp->init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) volatile struct lance_tx_desc *td;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #ifdef CONFIG_HP300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) blinken_leds(0x80, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* csr0 is 2f3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* csr0 is 73 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) j = lp->tx_old;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) for (i = j; i != lp->tx_new; i = j) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) td = &ib->btx_ring[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* If we hit a packet not owned by us, stop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (td->tmd1_bits & LE_T1_OWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (td->tmd1_bits & LE_T1_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) status = td->misc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (status & LE_T3_RTY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (status & LE_T3_LCOL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dev->stats.tx_window_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (status & LE_T3_CLOS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev->stats.tx_carrier_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) if (lp->auto_select) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) lp->tpe = 1 - lp->tpe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) printk("%s: Carrier Lost, trying %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) lp->tpe ? "TPE" : "AUI");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Stop the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) WRITERDP(lp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* buffer errors and underflows turn off the transmitter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Restart the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (status & (LE_T3_BUF|LE_T3_UFL)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) printk("%s: Tx: ERR_BUF|ERR_UFL, restarting\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* Stop the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) WRITERDP(lp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) } else if ((td->tmd1_bits & LE_T1_POK) == LE_T1_POK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * So we don't count the packet more than once.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) td->tmd1_bits &= ~(LE_T1_POK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* One collision before packet was sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (td->tmd1_bits & LE_T1_EONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev->stats.collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* More than one collision, be optimistic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (td->tmd1_bits & LE_T1_EMORE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev->stats.collisions += 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev->stats.tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) j = (j + 1) & lp->tx_ring_mod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) lp->tx_old = j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) WRITERDP(lp, LE_C0_TINT | LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) lance_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct net_device *dev = (struct net_device *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int csr0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) spin_lock(&lp->devlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) WRITERAP(lp, LE_CSR0); /* LANCE Controller Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) csr0 = READRDP(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) PRINT_RINGS();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) if (!(csr0 & LE_C0_INTR)) { /* Check if any interrupt has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) spin_unlock(&lp->devlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) return IRQ_NONE; /* been generated by the Lance. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* Acknowledge all the interrupt sources ASAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) WRITERDP(lp, csr0 & ~(LE_C0_INEA|LE_C0_TDMD|LE_C0_STOP|LE_C0_STRT|LE_C0_INIT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if ((csr0 & LE_C0_ERR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Clear the error condition */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) WRITERDP(lp, LE_C0_BABL|LE_C0_ERR|LE_C0_MISS|LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (csr0 & LE_C0_RINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) lance_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (csr0 & LE_C0_TINT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) lance_tx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Log misc errors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) if (csr0 & LE_C0_BABL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dev->stats.tx_errors++; /* Tx babble. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (csr0 & LE_C0_MISS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev->stats.rx_errors++; /* Missed a Rx frame. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (csr0 & LE_C0_MERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) printk("%s: Bus master arbitration failure, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev->name, csr0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Restart the chip. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) WRITERDP(lp, LE_C0_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (lp->tx_full && netif_queue_stopped(dev) && (TX_BUFFS_AVAIL >= 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) lp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) WRITERDP(lp, LE_C0_BABL|LE_C0_CERR|LE_C0_MISS|LE_C0_MERR|LE_C0_IDON|LE_C0_INEA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) spin_unlock(&lp->devlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) int lance_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* Install the Interrupt handler. Or we could shunt this out to specific drivers? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (request_irq(lp->irq, lance_interrupt, IRQF_SHARED, lp->name, dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) res = lance_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) spin_lock_init(&lp->devlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) EXPORT_SYMBOL_GPL(lance_open);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int lance_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Stop the LANCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) WRITERDP(lp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) free_irq(lp->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) EXPORT_SYMBOL_GPL(lance_close);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) void lance_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) printk("lance_tx_timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) lance_reset(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) EXPORT_SYMBOL_GPL(lance_tx_timeout);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) netdev_tx_t lance_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) volatile struct lance_init_block *ib = lp->init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int entry, skblen, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) static int outs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (!TX_BUFFS_AVAIL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) skblen = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #ifdef DEBUG_DRIVER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* dump the packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) for (i = 0; i < 64; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) if ((i % 16) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) printk("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) printk("%2.2x ", skb->data[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) len = (skblen <= ETH_ZLEN) ? ETH_ZLEN : skblen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) entry = lp->tx_new & lp->tx_ring_mod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ib->btx_ring[entry].length = (-len) | 0xf000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ib->btx_ring[entry].misc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (skb->len < ETH_ZLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) memset((void *)&ib->tx_buf[entry][0], 0, ETH_ZLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) skb_copy_from_linear_data(skb, (void *)&ib->tx_buf[entry][0], skblen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Now, give the packet to the lance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ib->btx_ring[entry].tmd1_bits = (LE_T1_POK|LE_T1_OWN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) lp->tx_new = (lp->tx_new + 1) & lp->tx_ring_mod_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) outs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Kick the lance: transmit now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) WRITERDP(lp, LE_C0_INEA | LE_C0_TDMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev_consume_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) spin_lock_irqsave(&lp->devlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (TX_BUFFS_AVAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) lp->tx_full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) spin_unlock_irqrestore(&lp->devlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) EXPORT_SYMBOL_GPL(lance_start_xmit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /* taken from the depca driver via a2065.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) static void lance_load_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) volatile struct lance_init_block *ib = lp->init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) volatile u16 *mcast_table = (u16 *)&ib->filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u32 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* set all multicast bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) if (dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) ib->filter[0] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) ib->filter[1] = 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* clear the multicast filter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) ib->filter[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ib->filter[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) /* Add addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) netdev_for_each_mc_addr(ha, dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) crc = ether_crc_le(6, ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) crc = crc >> 26;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mcast_table[crc >> 4] |= 1 << (crc & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) void lance_set_multicast(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) volatile struct lance_init_block *ib = lp->init_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) int stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) stopped = netif_queue_stopped(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (!stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) while (lp->tx_old != lp->tx_new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) WRITERDP(lp, LE_C0_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) lance_init_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ib->mode |= LE_MO_PROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ib->mode &= ~LE_MO_PROM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) lance_load_multicast(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) load_csrs(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) init_restart_lance(lp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) if (!stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) EXPORT_SYMBOL_GPL(lance_set_multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) void lance_poll(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) struct lance_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) spin_lock(&lp->devlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) WRITERAP(lp, LE_CSR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) WRITERDP(lp, LE_C0_STRT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) spin_unlock(&lp->devlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) lance_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) EXPORT_SYMBOL_GPL(lance_poll);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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