^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef _ACENIC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define _ACENIC_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Generate TX index update each time, when TX ring is closed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Normally, this is not useful, because results in more dma (and irqs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * without TX_COAL_INTS_ONLY).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define USE_TX_COAL_NOW 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Addressing:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The Tigon uses 64-bit host addresses, regardless of their actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * length, and it expects a big-endian format. For 32 bit systems the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * upper 32 bits of the address are simply ignored (zero), however for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * little endian 64 bit systems (Alpha) this looks strange with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * two parts of the address word being swapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The addresses are split in two 32 bit words for all architectures
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * as some of them are in PCI shared memory and it is necessary to use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * readl/writel to access them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * The addressing code is derived from Pete Wyckoff's work, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * modified to deal properly with readl/writel usage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct ace_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 pad0[16]; /* PCI control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 HostCtrl; /* 0x40 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 LocalCtrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 pad1[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 MiscCfg; /* 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 pad2[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 PciState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u32 pad3[2]; /* 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 WinBase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 WinData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 pad4[12]; /* 0x70 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 DmaWriteState; /* 0xa0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 pad5[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 DmaReadState; /* 0xb0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 pad6[26];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 AssistState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 pad7[8]; /* 0x120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 CpuCtrl; /* 0x140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 Pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 pad8[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 SramAddr; /* 0x154 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 SramData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 pad9[49];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 MacRxState; /* 0x220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 pad10[7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u32 CpuBCtrl; /* 0x240 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u32 PcB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) u32 pad11[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) u32 SramBAddr; /* 0x254 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 SramBData;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 pad12[105];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 pad13[32]; /* 0x400 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 Stats[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 Mb0Hi; /* 0x500 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 Mb0Lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 Mb1Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 CmdPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 Mb2Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 TxPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 Mb3Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 RxStdPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 Mb4Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 RxJumboPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u32 Mb5Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 RxMiniPrd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 Mb6Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 Mb6Lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 Mb7Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 Mb7Lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 Mb8Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 Mb8Lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 Mb9Hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 Mb9Lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 MbAHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 MbALo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 MbBHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 MbBLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 MbCHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 MbCLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 MbDHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 MbDLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 MbEHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 MbELo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 MbFHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 MbFLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 pad14[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 MacAddrHi; /* 0x600 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 MacAddrLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 InfoPtrHi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 InfoPtrLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 MultiCastHi; /* 0x610 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 MultiCastLo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 ModeStat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 DmaReadCfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 DmaWriteCfg; /* 0x620 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 TxBufRat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 EvtCsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u32 CmdCsm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u32 TuneRxCoalTicks;/* 0x630 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 TuneTxCoalTicks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 TuneStatTicks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 TuneMaxTxDesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 TuneMaxRxDesc; /* 0x640 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) u32 TuneTrace;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 TuneLink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 TuneFastLink;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 TracePtr; /* 0x650 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 TraceStrt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 TraceLen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 IfIdx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 IfMtu; /* 0x660 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u32 MaskInt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) u32 GigLnkState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) u32 FastLnkState;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 pad16[4]; /* 0x670 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 RxRetCsm; /* 0x680 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 pad17[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 CmdRng[64]; /* 0x700 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 Window[0x200];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) typedef struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 addrhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 addrlo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) } aceaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ACE_WINDOW_SIZE 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ACE_JUMBO_MTU 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ACE_STD_MTU 1500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ACE_TRACE_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * Host control register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IN_INT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLR_INT 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HW_RESET 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define BYTE_SWAP 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WORD_SWAP 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MASK_INTS 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Local control register bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EEPROM_DATA_IN 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EEPROM_DATA_OUT 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EEPROM_WRITE_ENABLE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EEPROM_CLK_OUT 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define EEPROM_BASE 0xa0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EEPROM_WRITE_SELECT 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EEPROM_READ_SELECT 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SRAM_BANK_512K 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * udelay() values for when clocking the eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define ACE_SHORT_DELAY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define ACE_LONG_DELAY 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * Misc Config bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SYNC_SRAM_TIMING 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * CPU state bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CPU_RESET 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CPU_TRACE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CPU_PROM_FAILED 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CPU_HALT 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CPU_HALTED 0xffff0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * PCI State bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define DMA_READ_MAX_4 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define DMA_READ_MAX_16 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define DMA_READ_MAX_32 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define DMA_READ_MAX_64 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DMA_READ_MAX_128 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DMA_READ_MAX_256 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DMA_READ_MAX_1K 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DMA_WRITE_MAX_4 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DMA_WRITE_MAX_16 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DMA_WRITE_MAX_32 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DMA_WRITE_MAX_64 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DMA_WRITE_MAX_128 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define DMA_WRITE_MAX_256 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DMA_WRITE_MAX_1K 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DMA_READ_WRITE_MASK 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MEM_READ_MULTIPLE 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PCI_66MHZ 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PCI_32BIT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define DMA_WRITE_ALL_ALIGN 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define READ_CMD_MEM 0x06000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define WRITE_CMD_MEM 0x70000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * Mode status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ACE_BYTE_SWAP_BD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ACE_WORD_SWAP_BD 0x04 /* not actually used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ACE_WARN 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ACE_BYTE_SWAP_DMA 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ACE_NO_JUMBO_FRAG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ACE_FATAL 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * DMA config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define DMA_THRESH_1W 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define DMA_THRESH_2W 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define DMA_THRESH_4W 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define DMA_THRESH_8W 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define DMA_THRESH_16W 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DMA_THRESH_32W 0x0 /* not described in doc, but exists. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * Tuning parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TICKS_PER_SEC 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * Link bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define LNK_PREF 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define LNK_10MB 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define LNK_100MB 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define LNK_1000MB 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define LNK_FULL_DUPLEX 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define LNK_HALF_DUPLEX 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define LNK_TX_FLOW_CTL_Y 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define LNK_NEG_ADVANCED 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define LNK_RX_FLOW_CTL_Y 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define LNK_NIC 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define LNK_JAM 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define LNK_JUMBO 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define LNK_ALTEON 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define LNK_NEG_FCTL 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define LNK_NEGOTIATE 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define LNK_ENABLE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define LNK_UP 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * Event definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define EVT_RING_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define EVT_RING_SIZE (EVT_RING_ENTRIES * sizeof(struct event))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct event {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #ifdef __LITTLE_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 idx:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u32 code:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) u32 evt:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u32 evt:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 code:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u32 idx:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define E_FW_RUNNING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define E_STATS_UPDATED 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define E_STATS_UPDATE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define E_LNK_STATE 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define E_C_LINK_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define E_C_LINK_DOWN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define E_C_LINK_10_100 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define E_ERROR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define E_C_ERR_INVAL_CMD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define E_C_ERR_UNIMP_CMD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define E_C_ERR_BAD_CFG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define E_MCAST_LIST 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define E_C_MCAST_ADDR_ADD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define E_C_MCAST_ADDR_DEL 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define E_RESET_JUMBO_RNG 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * Commands
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CMD_RING_ENTRIES 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #ifdef __LITTLE_ENDIAN_BITFIELD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) u32 idx:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) u32 code:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) u32 evt:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) u32 evt:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u32 code:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u32 idx:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define C_HOST_STATE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define C_C_STACK_UP 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define C_C_STACK_DOWN 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define C_FDR_FILTERING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define C_C_FDR_FILT_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define C_C_FDR_FILT_DISABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define C_SET_RX_PRD_IDX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define C_UPDATE_STATS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define C_RESET_JUMBO_RNG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define C_ADD_MULTICAST_ADDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define C_DEL_MULTICAST_ADDR 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define C_SET_PROMISC_MODE 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define C_C_PROMISC_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define C_C_PROMISC_DISABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define C_LNK_NEGOTIATION 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define C_C_NEGOTIATE_BOTH 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define C_C_NEGOTIATE_GIG 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define C_C_NEGOTIATE_10_100 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define C_SET_MAC_ADDR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define C_CLEAR_PROFILE 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define C_SET_MULTICAST_MODE 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define C_C_MCAST_ENABLE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define C_C_MCAST_DISABLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define C_CLEAR_STATS 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define C_SET_RX_JUMBO_PRD_IDX 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define C_REFRESH_STATS 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Descriptor flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define BD_FLG_TCP_UDP_SUM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define BD_FLG_IP_SUM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define BD_FLG_END 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define BD_FLG_MORE 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define BD_FLG_JUMBO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define BD_FLG_UCAST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define BD_FLG_MCAST 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define BD_FLG_BCAST 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define BD_FLG_TYP_MASK 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define BD_FLG_IP_FRAG 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define BD_FLG_IP_FRAG_END 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define BD_FLG_VLAN_TAG 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define BD_FLG_FRAME_ERROR 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define BD_FLG_COAL_NOW 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define BD_FLG_MINI 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Ring Control block flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define RCB_FLG_TCP_UDP_SUM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define RCB_FLG_IP_SUM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define RCB_FLG_NO_PSEUDO_HDR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define RCB_FLG_VLAN_ASSIST 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define RCB_FLG_COAL_INT_ONLY 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define RCB_FLG_TX_HOST_RING 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define RCB_FLG_IEEE_SNAP_SUM 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define RCB_FLG_EXT_RX_BD 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define RCB_FLG_RNG_DISABLE 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * TX ring - maximum TX ring entries for Tigon I's is 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define MAX_TX_RING_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TIGON_I_TX_RING_ENTRIES 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define TX_RING_SIZE (MAX_TX_RING_ENTRIES * sizeof(struct tx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TX_RING_BASE 0x3800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct tx_desc{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) aceaddr addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u32 flagsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * This is in PCI shared mem and must be accessed with readl/writel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * real layout is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #if __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 vlanres;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RX_STD_RING_ENTRIES 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RX_STD_RING_SIZE (RX_STD_RING_ENTRIES * sizeof(struct rx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define RX_JUMBO_RING_ENTRIES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define RX_JUMBO_RING_SIZE (RX_JUMBO_RING_ENTRIES *sizeof(struct rx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define RX_MINI_RING_ENTRIES 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define RX_MINI_RING_SIZE (RX_MINI_RING_ENTRIES *sizeof(struct rx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define RX_RETURN_RING_ENTRIES 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define RX_RETURN_RING_SIZE (RX_MAX_RETURN_RING_ENTRIES * \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) sizeof(struct rx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct rx_desc{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) aceaddr addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u16 idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u16 size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u16 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u16 tcp_udp_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u16 ip_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u16 ip_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u16 tcp_udp_csum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) u16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u16 err_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) u16 err_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u16 vlan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u32 opague;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * This struct is shared with the NIC firmware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct ring_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) aceaddr rngptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #ifdef __LITTLE_ENDIAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u16 max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u16 max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u32 pad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct ace_mac_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 excess_colls;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 coll_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 coll_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 coll_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 coll_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 coll_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 coll_6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 coll_7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 coll_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 coll_9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 coll_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 coll_11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 coll_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 coll_13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 coll_14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 coll_15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 late_coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) u32 defers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) u32 crc_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) u32 underrun;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) u32 crs_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) u32 pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) u32 drop_ula;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) u32 drop_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 drop_fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) u32 drop_space;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) u32 coll;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) u32 kept_bc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) u32 kept_mc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) u32 kept_uc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct ace_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) u32 stats[256];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) } s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct ring_ctrl evt_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct ring_ctrl cmd_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct ring_ctrl tx_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct ring_ctrl rx_std_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) struct ring_ctrl rx_jumbo_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) struct ring_ctrl rx_mini_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct ring_ctrl rx_return_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) aceaddr evt_prd_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) aceaddr rx_ret_prd_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) aceaddr tx_csm_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) aceaddr stats2_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) struct ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * Funny... As soon as we add maplen on alpha, it starts to work
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * much slower. Hmm... is it because struct does not fit to one cacheline?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * So, split tx_ring_info.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct tx_ring_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) DEFINE_DMA_UNMAP_ADDR(mapping);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DEFINE_DMA_UNMAP_LEN(maplen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * struct ace_skb holding the rings of skb's. This is an awful lot of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * pointers, but I don't see any other smart mode to do this in an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * efficient manner ;-(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct ace_skb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct tx_ring_info tx_skbuff[MAX_TX_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct ring_info rx_std_skbuff[RX_STD_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct ring_info rx_mini_skbuff[RX_MINI_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct ring_info rx_jumbo_skbuff[RX_JUMBO_RING_ENTRIES];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * Struct private for the AceNIC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * Elements are grouped so variables used by the tx handling goes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * together, and will go into the same cache lines etc. in order to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * avoid cache line contention between the rx and tx handling on SMP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * Frequently accessed variables are put at the beginning of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * struct to help the compiler generate better/shorter code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct ace_private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct net_device *ndev; /* backpointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) struct ace_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) struct ace_regs __iomem *regs; /* register base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct ace_skb *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dma_addr_t info_dma; /* 32/64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) int version, link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) int promisc, mcast_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) * TX elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct tx_desc *tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 tx_prd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) volatile u32 tx_ret_csm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int tx_ring_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * RX elements
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) unsigned long std_refill_busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) __attribute__ ((aligned (SMP_CACHE_BYTES)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned long mini_refill_busy, jumbo_refill_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) atomic_t cur_rx_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) atomic_t cur_mini_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) atomic_t cur_jumbo_bufs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) u32 rx_std_skbprd, rx_mini_skbprd, rx_jumbo_skbprd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) u32 cur_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct rx_desc *rx_std_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct rx_desc *rx_jumbo_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) struct rx_desc *rx_mini_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) struct rx_desc *rx_return_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int tasklet_pending, jumbo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct tasklet_struct ace_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct event *evt_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) volatile u32 *evt_prd, *rx_ret_prd, *tx_csm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dma_addr_t tx_ring_dma; /* 32/64 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) dma_addr_t rx_ring_base_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) dma_addr_t evt_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) dma_addr_t evt_prd_dma, rx_ret_prd_dma, tx_csm_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) unsigned char *trace_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) struct net_device *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) volatile int fw_running;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int board_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) u16 pci_command;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) u8 pci_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #ifdef INDEX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) spinlock_t debug_lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) __attribute__ ((aligned (SMP_CACHE_BYTES)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) u32 last_tx, last_std_rx, last_mini_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int pci_using_dac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) u8 firmware_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) u8 firmware_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) u8 firmware_fix;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) u32 firmware_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #define TX_RESERVED MAX_SKB_FRAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static inline int tx_space (struct ace_private *ap, u32 csm, u32 prd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return (csm - prd - 1) & (ACE_TX_RING_ENTRIES(ap) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define tx_free(ap) tx_space((ap)->tx_ret_csm, (ap)->tx_prd, ap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #define tx_ring_full(ap, csm, prd) (tx_space(ap, csm, prd) <= TX_RESERVED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static inline void set_aceaddr(aceaddr *aa, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u64 baddr = (u64) addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) aa->addrlo = baddr & 0xffffffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) aa->addrhi = baddr >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static inline void ace_set_txprd(struct ace_regs __iomem *regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct ace_private *ap, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) #ifdef INDEX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) spin_lock_irqsave(&ap->debug_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) writel(value, ®s->TxPrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (value == ap->last_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) printk(KERN_ERR "AceNIC RACE ALERT! writing identical value "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "to tx producer (%i)\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) ap->last_tx = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) spin_unlock_irqrestore(&ap->debug_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) writel(value, ®s->TxPrd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static inline void ace_mask_irq(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) struct ace_private *ap = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct ace_regs __iomem *regs = ap->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (ACE_IS_TIGON_I(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) writel(1, ®s->MaskInt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) writel(readl(®s->HostCtrl) | MASK_INTS, ®s->HostCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ace_sync_irq(dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static inline void ace_unmask_irq(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct ace_private *ap = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct ace_regs __iomem *regs = ap->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) if (ACE_IS_TIGON_I(ap))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) writel(0, ®s->MaskInt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) writel(readl(®s->HostCtrl) & ~MASK_INTS, ®s->HostCtrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * Prototypes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int ace_init(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void ace_load_std_rx_ring(struct net_device *dev, int nr_bufs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void ace_load_mini_rx_ring(struct net_device *dev, int nr_bufs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void ace_load_jumbo_rx_ring(struct net_device *dev, int nr_bufs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static irqreturn_t ace_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int ace_load_firmware(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) static int ace_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static netdev_tx_t ace_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static int ace_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void ace_tasklet(struct tasklet_struct *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static void ace_dump_trace(struct ace_private *ap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void ace_set_multicast_list(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static int ace_change_mtu(struct net_device *dev, int new_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) static int ace_set_mac_addr(struct net_device *dev, void *p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) static void ace_set_rxtx_parms(struct net_device *dev, int jumbo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static int ace_allocate_descriptors(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void ace_free_descriptors(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static void ace_init_cleanup(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static struct net_device_stats *ace_get_stats(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int read_eeprom_byte(struct net_device *dev, unsigned long offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #endif /* _ACENIC_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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