^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef _SLIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define _SLIC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/spinlock_types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/u64_stats_sync.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SLIC_VGBSTAT_XPERR 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SLIC_VGBSTAT_XERRSHFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SLIC_VGBSTAT_XCSERR 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SLIC_VGBSTAT_XUFLOW 0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SLIC_VGBSTAT_XHLEN 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SLIC_VGBSTAT_NETERR 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SLIC_VGBSTAT_NERRSHFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SLIC_VGBSTAT_NERRMSK 0x1ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SLIC_VGBSTAT_NCSERR 0x103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SLIC_VGBSTAT_NUFLOW 0x102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SLIC_VGBSTAT_NHLEN 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SLIC_VGBSTAT_LNKERR 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SLIC_VGBSTAT_LERRMSK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SLIC_VGBSTAT_LDEARLY 0x86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SLIC_VGBSTAT_LBOFLO 0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SLIC_VGBSTAT_LCODERR 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SLIC_VGBSTAT_LDBLNBL 0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SLIC_VGBSTAT_LCRCERR 0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SLIC_VGBSTAT_LOFLO 0x81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SLIC_VGBSTAT_LUFLO 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SLIC_IRHDDR_FLEN_MSK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SLIC_IRHDDR_SVALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SLIC_IRHDDR_ERR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SLIC_VRHSTAT_802OE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SLIC_VRHSTAT_TPOFLO 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SLIC_VRHSTATB_802UE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SLIC_VRHSTATB_RCVE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SLIC_VRHSTATB_BUFF 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SLIC_VRHSTATB_CARRE 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SLIC_VRHSTATB_LONGE 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SLIC_VRHSTATB_PREA 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SLIC_VRHSTATB_CRC 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SLIC_VRHSTATB_DRBL 0x00400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SLIC_VRHSTATB_CODE 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SLIC_VRHSTATB_TPCSUM 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SLIC_VRHSTATB_TPHLEN 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SLIC_VRHSTATB_IPCSUM 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SLIC_VRHSTATB_IPLERR 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SLIC_VRHSTATB_IPHERR 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SLIC_CMD_XMT_REQ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SLIC_CMD_TYPE_DUMB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SLIC_RESET_MAGIC 0xDEAD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SLIC_ICR_INT_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SLIC_ICR_INT_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SLIC_ICR_INT_MASK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SLIC_ISR_ERR 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SLIC_ISR_RCV 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SLIC_ISR_CMD 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SLIC_ISR_IO 0x60000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SLIC_ISR_UPC 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SLIC_ISR_LEVENT 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SLIC_ISR_RMISS 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SLIC_ISR_UPCERR 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SLIC_ISR_XDROP 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SLIC_ISR_UPCBSY 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SLIC_ISR_PING_MASK 0x00700000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SLIC_ISR_UPCERR_MASK (SLIC_ISR_UPCERR | SLIC_ISR_UPCBSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SLIC_ISR_UPC_MASK (SLIC_ISR_UPC | SLIC_ISR_UPCERR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SLIC_WCS_START 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SLIC_WCS_COMPARE 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SLIC_RCVWCS_BEGIN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SLIC_RCVWCS_FINISH 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SLIC_MIICR_REG_16 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SLIC_MRV_REG16_XOVERON 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SLIC_GIG_LINKUP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SLIC_GIG_FULLDUPLEX 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SLIC_GIG_SPEED_MASK 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SLIC_GIG_SPEED_1000 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SLIC_GIG_SPEED_100 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SLIC_GIG_SPEED_10 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SLIC_GMCR_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SLIC_GMCR_GBIT 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SLIC_GMCR_FULLD 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SLIC_GMCR_GAPBB_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SLIC_GMCR_GAPR1_SHIFT 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SLIC_GMCR_GAPR2_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SLIC_GMCR_GAPBB_1000 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SLIC_GMCR_GAPR1_1000 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SLIC_GMCR_GAPR2_1000 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SLIC_GMCR_GAPBB_100 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SLIC_GMCR_GAPR1_100 0x2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SLIC_GMCR_GAPR2_100 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SLIC_XCR_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SLIC_XCR_XMTEN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SLIC_XCR_PAUSEEN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SLIC_XCR_LOADRNG 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SLIC_GXCR_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SLIC_GXCR_XMTEN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SLIC_GXCR_PAUSEEN 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SLIC_GRCR_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SLIC_GRCR_RCVEN 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SLIC_GRCR_RCVALL 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SLIC_GRCR_RCVBAD 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SLIC_GRCR_CTLEN 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SLIC_GRCR_ADDRAEN 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SLIC_GRCR_HASHSIZE_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SLIC_GRCR_HASHSIZE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SLIC_REG_RESET 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Interrupt Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define SLIC_REG_ICR 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Interrupt status pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SLIC_REG_ISP 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SLIC_REG_ISR 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Header buffer address reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * 31-8 - phy addr of set of contiguous hdr buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 7-0 - number of buffers passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * Buffers are 256 bytes long on 256-byte boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SLIC_REG_HBAR 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Data buffer handle & address reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 4 sets of registers; Buffers are 2K bytes long 2 per 4K page.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SLIC_REG_DBAR 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* Xmt Cmd buf addr regs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * 1 per XMT interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * 31-5 - phy addr of host command buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 4-0 - length of cmd in multiples of 32 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * Buffers are 32 bytes up to 512 bytes long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SLIC_REG_CBAR 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Write control store */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SLIC_REG_WCS 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /*Response buffer address reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 31-8 - phy addr of set of contiguous response buffers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 7-0 - number of buffers passed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * Buffers are 32 bytes long on 32-byte boundaries.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SLIC_REG_RBAR 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Read statistics (UPR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define SLIC_REG_RSTAT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Read link status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define SLIC_REG_LSTAT 0x0048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Write Mac Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SLIC_REG_WMCFG 0x0050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Write phy register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define SLIC_REG_WPHY 0x0058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Rcv Cmd buf addr reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SLIC_REG_RCBAR 0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Read SLIC Config*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SLIC_REG_RCONFIG 0x0068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* Interrupt aggregation time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SLIC_REG_INTAGG 0x0070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Write XMIT config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SLIC_REG_WXCFG 0x0078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* Write RCV config reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SLIC_REG_WRCFG 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* Write rcv addr a low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SLIC_REG_WRADDRAL 0x0088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* Write rcv addr a high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define SLIC_REG_WRADDRAH 0x0090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* Write rcv addr b low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SLIC_REG_WRADDRBL 0x0098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Write rcv addr b high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SLIC_REG_WRADDRBH 0x00a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Low bits of mcast mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define SLIC_REG_MCASTLOW 0x00a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* High bits of mcast mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SLIC_REG_MCASTHIGH 0x00b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Ping the card */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SLIC_REG_PING 0x00b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Dump command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SLIC_REG_DUMP_CMD 0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Dump data pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SLIC_REG_DUMP_DATA 0x00c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* Read card's pci_status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SLIC_REG_PCISTATUS 0x00d0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Write hostid field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SLIC_REG_WRHOSTID 0x00d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Put card in a low power state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SLIC_REG_LOW_POWER 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* Force slic into quiescent state before soft reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SLIC_REG_QUIESCE 0x00e8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* Reset interface queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SLIC_REG_RESET_IFACE 0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Register is only written when it has changed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * Bits 63-32 for host i/f addrs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SLIC_REG_ADDR_UPPER 0x00f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* 64 bit Header buffer address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SLIC_REG_HBAR64 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* 64 bit Data buffer handle & address reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SLIC_REG_DBAR64 0x0108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* 64 bit Xmt Cmd buf addr regs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SLIC_REG_CBAR64 0x0110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 64 bit Response buffer address reg.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SLIC_REG_RBAR64 0x0118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* 64 bit Rcv Cmd buf addr reg*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SLIC_REG_RCBAR64 0x0120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Read statistics (64 bit UPR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SLIC_REG_RSTAT64 0x0128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* Download Gigabit RCV sequencer ucode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define SLIC_REG_RCV_WCS 0x0130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* Write VlanId field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SLIC_REG_WRVLANID 0x0138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Read Transformer info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SLIC_REG_READ_XF_INFO 0x0140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Write Transformer info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SLIC_REG_WRITE_XF_INFO 0x0148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Write card ticks per second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define SLIC_REG_TICKS_PER_SEC 0x0170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define SLIC_REG_HOSTID 0x1554
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PCI_VENDOR_ID_ALACRITECH 0x139A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PCI_DEVICE_ID_ALACRITECH_MOJAVE 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1 0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1_2 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PCI_SUBDEVICE_ID_ALACRITECH_1000X1F 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PCI_SUBDEVICE_ID_ALACRITECH_CICADA 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PCI_SUBDEVICE_ID_ALACRITECH_SES1001T 0x2006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PCI_SUBDEVICE_ID_ALACRITECH_SES1001F 0x2007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PCI_DEVICE_ID_ALACRITECH_OASIS 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XT 0x000B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2002XF 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XT 0x000D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2001XF 0x000E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104EF 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2104ET 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102EF 0x0011
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PCI_SUBDEVICE_ID_ALACRITECH_SEN2102ET 0x0012
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Note: power of two required for number descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define SLIC_NUM_RX_LES 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define SLIC_RX_BUFF_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define SLIC_RX_BUFF_ALIGN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define SLIC_RX_BUFF_HDR_SIZE 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define SLIC_MAX_REQ_RX_DESCS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define SLIC_NUM_TX_DESCS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define SLIC_TX_DESC_ALIGN 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SLIC_MIN_TX_WAKEUP_DESCS 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SLIC_MAX_REQ_TX_DESCS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define SLIC_MAX_TX_COMPLETIONS 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define SLIC_NUM_STAT_DESCS 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SLIC_STATS_DESC_ALIGN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SLIC_NUM_STAT_DESC_ARRAYS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SLIC_INVALID_STAT_DESC_IDX 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SLIC_NAPI_WEIGHT 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define SLIC_UPR_LSTAT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define SLIC_UPR_CONFIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define SLIC_EEPROM_SIZE 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define SLIC_EEPROM_MAGIC 0xa5a5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define SLIC_FIRMWARE_MOJAVE "slicoss/gbdownload.sys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define SLIC_FIRMWARE_OASIS "slicoss/oasisdownload.sys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define SLIC_RCV_FIRMWARE_MOJAVE "slicoss/gbrcvucode.sys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define SLIC_RCV_FIRMWARE_OASIS "slicoss/oasisrcvucode.sys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define SLIC_FIRMWARE_MIN_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SLIC_FIRMWARE_MAX_SECTIONS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define SLIC_MODEL_MOJAVE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SLIC_MODEL_OASIS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define SLIC_INC_STATS_COUNTER(st, counter) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u64_stats_update_begin(&(st)->syncp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) (st)->counter++; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u64_stats_update_end(&(st)->syncp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define SLIC_GET_STATS_COUNTER(newst, st, counter) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned int start; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) start = u64_stats_fetch_begin_irq(&(st)->syncp); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) newst = (st)->counter; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } while (u64_stats_fetch_retry_irq(&(st)->syncp, start)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct slic_upr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct slic_upr_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bool pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* upr list lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* SLIC EEPROM structure for Mojave */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) struct slic_mojave_eeprom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5'*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) __le16 flash_size; /* 02 Flash size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) __le16 eeprom_size; /* 03 EEPROM Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) __le16 vendor_id; /* 04 Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) __le16 dev_id; /* 05 Device ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 rev_id; /* 06 Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u8 class_code[3]; /* 07 Class Code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 irqpin_dbg; /* 08 Debug Interrupt pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 irqpin; /* Network Interrupt Pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u8 min_grant; /* 09 Minimum grant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u8 max_lat; /* Maximum Latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) __le16 pci_stat; /* 10 PCI Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) __le16 sub_vendor_id; /* 11 Subsystem Vendor Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) __le16 sub_id; /* 12 Subsystem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) __le16 dev_id_dbg; /* 13 Debug Device Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) __le16 ramrom; /* 14 Dram/Rom function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes * 64K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) __le16 rom_size2pci; /* 16 ROM extension size to PCI (bytes * 4k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u8 pad[2]; /* 17 Padding */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) u8 freetime; /* 18 FreeTime setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u8 ifctrl; /* 10-bit interface control (Mojave only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __le16 dram_size; /* 19 DRAM size (bytes * 64k) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u8 mac[ETH_ALEN]; /* 20 MAC addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u8 mac2[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) u8 pad2[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) u16 dev_id2; /* Device ID for 2nd PCI function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) u8 irqpin2; /* Interrupt pin for 2nd PCI function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u8 class_code2[3]; /* Class Code for 2nd PCI function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u16 cfg_byte6; /* Config Byte 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) u16 pme_cap; /* Power Mgment capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) u16 nwclk_ctrl; /* NetworkClockControls */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) u8 fru_format; /* Alacritech FRU format type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) u8 fru_assembly[6]; /* Alacritech FRU information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u8 fru_rev[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u8 fru_serial[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 fru_pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u8 oem_fru[28]; /* optional OEM FRU format type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u8 pad3[4]; /* Pad to 128 bytes - includes 2 cksum bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * (if OEM FRU info exists) and two unusable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * bytes at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* SLIC EEPROM structure for Oasis */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct slic_oasis_eeprom {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __le16 id; /* 00 EEPROM/FLASH Magic code 'A5A5' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) __le16 eeprom_code_size;/* 01 Size of EEPROM Codes (bytes * 4)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) __le16 spidev0_cfg; /* 02 Flash Config for SPI device 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) __le16 spidev1_cfg; /* 03 Flash Config for SPI device 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) __le16 vendor_id; /* 04 Vendor ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) __le16 dev_id; /* 05 Device ID (function 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) u8 rev_id; /* 06 Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) u8 class_code0[3]; /* 07 Class Code for PCI function 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) u8 irqpin1; /* 08 Interrupt pin for PCI function 1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) u8 class_code1[3]; /* 09 Class Code for PCI function 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) u8 irqpin2; /* 10 Interrupt pin for PCI function 2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) u8 irqpin0; /* Interrupt pin for PCI function 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) u8 min_grant; /* 11 Minimum grant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) u8 max_lat; /* Maximum Latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __le16 sub_vendor_id; /* 12 Subsystem Vendor Id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) __le16 sub_id; /* 13 Subsystem ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __le16 flash_size; /* 14 Flash size (bytes / 4K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) __le16 dram_size2pci; /* 15 DRAM size to PCI (bytes / 64K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) __le16 rom_size2pci; /* 16 Flash (ROM extension) size to PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) * (bytes / 4K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) __le16 dev_id1; /* 17 Device Id (function 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) __le16 dev_id2; /* 18 Device Id (function 2) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) __le16 dev_stat_cfg; /* 19 Device Status Config Bytes 6-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) __le16 pme_cap; /* 20 Power Mgment capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) u8 msi_cap; /* 21 MSI capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) u8 clock_div; /* Clock divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) __le16 pci_stat_lo; /* 22 PCI Status bits 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) __le16 pci_stat_hi; /* 23 PCI Status bits 31:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) __le16 dram_cfg_lo; /* 24 DRAM Configuration bits 15:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) __le16 dram_cfg_hi; /* 25 DRAM Configuration bits 31:16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __le16 dram_size; /* 26 DRAM size (bytes / 64K) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) __le16 gpio_tbi_ctrl; /* 27 GPIO/TBI controls for functions 1/0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) __le16 eeprom_size; /* 28 EEPROM Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) u8 mac[ETH_ALEN]; /* 29 MAC addresses (2 ports) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) u8 mac2[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) u8 fru_format; /* 35 Alacritech FRU format type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) u8 fru_assembly[6]; /* Alacritech FRU information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) u8 fru_rev[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) u8 fru_serial[14];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) u8 fru_pad[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) u8 oem_fru[28]; /* optional OEM FRU information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) u8 pad[4]; /* Pad to 128 bytes - includes 2 checksum bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * (if OEM FRU info exists) and two unusable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * bytes at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) struct slic_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u64 rx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u64 rx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u64 rx_mcasts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u64 rx_errors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u64 tx_packets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u64 tx_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /* HW STATS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u64 rx_buff_miss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u64 tx_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) u64 irq_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* transport layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u64 rx_tpcsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u64 rx_tpoflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u64 rx_tphlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /* ip layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u64 rx_ipcsum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u64 rx_iplen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) u64 rx_iphlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* link layer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u64 rx_early;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u64 rx_buffoflow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u64 rx_lcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u64 rx_drbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u64 rx_crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) u64 rx_oflow802;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u64 rx_uflow802;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* oasis only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) u64 tx_carrier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct u64_stats_sync syncp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct slic_shmem_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) __le32 isr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) __le32 link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct slic_shmem {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dma_addr_t isr_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dma_addr_t link_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct slic_shmem_data *shmem_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct slic_rx_info_oasis {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) __le32 frame_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) __le32 frame_status_b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) __le32 time_stamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) __le32 checksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct slic_rx_info_mojave {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) __le32 frame_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) __le16 byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) __le16 tp_chksum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) __le16 ctx_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) __le16 mac_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) __le16 buff_lnk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) struct slic_stat_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) __le32 hnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) __u8 pad[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) __u8 pad2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct slic_stat_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct slic_stat_desc *descs[SLIC_NUM_STAT_DESC_ARRAYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) dma_addr_t paddr[SLIC_NUM_STAT_DESC_ARRAYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) unsigned int addr_offset[SLIC_NUM_STAT_DESC_ARRAYS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) unsigned int active_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned int done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) size_t mem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct slic_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) __le32 hnd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) __le32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u8 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) __le16 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) __le32 totlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) __le32 paddrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) __le32 paddrh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) __le32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) __le32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct slic_tx_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) DEFINE_DMA_UNMAP_ADDR(map_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) DEFINE_DMA_UNMAP_LEN(map_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct slic_tx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dma_addr_t desc_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct slic_tx_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) struct dma_pool *dma_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) struct slic_tx_buffer *txbuffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) unsigned int put_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) unsigned int done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) struct slic_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 pad[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) __le32 buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct slic_rx_buffer {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) DEFINE_DMA_UNMAP_ADDR(map_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) DEFINE_DMA_UNMAP_LEN(map_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) unsigned int addr_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct slic_rx_queue {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct slic_rx_buffer *rxbuffs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned int done_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) unsigned int put_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct slic_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* upper address setting lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) spinlock_t upper_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct slic_shmem shmem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) struct slic_rx_queue rxq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) struct slic_tx_queue txq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct slic_stat_queue stq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) struct slic_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) struct slic_upr_list upr_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* link configuration lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) spinlock_t link_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) bool promisc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) unsigned int duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) bool is_fiber;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned char model;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static inline u32 slic_read(struct slic_device *sdev, unsigned int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return ioread32(sdev->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static inline void slic_write(struct slic_device *sdev, unsigned int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) iowrite32(val, sdev->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) static inline void slic_flush_write(struct slic_device *sdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) (void)ioread32(sdev->regs + SLIC_REG_HOSTID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #endif /* _SLIC_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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