^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Copyright © 2005 Agere Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * http://www.agere.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * SOFTWARE LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * This software is provided subject to the following terms and conditions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * which you should read carefully before using the software. Using this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * software indicates your acceptance of these terms and conditions. If you do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * not agree with these terms and conditions, do not use the software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright © 2005 Agere Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Redistribution and use in source or binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * modifications, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * . Redistributions of source code must retain the above copyright notice, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * list of conditions and the following Disclaimer as comments in the code as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * well as in the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * . Redistributions in binary form must reproduce the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * this list of conditions and the following Disclaimer in the documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * . Neither the name of Agere Systems Inc. nor the names of the contributors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * may be used to endorse or promote products derived from this software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * Disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define DRIVER_NAME "et131x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* EEPROM registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* LBCIF Register Groups (addressed via 32-bit offsets) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define LBCIF_DWORD0_GROUP 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define LBCIF_DWORD1_GROUP 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* LBCIF Registers (addressed via 8-bit offsets) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define LBCIF_ADDRESS_REGISTER 0xAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define LBCIF_DATA_REGISTER 0xB0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define LBCIF_CONTROL_REGISTER 0xB1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define LBCIF_STATUS_REGISTER 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* LBCIF Control Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define LBCIF_CONTROL_SEQUENTIAL_READ 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define LBCIF_CONTROL_PAGE_WRITE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define LBCIF_CONTROL_EEPROM_RELOAD 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define LBCIF_CONTROL_TWO_BYTE_ADDR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define LBCIF_CONTROL_I2C_WRITE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define LBCIF_CONTROL_LBCIF_ENABLE 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* LBCIF Status Register Bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define LBCIF_STATUS_PHY_QUEUE_AVAIL 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define LBCIF_STATUS_I2C_IDLE 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define LBCIF_STATUS_ACK_ERROR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define LBCIF_STATUS_GENERAL_ERROR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define LBCIF_STATUS_CHECKSUM_ERROR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define LBCIF_STATUS_EEPROM_PRESENT 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* START OF GLOBAL REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* 10bit registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * Tx queue start address reg in global address map at address 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * tx queue end address reg in global address map at address 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * rx queue start address reg in global address map at address 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * rx queue end address reg in global address map at address 0x000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* structure for power management control status reg in global address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * located at address 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * jagcore_rx_rdy bit 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * jagcore_tx_rdy bit 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * phy_lped_en bit 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * phy_sw_coma bit 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * rxclk_gate bit 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * txclk_gate bit 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * sysclk_gate bit 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * jagcore_rx_en bit 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * jagcore_tx_en bit 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * gigephy_en bit 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ET_PM_PHY_SW_COMA 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ET_PMCSR_INIT 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Interrupt status reg at address 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ET_INTR_TXDMA_ISR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ET_INTR_TXDMA_ERR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ET_INTR_RXDMA_XFR_DONE 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ET_INTR_RXDMA_FB_R0_LOW 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ET_INTR_RXDMA_FB_R1_LOW 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ET_INTR_RXDMA_STAT_LOW 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ET_INTR_RXDMA_ERR 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ET_INTR_WATCHDOG 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ET_INTR_WOL 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ET_INTR_PHY 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ET_INTR_TXMAC 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ET_INTR_RXMAC 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ET_INTR_MAC_STAT 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ET_INTR_SLV_TIMEOUT 0x00100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Interrupt mask register at address 0x001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * Interrupt alias clear mask reg at address 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Interrupt status alias reg at address 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * Same masks as above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Software reset reg at address 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * 0: txdma_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 1: rxdma_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 2: txmac_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 3: rxmac_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 4: mac_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * 5: mac_stat_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 6: mmc_sw_reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) *31: selfclr_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ET_RESET_ALL 0x007F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* SLV Timer reg at address 0x002C (low 24 bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) /* MSI Configuration reg at address 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ET_MSI_VECTOR 0x0000001F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ET_MSI_TC 0x00070000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Loopback reg located at address 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ET_LOOP_MAC 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ET_LOOP_DMA 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* GLOBAL Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * Located at address 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct global_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) u32 txq_start_addr; /* 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 txq_end_addr; /* 0x0004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 rxq_start_addr; /* 0x0008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 rxq_end_addr; /* 0x000C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 pm_csr; /* 0x0010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 unused; /* 0x0014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) u32 int_status; /* 0x0018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 int_mask; /* 0x001C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) u32 int_alias_clr_en; /* 0x0020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 int_status_alias; /* 0x0024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 sw_reset; /* 0x0028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 slv_timer; /* 0x002C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u32 msi_config; /* 0x0030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) u32 loopback; /* 0x0034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) u32 watchdog_timer; /* 0x0038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* START OF TXDMA REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* txdma control status reg at address 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ET_TXDMA_CSR_HALT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ET_TXDMA_DROP_TLP 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ET_TXDMA_CACHE_THRS 0x000000F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ET_TXDMA_CACHE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ET_TXDMA_SNGL_EPKT 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ET_TXDMA_CLASS 0x00001E00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* structure for txdma packet ring base address hi reg in txdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * located at address 0x1004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* structure for txdma packet ring base address low reg in txdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * located at address 0x1008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* structure for txdma packet ring number of descriptor reg in txdma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * map. Located at address 0x100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * 31-10: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * 9-0: pr ndes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ET_DMA12_MASK 0x0FFF /* 12 bit mask for DMA12W types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ET_DMA12_WRAP 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ET_DMA10_MASK 0x03FF /* 10 bit mask for DMA10W types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ET_DMA10_WRAP 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ET_DMA4_MASK 0x000F /* 4 bit mask for DMA4W types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ET_DMA4_WRAP 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define INDEX12(x) ((x) & ET_DMA12_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define INDEX10(x) ((x) & ET_DMA10_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define INDEX4(x) ((x) & ET_DMA4_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* 10bit DMA with wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * txdma tx queue write address reg in txdma address map at 0x1010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * txdma tx queue write address external reg in txdma address map at 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * txdma tx queue read address reg in txdma address map at 0x1018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * txdma status writeback address hi reg in txdma address map at0x101C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * txdma status writeback address lo reg in txdma address map at 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 10bit DMA with wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * txdma service request reg in txdma address map at 0x1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * structure for txdma service complete reg in txdma address map at 0x1028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 4bit DMA with wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * txdma tx descriptor cache read index reg in txdma address map at 0x102C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * txdma tx descriptor cache write index reg in txdma address map at 0x1030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * txdma error reg in txdma address map at address 0x1034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * 0: PyldResend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 1: PyldRewind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 4: DescrResend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 5: DescrRewind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 8: WrbkResend
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * 9: WrbkRewind
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Tx DMA Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Located at address 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct txdma_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 csr; /* 0x1000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 pr_base_hi; /* 0x1004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 pr_base_lo; /* 0x1008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 pr_num_des; /* 0x100C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 txq_wr_addr; /* 0x1010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 txq_wr_addr_ext; /* 0x1014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u32 txq_rd_addr; /* 0x1018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 dma_wb_base_hi; /* 0x101C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 dma_wb_base_lo; /* 0x1020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 service_request; /* 0x1024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u32 service_complete; /* 0x1028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 cache_rd_index; /* 0x102C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 cache_wr_index; /* 0x1030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u32 tx_dma_error; /* 0x1034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) u32 desc_abort_cnt; /* 0x1038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 payload_abort_cnt; /* 0x103c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) u32 writeback_abort_cnt; /* 0x1040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u32 desc_timeout_cnt; /* 0x1044 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 payload_timeout_cnt; /* 0x1048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) u32 writeback_timeout_cnt; /* 0x104c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 desc_error_cnt; /* 0x1050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) u32 payload_error_cnt; /* 0x1054 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 writeback_error_cnt; /* 0x1058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 dropped_tlp_cnt; /* 0x105c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 new_service_complete; /* 0x1060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 ethernet_packet_cnt; /* 0x1064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* END OF TXDMA REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* START OF RXDMA REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* structure for control status reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * Located at address 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * CSR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * 0: halt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * 1-3: tc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * 4: fbr_big_endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * 5: psr_big_endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * 6: pkt_big_endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * 7: dma_big_endian
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * 8-9: fbr0_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * 10: fbr0_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * 11-12: fbr1_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * 13: fbr1_enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * 14: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * 15: pkt_drop_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * 16: pkt_done_flush
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * 17: halt_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * 18-31: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ET_RXDMA_CSR_HALT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ET_RXDMA_CSR_FBR0_SIZE_LO 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ET_RXDMA_CSR_FBR0_SIZE_HI 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ET_RXDMA_CSR_FBR0_ENABLE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ET_RXDMA_CSR_FBR1_SIZE_LO 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ET_RXDMA_CSR_FBR1_SIZE_HI 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ET_RXDMA_CSR_FBR1_ENABLE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ET_RXDMA_CSR_HALT_STATUS 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) /* structure for dma writeback lo reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * located at address 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* structure for dma writeback hi reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * located at address 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* structure for number of packets done reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * located at address 0x200C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * 31-8: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * 7-0: num done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* structure for max packet time reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * located at address 0x2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * 31-18: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * 17-0: time done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* structure for rx queue read address reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * located at address 0x2014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* structure for rx queue read address external reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * located at address 0x2018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* structure for rx queue write address reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * located at address 0x201C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* structure for packet status ring base address lo reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * located at address 0x2020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* structure for packet status ring base address hi reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * located at address 0x2024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* structure for packet status ring number of descriptors reg in rxdma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * map. Located at address 0x2028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * 31-12: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * 11-0: psr ndes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define ET_RXDMA_PSR_NUM_DES_MASK 0xFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* structure for packet status ring available offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * located at address 0x202C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * 31-13: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) * 12: psr avail wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) * 11-0: psr avail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* structure for packet status ring full offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * located at address 0x2030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * 31-13: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * 12: psr full wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * 11-0: psr full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* structure for packet status ring access index reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * located at address 0x2034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * 31-5: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) * 4-0: psr_ai
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* structure for packet status ring minimum descriptors reg in rxdma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) * map. Located at address 0x2038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * 31-12: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * 11-0: psr_min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* structure for free buffer ring base lo address reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * located at address 0x203C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* structure for free buffer ring base hi address reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * located at address 0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* structure for free buffer ring number of descriptors reg in rxdma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * map. Located at address 0x2044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * 31-10: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * 9-0: fbr ndesc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* structure for free buffer ring 0 available offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * located at address 0x2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* structure for free buffer ring 0 full offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * located at address 0x204C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* structure for free buffer cache 0 full offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * located at address 0x2050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * 31-5: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * 4-0: fbc rdi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* structure for free buffer ring 0 minimum descriptor reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * located at address 0x2054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * 31-10: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * 9-0: fbr min
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* structure for free buffer ring 1 base address lo reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * located at address 0x2058 - 0x205C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Defined earlier (RXDMA_FBR_BASE_LO_t and RXDMA_FBR_BASE_HI_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* structure for free buffer ring 1 number of descriptors reg in rxdma address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * map. Located at address 0x2060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Defined earlier (RXDMA_FBR_NUM_DES_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* structure for free buffer ring 1 available offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * located at address 0x2064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * Defined Earlier (RXDMA_FBR_AVAIL_OFFSET_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* structure for free buffer ring 1 full offset reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * located at address 0x2068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * Defined Earlier (RXDMA_FBR_FULL_OFFSET_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* structure for free buffer cache 1 read index reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * located at address 0x206C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) * Defined Earlier (RXDMA_FBC_RD_INDEX_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* structure for free buffer ring 1 minimum descriptor reg in rxdma address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * located at address 0x2070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * Defined Earlier (RXDMA_FBR_MIN_DES_t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Rx DMA Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * Located at address 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct rxdma_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u32 csr; /* 0x2000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) u32 dma_wb_base_lo; /* 0x2004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 dma_wb_base_hi; /* 0x2008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) u32 num_pkt_done; /* 0x200C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 max_pkt_time; /* 0x2010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 rxq_rd_addr; /* 0x2014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u32 rxq_rd_addr_ext; /* 0x2018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 rxq_wr_addr; /* 0x201C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) u32 psr_base_lo; /* 0x2020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) u32 psr_base_hi; /* 0x2024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 psr_num_des; /* 0x2028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) u32 psr_avail_offset; /* 0x202C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u32 psr_full_offset; /* 0x2030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 psr_access_index; /* 0x2034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) u32 psr_min_des; /* 0x2038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) u32 fbr0_base_lo; /* 0x203C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u32 fbr0_base_hi; /* 0x2040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) u32 fbr0_num_des; /* 0x2044 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) u32 fbr0_avail_offset; /* 0x2048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) u32 fbr0_full_offset; /* 0x204C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) u32 fbr0_rd_index; /* 0x2050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) u32 fbr0_min_des; /* 0x2054 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) u32 fbr1_base_lo; /* 0x2058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) u32 fbr1_base_hi; /* 0x205C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u32 fbr1_num_des; /* 0x2060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) u32 fbr1_avail_offset; /* 0x2064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) u32 fbr1_full_offset; /* 0x2068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) u32 fbr1_rd_index; /* 0x206C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 fbr1_min_des; /* 0x2070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /* END OF RXDMA REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /* START OF TXMAC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) /* structure for control reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) * located at address 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) * 31-8: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) * 7: cklseg_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * 6: ckbcnt_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * 5: cksegnum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * 4: async_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * 3: fc_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * 2: mcif_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * 1: mif_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * 0: txmac_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define ET_TX_CTRL_FC_DISABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define ET_TX_CTRL_TXMAC_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* structure for shadow pointer reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) * located at address 0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) * 31-27: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) * 26-16: txq rd ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * 15-11: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * 10-0: txq wr ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* structure for error count reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * located at address 0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * 31-12: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * 11-8: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) * 7-4: txq_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * 3-0: fifo_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) /* structure for max fill reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * located at address 0x300C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * 31-12: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * 11-0: max fill
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /* structure for cf parameter reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * located at address 0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * 31-16: cfep
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * 15-0: cfpt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* structure for tx test reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * located at address 0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * 31-17: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * 16: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) * 15: txtest_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) * 14-11: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * 10-0: txq test pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* structure for error reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * located at address 0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) * 31-9: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * 8: fifo_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * 7-6: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * 5: ctrl2_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) * 4: txq_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) * 3: bcnt_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) * 2: lseg_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * 1: segnum_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * 0: seg0_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* structure for error interrupt reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * located at address 0x301C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * 31-9: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) * 8: fifo_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) * 7-6: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) * 5: ctrl2_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) * 4: txq_underrun
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * 3: bcnt_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * 2: lseg_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * 1: segnum_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * 0: seg0_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* structure for error interrupt reg in txmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * located at address 0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * 31-2: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * 1: bp_req
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * 0: bp_xonxoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Tx MAC Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct txmac_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u32 ctl; /* 0x3000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) u32 shadow_ptr; /* 0x3004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 err_cnt; /* 0x3008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 max_fill; /* 0x300C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) u32 cf_param; /* 0x3010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 tx_test; /* 0x3014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 err; /* 0x3018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) u32 err_int; /* 0x301C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 bp_ctrl; /* 0x3020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* END OF TXMAC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /* START OF RXMAC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /* structure for rxmac control reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) * located at address 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) * 31-7: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * 6: rxmac_int_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) * 5: async_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * 4: mif_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * 3: wol_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) * 2: pkt_filter_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) * 1: mcif_disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) * 0: rxmac_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define ET_RX_CTRL_WOL_DISABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define ET_RX_CTRL_RXMAC_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* structure for Wake On Lan Control and CRC 0 reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * located at address 0x4004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * 31-16: crc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * 15-12: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * 11: ignore_pp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) * 10: ignore_mp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) * 9: clr_intr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) * 8: ignore_link_chg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) * 7: ignore_uni
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * 6: ignore_multi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * 5: ignore_broad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * 4-0: valid_crc 4-0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) /* structure for CRC 1 and CRC 2 reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) * located at address 0x4008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * 31-16: crc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) * 15-0: crc1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* structure for CRC 3 and CRC 4 reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * located at address 0x400C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * 31-16: crc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) * 15-0: crc3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* structure for Wake On Lan Source Address Lo reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) * located at address 0x4010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * 31-24: sa3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) * 23-16: sa4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) * 15-8: sa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) * 7-0: sa6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define ET_RX_WOL_LO_SA3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) #define ET_RX_WOL_LO_SA4_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define ET_RX_WOL_LO_SA5_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) /* structure for Wake On Lan Source Address Hi reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * located at address 0x4014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * 31-16: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * 15-8: sa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * 7-0: sa2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) #define ET_RX_WOL_HI_SA1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* structure for Wake On Lan mask reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * located at address 0x4018 - 0x4064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* structure for Unicast Packet Filter Address 1 reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * located at address 0x4068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * 31-24: addr1_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * 23-16: addr1_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * 15-8: addr1_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * 7-0: addr1_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define ET_RX_UNI_PF_ADDR1_3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) #define ET_RX_UNI_PF_ADDR1_4_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define ET_RX_UNI_PF_ADDR1_5_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* structure for Unicast Packet Filter Address 2 reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) * located at address 0x406C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * 31-24: addr2_3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) * 23-16: addr2_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) * 15-8: addr2_5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) * 7-0: addr2_6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define ET_RX_UNI_PF_ADDR2_3_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define ET_RX_UNI_PF_ADDR2_4_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define ET_RX_UNI_PF_ADDR2_5_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* structure for Unicast Packet Filter Address 1 & 2 reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * located at address 0x4070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) * 31-24: addr2_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) * 23-16: addr2_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * 15-8: addr1_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * 7-0: addr1_2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define ET_RX_UNI_PF_ADDR2_1_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #define ET_RX_UNI_PF_ADDR2_2_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define ET_RX_UNI_PF_ADDR1_1_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* structure for Multicast Hash reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * located at address 0x4074 - 0x4080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* structure for Packet Filter Control reg in rxmac address map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * located at address 0x4084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) * 31-23: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) * 22-16: min_pkt_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) * 15-4: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * 3: filter_frag_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * 2: filter_uni_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) * 1: filter_multi_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * 0: filter_broad_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) #define ET_RX_PFCTRL_FRAG_FILTER_ENABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define ET_RX_PFCTRL_UNICST_FILTER_ENABLE 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) #define ET_RX_PFCTRL_MLTCST_FILTER_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define ET_RX_PFCTRL_BRDCST_FILTER_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* structure for Memory Controller Interface Control Max Segment reg in rxmac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) * address map. Located at address 0x4088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) * 31-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) * 9-2: max_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) * 1: fc_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) * 0: seg_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define ET_RX_MCIF_CTRL_MAX_SEG_SIZE_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) #define ET_RX_MCIF_CTRL_MAX_SEG_FC_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) #define ET_RX_MCIF_CTRL_MAX_SEG_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* structure for Memory Controller Interface Water Mark reg in rxmac address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * map. Located at address 0x408C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) * 31-26: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) * 25-16: mark_hi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) * 15-10: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * 9-0: mark_lo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /* structure for Rx Queue Dialog reg in rxmac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) * located at address 0x4090
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * 31-26: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) * 25-16: rd_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) * 15-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) * 9-0: wr_ptr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) /* structure for space available reg in rxmac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * located at address 0x4094
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) * 31-17: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) * 16: space_avail_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) * 15-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) * 9-0: space_avail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /* structure for management interface reg in rxmac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * located at address 0x4098
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) * 31-18: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) * 17: drop_pkt_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) * 16-0: drop_pkt_mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /* structure for Error reg in rxmac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) * located at address 0x409C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * 31-4: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * 3: mif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * 2: async
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * 1: pkt_filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * 0: mcif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Rx MAC Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct rxmac_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) u32 ctrl; /* 0x4000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) u32 crc0; /* 0x4004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) u32 crc12; /* 0x4008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) u32 crc34; /* 0x400C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) u32 sa_lo; /* 0x4010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) u32 sa_hi; /* 0x4014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) u32 mask0_word0; /* 0x4018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) u32 mask0_word1; /* 0x401C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) u32 mask0_word2; /* 0x4020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 mask0_word3; /* 0x4024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) u32 mask1_word0; /* 0x4028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) u32 mask1_word1; /* 0x402C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) u32 mask1_word2; /* 0x4030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) u32 mask1_word3; /* 0x4034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) u32 mask2_word0; /* 0x4038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) u32 mask2_word1; /* 0x403C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) u32 mask2_word2; /* 0x4040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 mask2_word3; /* 0x4044 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 mask3_word0; /* 0x4048 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 mask3_word1; /* 0x404C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u32 mask3_word2; /* 0x4050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) u32 mask3_word3; /* 0x4054 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) u32 mask4_word0; /* 0x4058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) u32 mask4_word1; /* 0x405C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) u32 mask4_word2; /* 0x4060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) u32 mask4_word3; /* 0x4064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) u32 uni_pf_addr1; /* 0x4068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) u32 uni_pf_addr2; /* 0x406C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 uni_pf_addr3; /* 0x4070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) u32 multi_hash1; /* 0x4074 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) u32 multi_hash2; /* 0x4078 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) u32 multi_hash3; /* 0x407C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) u32 multi_hash4; /* 0x4080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 pf_ctrl; /* 0x4084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 mcif_ctrl_max_seg; /* 0x4088 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) u32 mcif_water_mark; /* 0x408C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) u32 rxq_diag; /* 0x4090 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) u32 space_avail; /* 0x4094 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) u32 mif_ctrl; /* 0x4098 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) u32 err_reg; /* 0x409C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* END OF RXMAC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /* START OF MAC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* structure for configuration #1 reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * located at address 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * 31: soft reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * 30: sim reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * 29-20: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) * 19: reset rx mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) * 18: reset tx mc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) * 17: reset rx func
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) * 16: reset tx fnc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) * 15-9: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) * 8: loopback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) * 7-6: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) * 5: rx flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * 4: tx flow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * 3: syncd rx en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) * 2: rx enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * 1: syncd tx en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * 0: tx enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) #define ET_MAC_CFG1_SOFT_RESET 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define ET_MAC_CFG1_SIM_RESET 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #define ET_MAC_CFG1_RESET_RXMC 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define ET_MAC_CFG1_RESET_TXMC 0x00040000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define ET_MAC_CFG1_RESET_RXFUNC 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define ET_MAC_CFG1_RESET_TXFUNC 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) #define ET_MAC_CFG1_LOOPBACK 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define ET_MAC_CFG1_RX_FLOW 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) #define ET_MAC_CFG1_TX_FLOW 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define ET_MAC_CFG1_RX_ENABLE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) #define ET_MAC_CFG1_TX_ENABLE 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define ET_MAC_CFG1_WAIT 0x0000000A /* RX & TX syncd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) /* structure for configuration #2 reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) * located at address 0x5004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) * 31-16: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) * 15-12: preamble
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) * 11-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) * 9-8: if mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) * 7-6: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) * 5: huge frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) * 4: length check
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) * 3: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * 2: pad crc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) * 1: crc enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) * 0: full duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define ET_MAC_CFG2_PREAMBLE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #define ET_MAC_CFG2_IFMODE_MASK 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define ET_MAC_CFG2_IFMODE_1000 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) #define ET_MAC_CFG2_IFMODE_100 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define ET_MAC_CFG2_IFMODE_HUGE_FRAME 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) #define ET_MAC_CFG2_IFMODE_LEN_CHECK 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define ET_MAC_CFG2_IFMODE_PAD_CRC 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) #define ET_MAC_CFG2_IFMODE_CRC_ENABLE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define ET_MAC_CFG2_IFMODE_FULL_DPLX 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* structure for Interpacket gap reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) * located at address 0x5008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) * 31: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * 30-24: non B2B ipg 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * 23: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * 22-16: non B2B ipg 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) * 15-8: Min ifg enforce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) * 7-0: B2B ipg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) * structure for half duplex reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) * located at address 0x500C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) * 31-24: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) * 23-20: Alt BEB trunc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * 19: Alt BEB enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * 18: BP no backoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * 17: no backoff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * 16: excess defer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * 15-12: re-xmit max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * 11-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * 9-0: collision window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /* structure for Maximum Frame Length reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * located at address 0x5010: bits 0-15 hold the length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /* structure for Reserve 1 reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) * located at address 0x5014 - 0x5018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) /* structure for Test reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) * located at address 0x501C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) * test: bits 0-2, rest unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) /* structure for MII Management Configuration reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * located at address 0x5020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * 31: reset MII mgmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * 30-6: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * 5: scan auto increment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) * 4: preamble suppress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) * 3: undefined
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * 2-0: mgmt clock reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) #define ET_MAC_MIIMGMT_CLK_RST 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* structure for MII Management Command reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) * located at address 0x5024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) * bit 1: scan cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) * bit 0: read cycle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* structure for MII Management Address reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) * located at address 0x5028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) * 31-13: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) * 12-8: phy addr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) * 7-5: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * 4-0: register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) #define ET_MAC_MII_ADDR(phy, reg) ((phy) << 8 | (reg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* structure for MII Management Control reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) * located at address 0x502C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) * 31-16: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) * 15-0: phy control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* structure for MII Management Status reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * located at address 0x5030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * 31-16: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * 15-0: phy control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) #define ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK 0xFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* structure for MII Management Indicators reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * located at address 0x5034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) * 31-3: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * 2: not valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * 1: scanning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * 0: busy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) #define ET_MAC_MGMT_BUSY 0x00000001 /* busy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) #define ET_MAC_MGMT_WAIT 0x00000005 /* busy | not valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* structure for Interface Control reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) * located at address 0x5038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) * 31: reset if module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) * 30-28: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * 27: tbi mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * 26: ghd mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) * 25: lhd mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) * 24: phy mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) * 23: reset per mii
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) * 22-17: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) * 16: speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) * 15: reset pe100x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) * 14-11: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) * 10: force quiet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) * 9: no cipher
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) * 8: disable link fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) * 7: reset gpsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) * 6-1: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) * 0: enable jabber protection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #define ET_MAC_IFCTRL_GHDMODE (1 << 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) #define ET_MAC_IFCTRL_PHYMODE (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* structure for Interface Status reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * located at address 0x503C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * 31-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) * 9: excess_defer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * 8: clash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * 7: phy_jabber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * 6: phy_link_ok
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) * 5: phy_full_duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) * 4: phy_speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) * 3: pe100x_link_fail
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) * 2: pe10t_loss_carrier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) * 1: pe10t_sqe_error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * 0: pe10t_jabber
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* structure for Mac Station Address, Part 1 reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * located at address 0x5040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) * 31-24: Octet6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * 23-16: Octet5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * 15-8: Octet4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) * 7-0: Octet3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) #define ET_MAC_STATION_ADDR1_OC6_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) #define ET_MAC_STATION_ADDR1_OC5_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #define ET_MAC_STATION_ADDR1_OC4_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) /* structure for Mac Station Address, Part 2 reg in mac address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) * located at address 0x5044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) * 31-24: Octet2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) * 23-16: Octet1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) * 15-0: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) #define ET_MAC_STATION_ADDR2_OC2_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) #define ET_MAC_STATION_ADDR2_OC1_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* MAC Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct mac_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) u32 cfg1; /* 0x5000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) u32 cfg2; /* 0x5004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) u32 ipg; /* 0x5008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) u32 hfdp; /* 0x500C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) u32 max_fm_len; /* 0x5010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) u32 rsv1; /* 0x5014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) u32 rsv2; /* 0x5018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) u32 mac_test; /* 0x501C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) u32 mii_mgmt_cfg; /* 0x5020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) u32 mii_mgmt_cmd; /* 0x5024 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) u32 mii_mgmt_addr; /* 0x5028 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) u32 mii_mgmt_ctrl; /* 0x502C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) u32 mii_mgmt_stat; /* 0x5030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) u32 mii_mgmt_indicator; /* 0x5034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) u32 if_ctrl; /* 0x5038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) u32 if_stat; /* 0x503C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) u32 station_addr_1; /* 0x5040 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) u32 station_addr_2; /* 0x5044 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* END OF MAC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* START OF MAC STAT REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* structure for Carry Register One and it's Mask Register reg located in mac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * stat address map address 0x6130 and 0x6138.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * 31: tr64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) * 30: tr127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) * 29: tr255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) * 28: tr511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) * 27: tr1k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) * 26: trmax
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) * 25: trmgv
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) * 24-17: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) * 16: rbyt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) * 15: rpkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * 14: rfcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * 13: rmca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) * 12: rbca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * 11: rxcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * 10: rxpf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * 9: rxuo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * 8: raln
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * 7: rflr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * 6: rcde
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * 5: rcse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * 4: rund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * 3: rovr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * 2: rfrg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * 1: rjbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * 0: rdrp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* structure for Carry Register Two Mask Register reg in mac stat address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) * located at address 0x613C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) * 31-20: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) * 19: tjbr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) * 18: tfcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) * 17: txcf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) * 16: tovr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) * 15: tund
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) * 14: trfg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * 13: tbyt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * 12: tpkt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * 11: tmca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * 10: tbca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * 9: txpf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * 8: tdfr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * 7: tedf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * 6: tscl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * 5: tmcl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * 4: tlcl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * 3: txcl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * 2: tncl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) * 1: tpfh
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) * 0: tdrp
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* MAC STATS Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) struct macstat_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) u32 pad[32]; /* 0x6000 - 607C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) /* counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) u32 txrx_0_64_byte_frames; /* 0x6080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) u32 txrx_65_127_byte_frames; /* 0x6084 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) u32 txrx_128_255_byte_frames; /* 0x6088 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) u32 txrx_256_511_byte_frames; /* 0x608C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) u32 txrx_512_1023_byte_frames; /* 0x6090 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) u32 txrx_1024_1518_byte_frames; /* 0x6094 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) u32 txrx_1519_1522_gvln_frames; /* 0x6098 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) u32 rx_bytes; /* 0x609C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) u32 rx_packets; /* 0x60A0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) u32 rx_fcs_errs; /* 0x60A4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) u32 rx_multicast_packets; /* 0x60A8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u32 rx_broadcast_packets; /* 0x60AC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) u32 rx_control_frames; /* 0x60B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u32 rx_pause_frames; /* 0x60B4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) u32 rx_unknown_opcodes; /* 0x60B8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) u32 rx_align_errs; /* 0x60BC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) u32 rx_frame_len_errs; /* 0x60C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) u32 rx_code_errs; /* 0x60C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) u32 rx_carrier_sense_errs; /* 0x60C8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) u32 rx_undersize_packets; /* 0x60CC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) u32 rx_oversize_packets; /* 0x60D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) u32 rx_fragment_packets; /* 0x60D4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u32 rx_jabbers; /* 0x60D8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u32 rx_drops; /* 0x60DC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u32 tx_bytes; /* 0x60E0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) u32 tx_packets; /* 0x60E4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) u32 tx_multicast_packets; /* 0x60E8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) u32 tx_broadcast_packets; /* 0x60EC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) u32 tx_pause_frames; /* 0x60F0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) u32 tx_deferred; /* 0x60F4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) u32 tx_excessive_deferred; /* 0x60F8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) u32 tx_single_collisions; /* 0x60FC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) u32 tx_multiple_collisions; /* 0x6100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) u32 tx_late_collisions; /* 0x6104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) u32 tx_excessive_collisions; /* 0x6108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) u32 tx_total_collisions; /* 0x610C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) u32 tx_pause_honored_frames; /* 0x6110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) u32 tx_drops; /* 0x6114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u32 tx_jabbers; /* 0x6118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) u32 tx_fcs_errs; /* 0x611C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u32 tx_control_frames; /* 0x6120 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) u32 tx_oversize_frames; /* 0x6124 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) u32 tx_undersize_frames; /* 0x6128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u32 tx_fragments; /* 0x612C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 carry_reg1; /* 0x6130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u32 carry_reg2; /* 0x6134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) u32 carry_reg1_mask; /* 0x6138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 carry_reg2_mask; /* 0x613C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* END OF MAC STAT REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) /* START OF MMC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Main Memory Controller Control reg in mmc address map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) * located at address 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) #define ET_MMC_ENABLE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) #define ET_MMC_ARB_DISABLE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) #define ET_MMC_RXMAC_DISABLE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) #define ET_MMC_TXMAC_DISABLE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) #define ET_MMC_TXDMA_DISABLE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) #define ET_MMC_RXDMA_DISABLE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) #define ET_MMC_FORCE_CE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) /* Main Memory Controller Host Memory Access Address reg in mmc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) * address map. Located at address 0x7004. Top 16 bits hold the address bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) #define ET_SRAM_REQ_ACCESS 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) #define ET_SRAM_WR_ACCESS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) #define ET_SRAM_IS_CTRL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) /* structure for Main Memory Controller Host Memory Access Data reg in mmc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) * address map. Located at address 0x7008 - 0x7014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) * Defined earlier (u32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) /* Memory Control Module of JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) struct mmc_regs { /* Location: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) u32 mmc_ctrl; /* 0x7000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) u32 sram_access; /* 0x7004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) u32 sram_word1; /* 0x7008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) u32 sram_word2; /* 0x700C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) u32 sram_word3; /* 0x7010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) u32 sram_word4; /* 0x7014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* END OF MMC REGISTER ADDRESS MAP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) /* JAGCore Address Mapping
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) struct address_map {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) struct global_regs global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* unused section of global address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) u8 unused_global[4096 - sizeof(struct global_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) struct txdma_regs txdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* unused section of txdma address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) u8 unused_txdma[4096 - sizeof(struct txdma_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct rxdma_regs rxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) /* unused section of rxdma address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) u8 unused_rxdma[4096 - sizeof(struct rxdma_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct txmac_regs txmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) /* unused section of txmac address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u8 unused_txmac[4096 - sizeof(struct txmac_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) struct rxmac_regs rxmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* unused section of rxmac address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) u8 unused_rxmac[4096 - sizeof(struct rxmac_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) struct mac_regs mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* unused section of mac address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) u8 unused_mac[4096 - sizeof(struct mac_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) struct macstat_regs macstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) /* unused section of mac stat address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u8 unused_mac_stat[4096 - sizeof(struct macstat_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) struct mmc_regs mmc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) /* unused section of mmc address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) u8 unused_mmc[4096 - sizeof(struct mmc_regs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* unused section of address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u8 unused_[1015808];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) u8 unused_exp_rom[4096]; /* MGS-size TBD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u8 unused__[524288]; /* unused section of address map */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Defines for generic MII registers 0x00 -> 0x0F can be found in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * include/linux/mii.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* some defines for modem registers that seem to be 'reserved' */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) #define PHY_INDEX_REG 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) #define PHY_DATA_REG 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define PHY_MPHY_CONTROL_REG 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* defines for specified registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define PHY_LOOPBACK_CONTROL 0x13 /* TRU_VMI_LOOPBACK_CONTROL_1_REG 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) /* TRU_VMI_LOOPBACK_CONTROL_2_REG 20 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define PHY_REGISTER_MGMT_CONTROL 0x15 /* TRU_VMI_MI_SEQ_CONTROL_REG 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #define PHY_CONFIG 0x16 /* TRU_VMI_CONFIGURATION_REG 22 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) #define PHY_PHY_CONTROL 0x17 /* TRU_VMI_PHY_CONTROL_REG 23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) #define PHY_INTERRUPT_MASK 0x18 /* TRU_VMI_INTERRUPT_MASK_REG 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) #define PHY_INTERRUPT_STATUS 0x19 /* TRU_VMI_INTERRUPT_STATUS_REG 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) #define PHY_PHY_STATUS 0x1A /* TRU_VMI_PHY_STATUS_REG 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) #define PHY_LED_1 0x1B /* TRU_VMI_LED_CONTROL_1_REG 27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) #define PHY_LED_2 0x1C /* TRU_VMI_LED_CONTROL_2_REG 28 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* TRU_VMI_LINK_CONTROL_REG 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) /* TRU_VMI_TIMING_CONTROL_REG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* MI Register 10: Gigabit basic mode status reg(Reg 0x0A) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) #define ET_1000BT_MSTR_SLV 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* MI Register 16 - 18: Reserved Reg(0x10-0x12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* MI Register 19: Loopback Control Reg(0x13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) * 15: mii_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) * 14: pcs_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * 13: pmd_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * 12: all_digital_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * 11: replica_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * 10: line_driver_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * 9-0: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) /* MI Register 20: Reserved Reg(0x14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) /* MI Register 21: Management Interface Control Reg(0x15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) * 15-11: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) * 10-4: mi_error_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * 3: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * 2: ignore_10g_fr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) * 1: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) * 0: preamble_suppress_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* MI Register 22: PHY Configuration Reg(0x16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) * 15: crs_tx_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) * 14: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) * 13-12: tx_fifo_depth
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) * 11-10: speed_downshift
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) * 9: pbi_detect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) * 8: tbi_rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) * 7: alternate_np
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * 6: group_mdio_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * 5: tx_clock_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * 4: sys_clock_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * 3: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * 2-0: mac_if_mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) #define ET_PHY_CONFIG_TX_FIFO_DEPTH 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) #define ET_PHY_CONFIG_FIFO_DEPTH_8 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) #define ET_PHY_CONFIG_FIFO_DEPTH_16 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) #define ET_PHY_CONFIG_FIFO_DEPTH_32 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) #define ET_PHY_CONFIG_FIFO_DEPTH_64 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) /* MI Register 23: PHY CONTROL Reg(0x17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * 15: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * 14: tdr_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * 13: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * 12-11: downshift_attempts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * 10-6: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) * 5: jabber_10baseT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) * 4: sqe_10baseT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) * 3: tp_loopback_10baseT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * 2: preamble_gen_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * 1: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * 0: force_int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) /* MI Register 24: Interrupt Mask Reg(0x18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) * 15-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) * 9: mdio_sync_lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) * 8: autoneg_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) * 7: hi_bit_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) * 6: np_rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) * 5: err_counter_full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) * 4: fifo_over_underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) * 3: rx_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) * 2: link_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) * 1: automatic_speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) * 0: int_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) /* MI Register 25: Interrupt Status Reg(0x19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) * 15-10: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) * 9: mdio_sync_lost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) * 8: autoneg_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) * 7: hi_bit_err
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) * 6: np_rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) * 5: err_counter_full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) * 4: fifo_over_underflow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * 3: rx_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * 2: link_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) * 1: automatic_speed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) * 0: int_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* MI Register 26: PHY Status Reg(0x1A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * 15: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * 14-13: autoneg_fault
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * 12: autoneg_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) * 11: mdi_x_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) * 10: polarity_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) * 9-8: speed_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * 7: duplex_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * 6: link_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * 5: tx_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) * 4: rx_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * 3: collision_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) * 2: autoneg_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) * 1: pause_en
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) * 0: asymmetric_dir
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) #define ET_PHY_AUTONEG_STATUS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) #define ET_PHY_POLARITY_STATUS 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) #define ET_PHY_SPEED_STATUS 0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) #define ET_PHY_DUPLEX_STATUS 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) #define ET_PHY_LSTATUS 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) #define ET_PHY_AUTONEG_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) /* MI Register 27: LED Control Reg 1(0x1B)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) * 15-14: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) * 13-12: led_dup_indicate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) * 11-10: led_10baseT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) * 9-8: led_collision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) * 7-4: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) * 3-2: pulse_dur
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) * 1: pulse_stretch1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * 0: pulse_stretch0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) /* MI Register 28: LED Control Reg 2(0x1C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * 15-12: led_link
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) * 11-8: led_tx_rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) * 7-4: led_100BaseTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) * 3-0: led_1000BaseT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) #define ET_LED2_LED_LINK 0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) #define ET_LED2_LED_TXRX 0x0F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) #define ET_LED2_LED_100TX 0x00F0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) #define ET_LED2_LED_1000T 0x000F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* defines for LED control reg 2 values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) #define LED_VAL_1000BT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) #define LED_VAL_100BTX 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) #define LED_VAL_10BT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) #define LED_VAL_1000BT_100BTX 0x3 /* 1000BT on, 100BTX blink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) #define LED_VAL_LINKON 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) #define LED_VAL_TX 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) #define LED_VAL_RX 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) #define LED_VAL_TXRX 0x7 /* TX or RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) #define LED_VAL_DUPLEXFULL 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) #define LED_VAL_COLLISION 0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) #define LED_VAL_LINKON_ACTIVE 0xA /* Link on, activity blink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) #define LED_VAL_LINKON_RECV 0xB /* Link on, receive blink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) #define LED_VAL_DUPLEXFULL_COLLISION 0xC /* Duplex on, collision blink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) #define LED_VAL_BLINK 0xD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) #define LED_VAL_ON 0xE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) #define LED_VAL_OFF 0xF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) #define LED_LINK_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) #define LED_TXRX_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) #define LED_100TX_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* MI Register 29 - 31: Reserved Reg(0x1D - 0x1E) */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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