^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* Agere Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * 10/100/1000 Base-T Ethernet Driver for the ET1301 and ET131x series MACs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright © 2005 Agere Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * http://www.agere.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2011 Mark Einon <mark.einon@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *------------------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * SOFTWARE LICENSE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This software is provided subject to the following terms and conditions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * which you should read carefully before using the software. Using this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * software indicates your acceptance of these terms and conditions. If you do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * not agree with these terms and conditions, do not use the software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Copyright © 2005 Agere Systems Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Redistribution and use in source or binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * modifications, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * . Redistributions of source code must retain the above copyright notice, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * list of conditions and the following Disclaimer as comments in the code as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * well as in the documentation and/or other materials provided with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * . Redistributions in binary form must reproduce the above copyright notice,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * this list of conditions and the following Disclaimer in the documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * . Neither the name of Agere Systems Inc. nor the names of the contributors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * may be used to endorse or promote products derived from this software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Disclaimer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * THIS SOFTWARE IS PROVIDED "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * INCLUDING, BUT NOT LIMITED TO, INFRINGEMENT AND THE IMPLIED WARRANTIES OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * USE, MODIFICATION OR DISTRIBUTION OF THIS SOFTWARE IS SOLELY AT THE USERS OWN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * RISK. IN NO EVENT SHALL AGERE SYSTEMS INC. OR CONTRIBUTORS BE LIABLE FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * ON ANY THEORY OF LIABILITY, INCLUDING, BUT NOT LIMITED TO, CONTRACT, STRICT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/ptrace.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/ctype.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/if_arp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include "et131x.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MODULE_AUTHOR("Victor Soriano <vjsoriano@agere.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MODULE_AUTHOR("Mark Einon <mark.einon@gmail.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MODULE_LICENSE("Dual BSD/GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MODULE_DESCRIPTION("10/100/1000 Base-T Ethernet Driver for the ET1310 by Agere Systems");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* EEPROM defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MAX_NUM_REGISTER_POLLS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MAX_NUM_WRITE_RETRIES 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* MAC defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define COUNTER_WRAP_16_BIT 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define COUNTER_WRAP_12_BIT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* PCI defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define INTERNAL_MEM_SIZE 0x400 /* 1024 of internal memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define INTERNAL_MEM_RX_OFFSET 0x1FF /* 50% Tx, 50% Rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* ISR defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* For interrupts, normal running is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * rxdma_xfr_done, phy_interrupt, mac_stat_interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * watchdog_interrupt & txdma_xfer_done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * In both cases, when flow control is enabled for either Tx or bi-direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * we additional enable rx_fbr0_low and rx_fbr1_low, so we know when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * buffer rings are running low.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define INT_MASK_DISABLE 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* NOTE: Masking out MAC_STAT Interrupt for now...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * #define INT_MASK_ENABLE 0xfff6bf17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * #define INT_MASK_ENABLE_NO_FLOW 0xfff6bfd7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define INT_MASK_ENABLE 0xfffebf17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define INT_MASK_ENABLE_NO_FLOW 0xfffebfd7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* General defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Packet and header sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define NIC_MIN_PACKET_SIZE 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Multicast list size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define NIC_MAX_MCAST_LIST 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Supported Filters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ET131X_PACKET_TYPE_DIRECTED 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ET131X_PACKET_TYPE_MULTICAST 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ET131X_PACKET_TYPE_BROADCAST 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ET131X_PACKET_TYPE_PROMISCUOUS 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ET131X_PACKET_TYPE_ALL_MULTICAST 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* Tx Timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ET131X_TX_TIMEOUT (1 * HZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define NIC_SEND_HANG_THRESHOLD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* MP_ADAPTER flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define FMP_ADAPTER_INTERRUPT_IN_USE 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* MP_SHARED flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define FMP_ADAPTER_LOWER_POWER 0x00200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FMP_ADAPTER_NON_RECOVER_ERROR 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define FMP_ADAPTER_HARDWARE_ERROR 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FMP_ADAPTER_FAIL_SEND_MASK 0x3ff00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Some offsets in PCI config space that are actually used. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ET1310_PCI_MAC_ADDRESS 0xA4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ET1310_PCI_EEPROM_STATUS 0xB2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ET1310_PCI_ACK_NACK 0xC0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ET1310_PCI_REPLAY 0xC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ET1310_PCI_L0L1LATENCY 0xCF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* PCI Product IDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ET131X_PCI_DEVICE_ID_GIG 0xED00 /* ET1310 1000 Base-T 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ET131X_PCI_DEVICE_ID_FAST 0xED01 /* ET1310 100 Base-T */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Define order of magnitude converter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define NANO_IN_A_MICRO 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define PARM_RX_NUM_BUFS_DEF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define PARM_RX_TIME_INT_DEF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PARM_RX_MEM_END_DEF 0x2bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PARM_TX_TIME_INT_DEF 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define PARM_TX_NUM_BUFS_DEF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define PARM_DMA_CACHE_DEF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* RX defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define FBR_CHUNKS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MAX_DESC_PER_RING_RX 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* number of RFDs - default and min */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define RFD_LOW_WATER_MARK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define NIC_DEFAULT_NUM_RFD 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define NUM_FBRS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MAX_PACKETS_HANDLED 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define ET131X_MIN_MTU 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ET131X_MAX_MTU 9216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ALCATEL_MULTICAST_PKT 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ALCATEL_BROADCAST_PKT 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* typedefs for Free Buffer Descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct fbr_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u32 addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 word2; /* Bits 10-31 reserved, 0-9 descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Packet Status Ring Descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * Word 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * top 16 bits are from the Alcatel Status Word as enumerated in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * PE-MCXMAC Data Sheet IPD DS54 0210-1 (also IPD-DS80 0205-2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * 0: hp hash pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * 1: ipa IP checksum assist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * 2: ipp IP checksum pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * 3: tcpa TCP checksum assist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * 4: tcpp TCP checksum pass
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * 5: wol WOL Event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * 6: rxmac_error RXMAC Error Indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * 7: drop Drop packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * 8: ft Frame Truncated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * 9: jp Jumbo Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * 10: vp VLAN Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * 11-15: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * 16: asw_prev_pkt_dropped e.g. IFG too small on previous
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * 17: asw_RX_DV_event short receive event detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * 18: asw_false_carrier_event bad carrier since last good packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * 19: asw_code_err one or more nibbles signalled as errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * 20: asw_CRC_err CRC error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * 21: asw_len_chk_err frame length field incorrect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * 22: asw_too_long frame length > 1518 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * 23: asw_OK valid CRC + no code error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * 24: asw_multicast has a multicast address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * 25: asw_broadcast has a broadcast address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * 26: asw_dribble_nibble spurious bits after EOP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * 27: asw_control_frame is a control frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * 28: asw_pause_frame is a pause frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * 29: asw_unsupported_op unsupported OP code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * 30: asw_VLAN_tag VLAN tag detected
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * 31: asw_long_evt Rx long event
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * Word 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * 0-15: length length in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * 16-25: bi Buffer Index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * 26-27: ri Ring Index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * 28-31: reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) struct pkt_stat_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* Typedefs for the RX DMA status word */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* rx status word 0 holds part of the status bits of the Rx DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * that get copied out to memory by the ET-1310. Word 0 is a 32 bit word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * which contains the Free Buffer ring 0 and 1 available offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * bit 0-9 FBR1 offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * bit 10 Wrap flag for FBR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * bit 16-25 FBR0 offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * bit 26 Wrap flag for FBR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* RXSTAT_WORD1_t structure holds part of the status bits of the Rx DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * that get copied out to memory by the ET-1310. Word 3 is a 32 bit word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * which contains the Packet Status Ring available offset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * bit 0-15 reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * bit 16-27 PSRoffset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * bit 28 PSRwrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * bit 29-31 unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* struct rx_status_block is a structure representing the status of the Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * DMA engine it sits in free memory, and is pointed to by 0x101c / 0x1020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct rx_status_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* Structure for look-up table holding free buffer ring pointers, addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * and state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct fbr_lookup {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) void *virt[MAX_DESC_PER_RING_RX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 bus_high[MAX_DESC_PER_RING_RX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 bus_low[MAX_DESC_PER_RING_RX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) void *ring_virtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) dma_addr_t ring_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) void *mem_virtaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) dma_addr_t mem_physaddrs[MAX_DESC_PER_RING_RX / FBR_CHUNKS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 local_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dma_addr_t buffsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* struct rx_ring is the structure representing the adaptor's local
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * reference(s) to the rings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct rx_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct fbr_lookup *fbr[NUM_FBRS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) void *ps_ring_virtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) dma_addr_t ps_ring_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 local_psr_full;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 psr_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) struct rx_status_block *rx_status_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dma_addr_t rx_status_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct list_head recv_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 num_ready_recv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) u32 num_rfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) bool unfinished_receives;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* TX defines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* word 2 of the control bits in the Tx Descriptor ring for the ET-1310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * 0-15: length of packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * 16-27: VLAN tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * 28: VLAN CFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * 29-31: VLAN priority
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * word 3 of the control bits in the Tx Descriptor ring for the ET-1310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * 0: last packet in the sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) * 1: first packet in the sequence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * 2: interrupt the processor when this pkt sent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * 3: Control word - no packet data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * 4: Issue half-duplex backpressure : XON/XOFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * 5: send pause frame
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * 6: Tx frame has error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * 7: append CRC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * 8: MAC override
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * 9: pad packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * 10: Packet is a Huge packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * 11: append VLAN tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * 12: IP checksum assist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * 13: TCP checksum assist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * 14: UDP checksum assist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TXDESC_FLAG_LASTPKT 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TXDESC_FLAG_FIRSTPKT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TXDESC_FLAG_INTPROC 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* struct tx_desc represents each descriptor on the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 addr_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u32 len_vlan; /* control words how to xmit the */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) u32 flags; /* data (detailed above) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* The status of the Tx DMA engine it sits in free memory, and is pointed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * by 0x101c / 0x1020. This is a DMA10 type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) /* TCB (Transmit Control Block: Host Side) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct tcb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct tcb *next; /* Next entry in ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 count; /* Used to spot stuck/lost packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) u32 stale; /* Used to spot stuck/lost packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct sk_buff *skb; /* Network skb we are tied to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 index; /* Ring indexes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) u32 index_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Structure representing our local reference(s) to the ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) struct tx_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* TCB (Transmit Control Block) memory and lists */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct tcb *tcb_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* List of TCBs that are ready to be used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct tcb *tcb_qhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct tcb *tcb_qtail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* list of TCBs that are currently being sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct tcb *send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct tcb *send_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) int used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* The actual descriptor ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct tx_desc *tx_desc_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dma_addr_t tx_desc_ring_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* send_idx indicates where we last wrote to in the descriptor ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) u32 send_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* The location of the write-back status block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 *tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dma_addr_t tx_status_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* Packets since the last IRQ: used for interrupt coalescing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int since_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /* Do not change these values: if changed, then change also in respective
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * TXdma and Rxdma engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define NUM_DESC_PER_RING_TX 512 /* TX Do not change these values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define NUM_TCB 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* These values are all superseded by registry entries to facilitate tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * Once the desired performance has been achieved, the optimal registry values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) * should be re-populated to these #defines:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TX_ERROR_PERIOD 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define LO_MARK_PERCENT_FOR_PSR 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define LO_MARK_PERCENT_FOR_RX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* RFD (Receive Frame Descriptor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct rfd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct list_head list_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) u32 len; /* total size of receive frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) u16 bufferindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) u8 ringindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Flow Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define FLOW_BOTH 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define FLOW_TXONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define FLOW_RXONLY 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define FLOW_NONE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* Struct to define some device statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) struct ce_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 multicast_pkts_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 rcvd_pkts_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) u32 tx_underflows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u32 tx_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u32 tx_excessive_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) u32 tx_first_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) u32 tx_late_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) u32 tx_max_pkt_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) u32 tx_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u32 rx_overflows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) u32 rx_length_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 rx_align_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 rx_crc_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 rx_code_violations;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) u32 rx_other_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* The private adapter structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct et131x_adapter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct mii_bus *mii_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* Flags that indicate current state of the adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* local link state, to determine if a state change has occurred */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) u8 rom_addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) u8 addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) bool has_eeprom;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) u8 eeprom_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) spinlock_t tcb_send_qlock; /* protects the tx_ring send tcb list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spinlock_t tcb_ready_qlock; /* protects the tx_ring ready tcb list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) spinlock_t rcv_lock; /* protects the rx_ring receive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Packet Filter and look ahead size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) u32 packet_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* multicast list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u32 multicast_addr_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) u8 multicast_list[NIC_MAX_MCAST_LIST][ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* Pointer to the device's PCI register space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct address_map __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Registry parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) u8 wanted_flow; /* Flow we want for 802.3x flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 registry_jumbo_packet; /* Max supported ethernet packet size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* Derived from the registry: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) u8 flow; /* flow control validated by the far-end */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Minimize init-time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) struct timer_list error_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* variable putting the phy into coma mode when boot up with no cable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) * plugged in after 5 seconds
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) u8 boot_coma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* Tx Memory Variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct tx_ring tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Rx Memory Variables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct rx_ring rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct ce_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int eeprom_wait_ready(struct pci_dev *pdev, u32 *status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) /* 1. Check LBCIF Status Register for bits 6 & 3:2 all equal to 0 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) * bits 7,1:0 both equal to 1, at least once after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) * Subsequent operations need only to check that bits 1:0 are equal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * to 1 prior to starting a single byte read/write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) for (i = 0; i < MAX_NUM_REGISTER_POLLS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (pci_read_config_dword(pdev, LBCIF_DWORD1_GROUP, ®))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /* I2C idle and Phy Queue Avail both true */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) if ((reg & 0x3000) == 0x3000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) *status = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return reg & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) static int eeprom_write(struct et131x_adapter *adapter, u32 addr, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) struct pci_dev *pdev = adapter->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) int retries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int writeok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /* For an EEPROM, an I2C single byte write is defined as a START
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * condition followed by the device address, EEPROM address, one byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * of data and a STOP condition. The STOP condition will trigger the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * EEPROM's internally timed write cycle to the nonvolatile memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) * All inputs are disabled during this write cycle and the EEPROM will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) * not respond to any access until the internal write is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) err = eeprom_wait_ready(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* 2. Write to the LBCIF Control Register: bit 7=1, bit 6=1, bit 3=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) * and bits 1:0 both =0. Bit 5 should be set according to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) * type of EEPROM being accessed (1=two byte addressing, 0=one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) * byte addressing).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) LBCIF_CONTROL_LBCIF_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) LBCIF_CONTROL_I2C_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* Prepare EEPROM address for Step 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) for (retries = 0; retries < MAX_NUM_WRITE_RETRIES; retries++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Write the data to the LBCIF Data Register (the I2C write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * will begin).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (pci_write_config_byte(pdev, LBCIF_DATA_REGISTER, data))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /* Monitor bit 1:0 of the LBCIF Status Register. When bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * 1:0 are both equal to 1, the I2C write has completed and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * internal write cycle of the EEPROM is about to start.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * (bits 1:0 = 01 is a legal state while waiting from both
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) * equal to 1, but bits 1:0 = 10 is invalid and implies that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) * something is broken).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) err = eeprom_wait_ready(pdev, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /* Check bit 3 of the LBCIF Status Register. If equal to 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * an error has occurred.Don't break here if we are revision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * 1, this is so we do a blind write for load bug.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if ((status & LBCIF_STATUS_GENERAL_ERROR) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) adapter->pdev->revision == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) /* Check bit 2 of the LBCIF Status Register. If equal to 1 an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) * ACK error has occurred on the address phase of the write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * This could be due to an actual hardware failure or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * EEPROM may still be in its internal write cycle from a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * previous write. This write operation was ignored and must be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) *repeated later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (status & LBCIF_STATUS_ACK_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* This could be due to an actual hardware failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) * or the EEPROM may still be in its internal write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) * cycle from a previous write. This write operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) * was ignored and must be repeated later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) writeok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) while (1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) LBCIF_CONTROL_LBCIF_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) writeok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* Do read until internal ACK_ERROR goes away meaning write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) * completed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pci_write_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) LBCIF_ADDRESS_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) pci_read_config_dword(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) LBCIF_DATA_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) } while ((val & 0x00010000) == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) } while (val & 0x00040000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if ((val & 0xFF00) != 0xC000 || index == 10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) index++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) return writeok ? 0 : -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int eeprom_read(struct et131x_adapter *adapter, u32 addr, u8 *pdata)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct pci_dev *pdev = adapter->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /* A single byte read is similar to the single byte write, with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * exception of the data flow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) err = eeprom_wait_ready(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Write to the LBCIF Control Register: bit 7=1, bit 6=0, bit 3=0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) * and bits 1:0 both =0. Bit 5 should be set according to the type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) * of EEPROM being accessed (1=two byte addressing, 0=one byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) * addressing).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) if (pci_write_config_byte(pdev, LBCIF_CONTROL_REGISTER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) LBCIF_CONTROL_LBCIF_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /* Write the address to the LBCIF Address Register (I2C read will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) * begin).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (pci_write_config_dword(pdev, LBCIF_ADDRESS_REGISTER, addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Monitor bit 0 of the LBCIF Status Register. When = 1, I2C read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) * is complete. (if bit 1 =1 and bit 0 stays = 0, a hardware failure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) * has occurred).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) err = eeprom_wait_ready(pdev, &status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* Regardless of error status, read data byte from LBCIF Data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * Register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) *pdata = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) return (status & LBCIF_STATUS_ACK_ERROR) ? -EIO : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static int et131x_init_eeprom(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct pci_dev *pdev = adapter->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) u8 eestatus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) /* THIS IS A WORKAROUND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * I need to call this function twice to get my card in a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) * LG M1 Express Dual running. I tried also a msleep before this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) * function, because I thought there could be some time conditions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) * but it didn't work. Call the whole function twice also work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (pci_read_config_byte(pdev, ET1310_PCI_EEPROM_STATUS, &eestatus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "Could not read PCI config space for EEPROM Status\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) /* Determine if the error(s) we care about are present. If they are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) * present we need to fail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) if (eestatus & 0x4C) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int write_failed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (pdev->revision == 0x01) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static const u8 eedata[4] = { 0xFE, 0x13, 0x10, 0xFF };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* Re-write the first 4 bytes if we have an eeprom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) * present and the revision id is 1, this fixes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) * corruption seen with 1310 B Silicon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (eeprom_write(adapter, i, eedata[i]) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) write_failed = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) if (pdev->revision != 0x01 || write_failed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "Fatal EEPROM Status Error - 0x%04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) eestatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /* This error could mean that there was an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * reading the eeprom or that the eeprom doesn't exist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * We will treat each case the same and not try to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * gather additional information that normally would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * come from the eeprom, like MAC Address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) adapter->has_eeprom = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) adapter->has_eeprom = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Read the EEPROM for information regarding LED behavior. Refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * et131x_xcvr_init() for its use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) eeprom_read(adapter, 0x70, &adapter->eeprom_data[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) eeprom_read(adapter, 0x71, &adapter->eeprom_data[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (adapter->eeprom_data[0] != 0xcd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) /* Disable all optional features */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) adapter->eeprom_data[1] = 0x00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static void et131x_rx_dma_enable(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* Setup the receive dma configuration register for normal operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) u32 csr = ET_RXDMA_CSR_FBR1_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct rx_ring *rx_ring = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (rx_ring->fbr[1]->buffsize == 4096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) csr |= ET_RXDMA_CSR_FBR1_SIZE_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) else if (rx_ring->fbr[1]->buffsize == 8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) csr |= ET_RXDMA_CSR_FBR1_SIZE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) else if (rx_ring->fbr[1]->buffsize == 16384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) csr |= ET_RXDMA_CSR_FBR1_SIZE_LO | ET_RXDMA_CSR_FBR1_SIZE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) csr |= ET_RXDMA_CSR_FBR0_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (rx_ring->fbr[0]->buffsize == 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) csr |= ET_RXDMA_CSR_FBR0_SIZE_LO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) else if (rx_ring->fbr[0]->buffsize == 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) csr |= ET_RXDMA_CSR_FBR0_SIZE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) else if (rx_ring->fbr[0]->buffsize == 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) csr |= ET_RXDMA_CSR_FBR0_SIZE_LO | ET_RXDMA_CSR_FBR0_SIZE_HI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) writel(csr, &adapter->regs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) csr = readl(&adapter->regs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (csr & ET_RXDMA_CSR_HALT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) csr = readl(&adapter->regs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (csr & ET_RXDMA_CSR_HALT_STATUS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "RX Dma failed to exit halt state. CSR 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static void et131x_rx_dma_disable(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 csr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Setup the receive dma configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) writel(ET_RXDMA_CSR_HALT | ET_RXDMA_CSR_FBR1_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) &adapter->regs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) csr = readl(&adapter->regs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (!(csr & ET_RXDMA_CSR_HALT_STATUS)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) udelay(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) csr = readl(&adapter->regs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!(csr & ET_RXDMA_CSR_HALT_STATUS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "RX Dma failed to enter halt state. CSR 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static void et131x_tx_dma_enable(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /* Setup the transmit dma configuration register for normal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) writel(ET_TXDMA_SNGL_EPKT | (PARM_DMA_CACHE_DEF << ET_TXDMA_CACHE_SHIFT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) &adapter->regs->txdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static inline void add_10bit(u32 *v, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) *v = INDEX10(*v + n) | (*v & ET_DMA10_WRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static inline void add_12bit(u32 *v, int n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) *v = INDEX12(*v + n) | (*v & ET_DMA12_WRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) static void et1310_config_mac_regs1(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) struct mac_regs __iomem *macregs = &adapter->regs->mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) u32 station1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) u32 station2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) u32 ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /* First we need to reset everything. Write to MAC configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * register 1 to perform reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) writel(ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) ¯egs->cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) /* Next lets configure the MAC Inter-packet gap register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) ipg = 0x38005860; /* IPG1 0x38 IPG2 0x58 B2B 0x60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) ipg |= 0x50 << 8; /* ifg enforce 0x50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) writel(ipg, ¯egs->ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) /* Next lets configure the MAC Half Duplex register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /* BEB trunc 0xA, Ex Defer, Rexmit 0xF Coll 0x37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) writel(0x00A1F037, ¯egs->hfdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Next lets configure the MAC Interface Control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) writel(0, ¯egs->if_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) writel(ET_MAC_MIIMGMT_CLK_RST, ¯egs->mii_mgmt_cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Next lets configure the MAC Station Address register. These
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) * values are read from the EEPROM during initialization and stored
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) * in the adapter structure. We write what is stored in the adapter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * structure to the MAC Station Address registers high and low. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * station address is used for generating and checking pause control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) station2 = (adapter->addr[1] << ET_MAC_STATION_ADDR2_OC2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) (adapter->addr[0] << ET_MAC_STATION_ADDR2_OC1_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) station1 = (adapter->addr[5] << ET_MAC_STATION_ADDR1_OC6_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (adapter->addr[4] << ET_MAC_STATION_ADDR1_OC5_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (adapter->addr[3] << ET_MAC_STATION_ADDR1_OC4_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) adapter->addr[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) writel(station1, ¯egs->station_addr_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) writel(station2, ¯egs->station_addr_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) /* Max ethernet packet in bytes that will be passed by the mac without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) * being truncated. Allow the MAC to pass 4 more than our max packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) * size. This is 4 for the Ethernet CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Packets larger than (registry_jumbo_packet) that do not contain a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * VLAN ID will be dropped by the Rx function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) writel(adapter->registry_jumbo_packet + 4, ¯egs->max_fm_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /* clear out MAC config reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) writel(0, ¯egs->cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static void et1310_config_mac_regs2(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) int32_t delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct mac_regs __iomem *mac = &adapter->regs->mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) u32 cfg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) u32 cfg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) u32 ifctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) u32 ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) ctl = readl(&adapter->regs->txmac.ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) cfg1 = readl(&mac->cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) cfg2 = readl(&mac->cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) ifctrl = readl(&mac->if_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) /* Set up the if mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) cfg2 &= ~ET_MAC_CFG2_IFMODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (phydev->speed == SPEED_1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) cfg2 |= ET_MAC_CFG2_IFMODE_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ifctrl &= ~ET_MAC_IFCTRL_PHYMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) cfg2 |= ET_MAC_CFG2_IFMODE_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ifctrl |= ET_MAC_IFCTRL_PHYMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) cfg1 |= ET_MAC_CFG1_RX_ENABLE | ET_MAC_CFG1_TX_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) ET_MAC_CFG1_TX_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) cfg1 &= ~(ET_MAC_CFG1_LOOPBACK | ET_MAC_CFG1_RX_FLOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (adapter->flow == FLOW_RXONLY || adapter->flow == FLOW_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) cfg1 |= ET_MAC_CFG1_RX_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) writel(cfg1, &mac->cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* Now we need to initialize the MAC Configuration 2 register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* preamble 7, check length, huge frame off, pad crc, crc enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) * full duplex off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) cfg2 |= 0x7 << ET_MAC_CFG2_PREAMBLE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) cfg2 |= ET_MAC_CFG2_IFMODE_LEN_CHECK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) cfg2 |= ET_MAC_CFG2_IFMODE_PAD_CRC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) cfg2 |= ET_MAC_CFG2_IFMODE_CRC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) cfg2 &= ~ET_MAC_CFG2_IFMODE_HUGE_FRAME;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) cfg2 &= ~ET_MAC_CFG2_IFMODE_FULL_DPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (phydev->duplex == DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) cfg2 |= ET_MAC_CFG2_IFMODE_FULL_DPLX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) ifctrl &= ~ET_MAC_IFCTRL_GHDMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (phydev->duplex == DUPLEX_HALF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ifctrl |= ET_MAC_IFCTRL_GHDMODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) writel(ifctrl, &mac->if_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) writel(cfg2, &mac->cfg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) delay++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) cfg1 = readl(&mac->cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } while ((cfg1 & ET_MAC_CFG1_WAIT) != ET_MAC_CFG1_WAIT && delay < 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (delay == 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) "Syncd bits did not respond correctly cfg1 word 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) ctl |= ET_TX_CTRL_TXMAC_ENABLE | ET_TX_CTRL_FC_DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) writel(ctl, &adapter->regs->txmac.ctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (adapter->flags & FMP_ADAPTER_LOWER_POWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) et131x_rx_dma_enable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) et131x_tx_dma_enable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int et1310_in_phy_coma(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) u32 pmcsr = readl(&adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) return ET_PM_PHY_SW_COMA & pmcsr ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) static void et1310_setup_device_for_multicast(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) u32 hash1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) u32 hash2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) u32 hash3 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) u32 hash4 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* If ET131X_PACKET_TYPE_MULTICAST is specified, then we provision
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) * the multi-cast LIST. If it is NOT specified, (and "ALL" is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) * specified) then we should pass NO multi-cast addresses to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) * driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) if (adapter->packet_filter & ET131X_PACKET_TYPE_MULTICAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Loop through our multicast array and set up the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) for (i = 0; i < adapter->multicast_addr_count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u32 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) result = ether_crc(6, adapter->multicast_list[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) result = (result & 0x3F800000) >> 23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) if (result < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) hash1 |= (1 << result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) } else if ((31 < result) && (result < 64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) result -= 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) hash2 |= (1 << result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) } else if ((63 < result) && (result < 96)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) result -= 64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) hash3 |= (1 << result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) result -= 96;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) hash4 |= (1 << result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Write out the new hash to the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (!et1310_in_phy_coma(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) writel(hash1, &rxmac->multi_hash1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) writel(hash2, &rxmac->multi_hash2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) writel(hash3, &rxmac->multi_hash3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) writel(hash4, &rxmac->multi_hash4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) static void et1310_setup_device_for_unicast(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) u32 uni_pf1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) u32 uni_pf2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) u32 uni_pf3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) /* Set up unicast packet filter reg 3 to be the first two octets of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) * the MAC address for both address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) * Set up unicast packet filter reg 2 to be the octets 2 - 5 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) * MAC address for second address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) * Set up unicast packet filter reg 3 to be the octets 2 - 5 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) * MAC address for first address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) uni_pf3 = (adapter->addr[0] << ET_RX_UNI_PF_ADDR2_1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) (adapter->addr[1] << ET_RX_UNI_PF_ADDR2_2_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) (adapter->addr[0] << ET_RX_UNI_PF_ADDR1_1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) adapter->addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) uni_pf2 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR2_3_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) (adapter->addr[3] << ET_RX_UNI_PF_ADDR2_4_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) (adapter->addr[4] << ET_RX_UNI_PF_ADDR2_5_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) adapter->addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) uni_pf1 = (adapter->addr[2] << ET_RX_UNI_PF_ADDR1_3_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) (adapter->addr[3] << ET_RX_UNI_PF_ADDR1_4_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) (adapter->addr[4] << ET_RX_UNI_PF_ADDR1_5_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) adapter->addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!et1310_in_phy_coma(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) writel(uni_pf1, &rxmac->uni_pf_addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) writel(uni_pf2, &rxmac->uni_pf_addr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) writel(uni_pf3, &rxmac->uni_pf_addr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static void et1310_config_rxmac_regs(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct rxmac_regs __iomem *rxmac = &adapter->regs->rxmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u32 sa_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) u32 sa_hi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) u32 pf_ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) u32 __iomem *wolw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) /* Disable the MAC while it is being configured (also disable WOL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) writel(0x8, &rxmac->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) /* Initialize WOL to disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) writel(0, &rxmac->crc0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) writel(0, &rxmac->crc12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) writel(0, &rxmac->crc34);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) /* We need to set the WOL mask0 - mask4 next. We initialize it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) * its default Values of 0x00000000 because there are not WOL masks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) * as of this time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) for (wolw = &rxmac->mask0_word0; wolw <= &rxmac->mask4_word3; wolw++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) writel(0, wolw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* Lets setup the WOL Source Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) sa_lo = (adapter->addr[2] << ET_RX_WOL_LO_SA3_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) (adapter->addr[3] << ET_RX_WOL_LO_SA4_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) (adapter->addr[4] << ET_RX_WOL_LO_SA5_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) adapter->addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) writel(sa_lo, &rxmac->sa_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) sa_hi = (u32)(adapter->addr[0] << ET_RX_WOL_HI_SA1_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) adapter->addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) writel(sa_hi, &rxmac->sa_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) /* Disable all Packet Filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) writel(0, &rxmac->pf_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /* Let's initialize the Unicast Packet filtering address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) if (adapter->packet_filter & ET131X_PACKET_TYPE_DIRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) et1310_setup_device_for_unicast(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) pf_ctrl |= ET_RX_PFCTRL_UNICST_FILTER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) writel(0, &rxmac->uni_pf_addr1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) writel(0, &rxmac->uni_pf_addr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) writel(0, &rxmac->uni_pf_addr3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* Let's initialize the Multicast hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) if (!(adapter->packet_filter & ET131X_PACKET_TYPE_ALL_MULTICAST)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) pf_ctrl |= ET_RX_PFCTRL_MLTCST_FILTER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) et1310_setup_device_for_multicast(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /* Runt packet filtering. Didn't work in version A silicon. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) pf_ctrl |= (NIC_MIN_PACKET_SIZE + 4) << ET_RX_PFCTRL_MIN_PKT_SZ_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pf_ctrl |= ET_RX_PFCTRL_FRAG_FILTER_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (adapter->registry_jumbo_packet > 8192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) /* In order to transmit jumbo packets greater than 8k, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) * FIFO between RxMAC and RxDMA needs to be reduced in size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * to (16k - Jumbo packet size). In order to implement this,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * we must use "cut through" mode in the RxMAC, which chops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) * packets down into segments which are (max_size * 16). In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) * this case we selected 256 bytes, since this is the size of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) * the PCI-Express TLP's that the 1310 uses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) * seg_en on, fc_en off, size 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) writel(0x41, &rxmac->mcif_ctrl_max_seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) writel(0, &rxmac->mcif_ctrl_max_seg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) writel(0, &rxmac->mcif_water_mark);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) writel(0, &rxmac->mif_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) writel(0, &rxmac->space_avail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* Initialize the the mif_ctrl register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) * bit 3: Receive code error. One or more nibbles were signaled as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * errors during the reception of the packet. Clear this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) * bit in Gigabit, set it in 100Mbit. This was derived
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) * experimentally at UNH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) * bit 4: Receive CRC error. The packet's CRC did not match the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * internally generated CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * bit 5: Receive length check error. Indicates that frame length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * field value in the packet does not match the actual data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * byte length and is not a type field.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * bit 16: Receive frame truncated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * bit 17: Drop packet enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (phydev && phydev->speed == SPEED_100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) writel(0x30038, &rxmac->mif_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) writel(0x30030, &rxmac->mif_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* Finally we initialize RxMac to be enabled & WOL disabled. Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * filter is always enabled since it is where the runt packets are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) * supposed to be dropped. For version A silicon, runt packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) * dropping doesn't work, so it is disabled in the pf_ctrl register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * but we still leave the packet filter on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) writel(pf_ctrl, &rxmac->pf_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) writel(ET_RX_CTRL_RXMAC_ENABLE | ET_RX_CTRL_WOL_DISABLE, &rxmac->ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static void et1310_config_txmac_regs(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) struct txmac_regs __iomem *txmac = &adapter->regs->txmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) /* We need to update the Control Frame Parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) * cfpt - control frame pause timer set to 64 (0x40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) * cfep - control frame extended pause timer set to 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (adapter->flow == FLOW_NONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) writel(0, &txmac->cf_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) writel(0x40, &txmac->cf_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) static void et1310_config_macstat_regs(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) struct macstat_regs __iomem *macstat = &adapter->regs->macstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) u32 __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) /* initialize all the macstat registers to zero on the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) for (reg = &macstat->txrx_0_64_byte_frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) reg <= &macstat->carry_reg2; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) writel(0, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) /* Unmask any counters that we want to track the overflow of.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) * Initially this will be all counters. It may become clear later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) * that we do not need to track all counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) writel(0xFFFFBE32, &macstat->carry_reg1_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) writel(0xFFFE7E8B, &macstat->carry_reg2_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) static int et131x_phy_mii_read(struct et131x_adapter *adapter, u8 addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) u8 reg, u16 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) struct mac_regs __iomem *mac = &adapter->regs->mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) u32 delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) u32 mii_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) u32 mii_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) u32 mii_indicator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) /* Save a local copy of the registers we are dealing with so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) * set them back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) mii_addr = readl(&mac->mii_mgmt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) mii_cmd = readl(&mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) /* Stop the current operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) writel(0, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) /* Set up the register we need to read from on the correct PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) writel(0x1, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) delay++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) mii_indicator = readl(&mac->mii_mgmt_indicator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) } while ((mii_indicator & ET_MAC_MGMT_WAIT) && delay < 50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* If we hit the max delay, we could not read the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) if (delay == 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) "reg 0x%08x could not be read\n", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mii_indicator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) /* If we hit here we were able to read the register and we need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) * return the value to the caller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) *value = readl(&mac->mii_mgmt_stat) & ET_MAC_MIIMGMT_STAT_PHYCRTL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* Stop the read operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) writel(0, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) /* set the registers we touched back to the state at which we entered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) writel(mii_addr, &mac->mii_mgmt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) writel(mii_cmd, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) static int et131x_mii_read(struct et131x_adapter *adapter, u8 reg, u16 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (!phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) return et131x_phy_mii_read(adapter, phydev->mdio.addr, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) static int et131x_mii_write(struct et131x_adapter *adapter, u8 addr, u8 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) struct mac_regs __iomem *mac = &adapter->regs->mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) int status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) u32 delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) u32 mii_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) u32 mii_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) u32 mii_indicator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) /* Save a local copy of the registers we are dealing with so we can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) * set them back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) mii_addr = readl(&mac->mii_mgmt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) mii_cmd = readl(&mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) /* Stop the current operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) writel(0, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) /* Set up the register we need to write to on the correct PHY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) writel(ET_MAC_MII_ADDR(addr, reg), &mac->mii_mgmt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) /* Add the value to write to the registers to the mac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) writel(value, &mac->mii_mgmt_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) udelay(50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) delay++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) mii_indicator = readl(&mac->mii_mgmt_indicator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) } while ((mii_indicator & ET_MAC_MGMT_BUSY) && delay < 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) /* If we hit the max delay, we could not write the register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (delay == 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) "reg 0x%08x could not be written", reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev_warn(&adapter->pdev->dev, "status is 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) mii_indicator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) dev_warn(&adapter->pdev->dev, "command is 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) readl(&mac->mii_mgmt_cmd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) et131x_mii_read(adapter, reg, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) status = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) /* Stop the write operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) writel(0, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* set the registers we touched back to the state at which we entered
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) * this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) writel(mii_addr, &mac->mii_mgmt_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) writel(mii_cmd, &mac->mii_mgmt_cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static void et1310_phy_read_mii_bit(struct et131x_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) u16 regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) u16 bitnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) u8 *value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) u16 mask = 1 << bitnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) et131x_mii_read(adapter, regnum, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) *value = (reg & mask) >> bitnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) static void et1310_config_flow_control(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (phydev->duplex == DUPLEX_HALF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) adapter->flow = FLOW_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) char remote_pause, remote_async_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) et1310_phy_read_mii_bit(adapter, 5, 10, &remote_pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) et1310_phy_read_mii_bit(adapter, 5, 11, &remote_async_pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) if (remote_pause && remote_async_pause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) adapter->flow = adapter->wanted_flow;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) } else if (remote_pause && !remote_async_pause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (adapter->wanted_flow == FLOW_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) adapter->flow = FLOW_BOTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) adapter->flow = FLOW_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) } else if (!remote_pause && !remote_async_pause) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) adapter->flow = FLOW_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) if (adapter->wanted_flow == FLOW_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) adapter->flow = FLOW_RXONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) adapter->flow = FLOW_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* et1310_update_macstat_host_counters - Update local copy of the statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) static void et1310_update_macstat_host_counters(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) struct ce_stats *stats = &adapter->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) struct macstat_regs __iomem *macstat =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) &adapter->regs->macstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) stats->tx_collisions += readl(&macstat->tx_total_collisions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) stats->tx_first_collisions += readl(&macstat->tx_single_collisions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) stats->tx_deferred += readl(&macstat->tx_deferred);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) stats->tx_excessive_collisions +=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) readl(&macstat->tx_multiple_collisions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) stats->tx_late_collisions += readl(&macstat->tx_late_collisions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) stats->tx_underflows += readl(&macstat->tx_undersize_frames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) stats->tx_max_pkt_errs += readl(&macstat->tx_oversize_frames);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) stats->rx_align_errs += readl(&macstat->rx_align_errs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) stats->rx_crc_errs += readl(&macstat->rx_code_errs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) stats->rcvd_pkts_dropped += readl(&macstat->rx_drops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) stats->rx_overflows += readl(&macstat->rx_oversize_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) stats->rx_code_violations += readl(&macstat->rx_fcs_errs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) stats->rx_length_errs += readl(&macstat->rx_frame_len_errs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) stats->rx_other_errs += readl(&macstat->rx_fragment_packets);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) /* et1310_handle_macstat_interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * One of the MACSTAT counters has wrapped. Update the local copy of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) * the statistics held in the adapter structure, checking the "wrap"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) * bit for each counter.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static void et1310_handle_macstat_interrupt(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) u32 carry_reg1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) u32 carry_reg2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) /* Read the interrupt bits from the register(s). These are Clear On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) * Write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) carry_reg1 = readl(&adapter->regs->macstat.carry_reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) carry_reg2 = readl(&adapter->regs->macstat.carry_reg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) writel(carry_reg1, &adapter->regs->macstat.carry_reg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) writel(carry_reg2, &adapter->regs->macstat.carry_reg2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) /* We need to do update the host copy of all the MAC_STAT counters.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) * For each counter, check it's overflow bit. If the overflow bit is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) * set, then increment the host version of the count by one complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * revolution of the counter. This routine is called when the counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * block indicates that one of the counters has wrapped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (carry_reg1 & (1 << 14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) adapter->stats.rx_code_violations += COUNTER_WRAP_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (carry_reg1 & (1 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) adapter->stats.rx_align_errs += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) if (carry_reg1 & (1 << 7))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) adapter->stats.rx_length_errs += COUNTER_WRAP_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (carry_reg1 & (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) adapter->stats.rx_other_errs += COUNTER_WRAP_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (carry_reg1 & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) adapter->stats.rx_crc_errs += COUNTER_WRAP_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (carry_reg1 & (1 << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) adapter->stats.rx_overflows += COUNTER_WRAP_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) if (carry_reg1 & (1 << 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) adapter->stats.rcvd_pkts_dropped += COUNTER_WRAP_16_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) if (carry_reg2 & (1 << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) adapter->stats.tx_max_pkt_errs += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) if (carry_reg2 & (1 << 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) adapter->stats.tx_underflows += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (carry_reg2 & (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) adapter->stats.tx_first_collisions += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) if (carry_reg2 & (1 << 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) adapter->stats.tx_deferred += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) if (carry_reg2 & (1 << 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) adapter->stats.tx_excessive_collisions += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (carry_reg2 & (1 << 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) adapter->stats.tx_late_collisions += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (carry_reg2 & (1 << 2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) adapter->stats.tx_collisions += COUNTER_WRAP_12_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static int et131x_mdio_read(struct mii_bus *bus, int phy_addr, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) struct net_device *netdev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) u16 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) ret = et131x_phy_mii_read(adapter, phy_addr, reg, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) static int et131x_mdio_write(struct mii_bus *bus, int phy_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) int reg, u16 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct net_device *netdev = bus->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) return et131x_mii_write(adapter, phy_addr, reg, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /* et1310_phy_power_switch - PHY power control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * @adapter: device to control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) * @down: true for off/false for back on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) * one hundred, ten, one thousand megs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) * How would you like to have your LAN accessed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) * Can't you see that this code processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) * Phy power, phy power..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) static void et1310_phy_power_switch(struct et131x_adapter *adapter, bool down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) u16 data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) et131x_mii_read(adapter, MII_BMCR, &data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) data &= ~BMCR_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) if (down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) data |= BMCR_PDOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) et131x_mii_write(adapter, phydev->mdio.addr, MII_BMCR, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) /* et131x_xcvr_init - Init the phy if we are setting it into force mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static void et131x_xcvr_init(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) u16 lcr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* Set the LED behavior such that LED 1 indicates speed (off =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) * 10Mbits, blink = 100Mbits, on = 1000Mbits) and LED 2 indicates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) * link and activity (on for link, blink off for activity).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) * NOTE: Some customizations have been added here for specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * vendors; The LED behavior is now determined by vendor data in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * EEPROM. However, the above description is the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if ((adapter->eeprom_data[1] & 0x4) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) et131x_mii_read(adapter, PHY_LED_2, &lcr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) lcr2 &= (ET_LED2_LED_100TX | ET_LED2_LED_1000T);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) lcr2 |= (LED_VAL_LINKON_ACTIVE << LED_LINK_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if ((adapter->eeprom_data[1] & 0x8) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) lcr2 |= (LED_VAL_1000BT_100BTX << LED_TXRX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) lcr2 |= (LED_VAL_LINKON << LED_TXRX_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) et131x_mii_write(adapter, phydev->mdio.addr, PHY_LED_2, lcr2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) /* et131x_configure_global_regs - configure JAGCore global regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) static void et131x_configure_global_regs(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) struct global_regs __iomem *regs = &adapter->regs->global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) writel(0, ®s->rxq_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) writel(INTERNAL_MEM_SIZE - 1, ®s->txq_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (adapter->registry_jumbo_packet < 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* Tx / RxDMA and Tx/Rx MAC interfaces have a 1k word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) * block of RAM that the driver can split between Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) * and Rx as it desires. Our default is to split it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) * 50/50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) writel(PARM_RX_MEM_END_DEF, ®s->rxq_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) writel(PARM_RX_MEM_END_DEF + 1, ®s->txq_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) } else if (adapter->registry_jumbo_packet < 8192) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* For jumbo packets > 2k but < 8k, split 50-50. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) writel(INTERNAL_MEM_RX_OFFSET, ®s->rxq_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) writel(INTERNAL_MEM_RX_OFFSET + 1, ®s->txq_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) /* 9216 is the only packet size greater than 8k that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) * is available. The Tx buffer has to be big enough
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) * for one whole packet on the Tx side. We'll make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) * the Tx 9408, and give the rest to Rx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) writel(0x01b3, ®s->rxq_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) writel(0x01b4, ®s->txq_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) /* Initialize the loopback register. Disable all loopbacks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) writel(0, ®s->loopback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) writel(0, ®s->msi_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /* By default, disable the watchdog timer. It will be enabled when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * a packet is queued.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) writel(0, ®s->watchdog_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) /* et131x_config_rx_dma_regs - Start of Rx_DMA init sequence */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) static void et131x_config_rx_dma_regs(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct rx_ring *rx_local = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) struct fbr_desc *fbr_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) u32 entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u32 psr_num_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) et131x_rx_dma_disable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) /* Load the completion writeback physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) writel(upper_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) writel(lower_32_bits(rx_local->rx_status_bus), &rx_dma->dma_wb_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) memset(rx_local->rx_status_block, 0, sizeof(struct rx_status_block));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) /* Set the address and parameters of the packet status ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) writel(upper_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) writel(lower_32_bits(rx_local->ps_ring_physaddr), &rx_dma->psr_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) writel(rx_local->psr_entries - 1, &rx_dma->psr_num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) writel(0, &rx_dma->psr_full_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) psr_num_des = readl(&rx_dma->psr_num_des) & ET_RXDMA_PSR_NUM_DES_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) writel((psr_num_des * LO_MARK_PERCENT_FOR_PSR) / 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) &rx_dma->psr_min_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) spin_lock_irqsave(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) /* These local variables track the PSR in the adapter structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) rx_local->local_psr_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) for (id = 0; id < NUM_FBRS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) u32 __iomem *num_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) u32 __iomem *full_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) u32 __iomem *min_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) u32 __iomem *base_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) u32 __iomem *base_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) struct fbr_lookup *fbr = rx_local->fbr[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) if (id == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) num_des = &rx_dma->fbr0_num_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) full_offset = &rx_dma->fbr0_full_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) min_des = &rx_dma->fbr0_min_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) base_hi = &rx_dma->fbr0_base_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) base_lo = &rx_dma->fbr0_base_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) num_des = &rx_dma->fbr1_num_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) full_offset = &rx_dma->fbr1_full_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) min_des = &rx_dma->fbr1_min_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) base_hi = &rx_dma->fbr1_base_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) base_lo = &rx_dma->fbr1_base_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /* Now's the best time to initialize FBR contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) fbr_entry = fbr->ring_virtaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) for (entry = 0; entry < fbr->num_entries; entry++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) fbr_entry->addr_hi = fbr->bus_high[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) fbr_entry->addr_lo = fbr->bus_low[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) fbr_entry->word2 = entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) fbr_entry++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* Set the address and parameters of Free buffer ring 1 and 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) writel(upper_32_bits(fbr->ring_physaddr), base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) writel(lower_32_bits(fbr->ring_physaddr), base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) writel(fbr->num_entries - 1, num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) writel(ET_DMA10_WRAP, full_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) /* This variable tracks the free buffer ring 1 full position,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) * so it has to match the above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) fbr->local_full = ET_DMA10_WRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) writel(((fbr->num_entries * LO_MARK_PERCENT_FOR_RX) / 100) - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) min_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) /* Program the number of packets we will receive before generating an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) * For version B silicon, this value gets updated once autoneg is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) *complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) writel(PARM_RX_NUM_BUFS_DEF, &rx_dma->num_pkt_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) /* The "time_done" is not working correctly to coalesce interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * after a given time period, but rather is giving us an interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) * regardless of whether we have received packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) * This value gets updated once autoneg is complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) writel(PARM_RX_TIME_INT_DEF, &rx_dma->max_pkt_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) spin_unlock_irqrestore(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) /* et131x_config_tx_dma_regs - Set up the tx dma section of the JAGCore.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) * Configure the transmit engine with the ring buffers we have created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) * and prepare it for use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) static void et131x_config_tx_dma_regs(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) struct txdma_regs __iomem *txdma = &adapter->regs->txdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) /* Load the hardware with the start of the transmit descriptor ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) writel(upper_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) writel(lower_32_bits(tx_ring->tx_desc_ring_pa), &txdma->pr_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /* Initialise the transmit DMA engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) writel(NUM_DESC_PER_RING_TX - 1, &txdma->pr_num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* Load the completion writeback physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) writel(upper_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) writel(lower_32_bits(tx_ring->tx_status_pa), &txdma->dma_wb_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) *tx_ring->tx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) writel(0, &txdma->service_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) tx_ring->send_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* et131x_adapter_setup - Set the adapter up as per cassini+ documentation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) static void et131x_adapter_setup(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) et131x_configure_global_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) et1310_config_mac_regs1(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* Configure the MMC registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) /* All we need to do is initialize the Memory Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) writel(ET_MMC_ENABLE, &adapter->regs->mmc.mmc_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) et1310_config_rxmac_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) et1310_config_txmac_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) et131x_config_rx_dma_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) et131x_config_tx_dma_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) et1310_config_macstat_regs(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) et1310_phy_power_switch(adapter, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) et131x_xcvr_init(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* et131x_soft_reset - Issue soft reset to the hardware, complete for ET1310 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) static void et131x_soft_reset(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) /* Disable MAC Core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) reg = ET_MAC_CFG1_SOFT_RESET | ET_MAC_CFG1_SIM_RESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) writel(reg, &adapter->regs->mac.cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) reg = ET_RESET_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) writel(reg, &adapter->regs->global.sw_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) reg = ET_MAC_CFG1_RESET_RXMC | ET_MAC_CFG1_RESET_TXMC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) ET_MAC_CFG1_RESET_RXFUNC | ET_MAC_CFG1_RESET_TXFUNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) writel(reg, &adapter->regs->mac.cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) writel(0, &adapter->regs->mac.cfg1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) static void et131x_enable_interrupts(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) mask = INT_MASK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) mask = INT_MASK_ENABLE_NO_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) writel(mask, &adapter->regs->global.int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static void et131x_disable_interrupts(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) writel(INT_MASK_DISABLE, &adapter->regs->global.int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static void et131x_tx_dma_disable(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) /* Setup the transmit dma configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) writel(ET_TXDMA_CSR_HALT | ET_TXDMA_SNGL_EPKT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) &adapter->regs->txdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) static void et131x_enable_txrx(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) et131x_rx_dma_enable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) et131x_tx_dma_enable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) et131x_enable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) netif_start_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) static void et131x_disable_txrx(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) et131x_rx_dma_disable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) et131x_tx_dma_disable(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) et131x_disable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) static void et131x_init_send(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) struct tcb *tcb = tx_ring->tcb_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) tx_ring->tcb_qhead = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) memset(tcb, 0, sizeof(struct tcb) * NUM_TCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) for (i = 0; i < NUM_TCB; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) tcb->next = tcb + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) tcb++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) tcb--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) tx_ring->tcb_qtail = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) tcb->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) /* Curr send queue should now be empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) tx_ring->send_head = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) tx_ring->send_tail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* et1310_enable_phy_coma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) * driver receive an phy status change interrupt while in D0 and check that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) * phy_status is down.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) * -- gate off JAGCore;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) * -- set gigE PHY in Coma mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) * -- wake on phy_interrupt; Perform software reset JAGCore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) * re-initialize jagcore and gigE PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static void et1310_enable_phy_coma(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) u32 pmcsr = readl(&adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) /* Stop sending packets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) adapter->flags |= FMP_ADAPTER_LOWER_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* Wait for outstanding Receive packets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) et131x_disable_txrx(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) /* Gate off JAGCore 3 clock domains */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) pmcsr &= ~ET_PMCSR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) writel(pmcsr, &adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* Program gigE PHY in to Coma mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) pmcsr |= ET_PM_PHY_SW_COMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) writel(pmcsr, &adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) static void et1310_disable_phy_coma(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) u32 pmcsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) pmcsr = readl(&adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) /* Disable phy_sw_coma register and re-enable JAGCore clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) pmcsr |= ET_PMCSR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) pmcsr &= ~ET_PM_PHY_SW_COMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) writel(pmcsr, &adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* Restore the GbE PHY speed and duplex modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) * Reset JAGCore; re-configure and initialize JAGCore and gigE PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) /* Re-initialize the send structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) et131x_init_send(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) /* Bring the device back to the state it was during init prior to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) * autonegotiation being complete. This way, when we get the auto-neg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) * complete interrupt, we can complete init by calling ConfigMacREGS2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) et131x_soft_reset(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) et131x_adapter_setup(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) /* Allow Tx to restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) adapter->flags &= ~FMP_ADAPTER_LOWER_POWER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) et131x_enable_txrx(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static inline u32 bump_free_buff_ring(u32 *free_buff_ring, u32 limit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) u32 tmp_free_buff_ring = *free_buff_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) tmp_free_buff_ring++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) /* This works for all cases where limit < 1024. The 1023 case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) * works because 1023++ is 1024 which means the if condition is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) * taken but the carry of the bit into the wrap bit toggles the wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * value correctly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if ((tmp_free_buff_ring & ET_DMA10_MASK) > limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) tmp_free_buff_ring &= ~ET_DMA10_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) tmp_free_buff_ring ^= ET_DMA10_WRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* For the 1023 case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) tmp_free_buff_ring &= (ET_DMA10_MASK | ET_DMA10_WRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) *free_buff_ring = tmp_free_buff_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) return tmp_free_buff_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) /* et131x_rx_dma_memory_alloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) * Allocates Free buffer ring 1 for sure, free buffer ring 0 if required,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) * and the Packet Status Ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static int et131x_rx_dma_memory_alloc(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) u32 i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) u32 bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) u32 psr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) u32 fbr_chunksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) struct rx_ring *rx_ring = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) struct fbr_lookup *fbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /* Alloc memory for the lookup table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) rx_ring->fbr[0] = kzalloc(sizeof(*fbr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (rx_ring->fbr[0] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) rx_ring->fbr[1] = kzalloc(sizeof(*fbr), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) if (rx_ring->fbr[1] == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) /* The first thing we will do is configure the sizes of the buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) * rings. These will change based on jumbo packet support. Larger
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) * jumbo packets increases the size of each entry in FBR0, and the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) * number of entries in FBR0, while at the same time decreasing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) * number of entries in FBR1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) * FBR1 holds "large" frames, FBR0 holds "small" frames. If FBR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) * entries are huge in order to accommodate a "jumbo" frame, then it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) * will have less entries. Conversely, FBR1 will now be relied upon
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) * to carry more "normal" frames, thus it's entry size also increases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) * and the number of entries goes up too (since it now carries
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * "small" + "regular" packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) * In this scheme, we try to maintain 512 entries between the two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) * rings. Also, FBR1 remains a constant size - when it's size doubles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) * the number of entries halves. FBR0 increases in size, however.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (adapter->registry_jumbo_packet < 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) rx_ring->fbr[0]->buffsize = 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) rx_ring->fbr[0]->num_entries = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) rx_ring->fbr[1]->buffsize = 2048;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) rx_ring->fbr[1]->num_entries = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) } else if (adapter->registry_jumbo_packet < 4096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) rx_ring->fbr[0]->buffsize = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) rx_ring->fbr[0]->num_entries = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) rx_ring->fbr[1]->buffsize = 4096;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) rx_ring->fbr[1]->num_entries = 512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) rx_ring->fbr[0]->buffsize = 1024;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) rx_ring->fbr[0]->num_entries = 768;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) rx_ring->fbr[1]->buffsize = 16384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) rx_ring->fbr[1]->num_entries = 128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) rx_ring->psr_entries = rx_ring->fbr[0]->num_entries +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) rx_ring->fbr[1]->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) for (id = 0; id < NUM_FBRS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) fbr = rx_ring->fbr[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) /* Allocate an area of memory for Free Buffer Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) fbr->ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) bufsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) &fbr->ring_physaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (!fbr->ring_virtaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) "Cannot alloc memory for Free Buffer Ring %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) for (id = 0; id < NUM_FBRS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) fbr = rx_ring->fbr[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) fbr_chunksize = (FBR_CHUNKS * fbr->buffsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) for (i = 0; i < fbr->num_entries / FBR_CHUNKS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) dma_addr_t fbr_physaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) fbr->mem_virtaddrs[i] = dma_alloc_coherent(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) &adapter->pdev->dev, fbr_chunksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) &fbr->mem_physaddrs[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) if (!fbr->mem_virtaddrs[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) "Could not alloc memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) /* See NOTE in "Save Physical Address" comment above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) fbr_physaddr = fbr->mem_physaddrs[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) for (j = 0; j < FBR_CHUNKS; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) u32 k = (i * FBR_CHUNKS) + j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /* Save the Virtual address of this index for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * quick access later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) fbr->virt[k] = (u8 *)fbr->mem_virtaddrs[i] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) (j * fbr->buffsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) /* now store the physical address in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) * descriptor so the device can access it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) fbr->bus_high[k] = upper_32_bits(fbr_physaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) fbr->bus_low[k] = lower_32_bits(fbr_physaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) fbr_physaddr += fbr->buffsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) /* Allocate an area of memory for FIFO of Packet Status ring entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) psr_size = sizeof(struct pkt_stat_desc) * rx_ring->psr_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) rx_ring->ps_ring_virtaddr = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) psr_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) &rx_ring->ps_ring_physaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) if (!rx_ring->ps_ring_virtaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) "Cannot alloc memory for Packet Status Ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* Allocate an area of memory for writeback of status information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) rx_ring->rx_status_block = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) sizeof(struct rx_status_block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) &rx_ring->rx_status_bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) if (!rx_ring->rx_status_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) "Cannot alloc memory for Status Block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) rx_ring->num_rfd = NIC_DEFAULT_NUM_RFD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* The RFDs are going to be put on lists later on, so initialize the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * lists now.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) INIT_LIST_HEAD(&rx_ring->recv_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static void et131x_rx_dma_memory_free(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) u8 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) u32 ii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) u32 bufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) u32 psr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) struct rfd *rfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) struct rx_ring *rx_ring = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) struct fbr_lookup *fbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) /* Free RFDs and associated packet descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) WARN_ON(rx_ring->num_ready_recv != rx_ring->num_rfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) while (!list_empty(&rx_ring->recv_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) rfd = list_entry(rx_ring->recv_list.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) struct rfd, list_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) list_del(&rfd->list_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) rfd->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) kfree(rfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) /* Free Free Buffer Rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) for (id = 0; id < NUM_FBRS; id++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) fbr = rx_ring->fbr[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) if (!fbr || !fbr->ring_virtaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /* First the packet memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) for (ii = 0; ii < fbr->num_entries / FBR_CHUNKS; ii++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) if (fbr->mem_virtaddrs[ii]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) bufsize = fbr->buffsize * FBR_CHUNKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) bufsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) fbr->mem_virtaddrs[ii],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) fbr->mem_physaddrs[ii]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) fbr->mem_virtaddrs[ii] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) bufsize = sizeof(struct fbr_desc) * fbr->num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) bufsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) fbr->ring_virtaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) fbr->ring_physaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) fbr->ring_virtaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) /* Free Packet Status Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (rx_ring->ps_ring_virtaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) psr_size = sizeof(struct pkt_stat_desc) * rx_ring->psr_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dma_free_coherent(&adapter->pdev->dev, psr_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) rx_ring->ps_ring_virtaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) rx_ring->ps_ring_physaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) rx_ring->ps_ring_virtaddr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* Free area of memory for the writeback of status information */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) if (rx_ring->rx_status_block) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) sizeof(struct rx_status_block),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) rx_ring->rx_status_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) rx_ring->rx_status_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) rx_ring->rx_status_block = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) /* Free the FBR Lookup Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) kfree(rx_ring->fbr[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) kfree(rx_ring->fbr[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* Reset Counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) rx_ring->num_ready_recv = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /* et131x_init_recv - Initialize receive data structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) static int et131x_init_recv(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) struct rfd *rfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) u32 rfdct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) struct rx_ring *rx_ring = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) /* Setup each RFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) for (rfdct = 0; rfdct < rx_ring->num_rfd; rfdct++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) rfd = kzalloc(sizeof(*rfd), GFP_ATOMIC | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (!rfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) rfd->skb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) /* Add this RFD to the recv_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) list_add_tail(&rfd->list_node, &rx_ring->recv_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) /* Increment the available RFD's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) rx_ring->num_ready_recv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* et131x_set_rx_dma_timer - Set the heartbeat timer according to line rate */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) static void et131x_set_rx_dma_timer(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /* For version B silicon, we do not use the RxDMA timer for 10 and 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) * Mbits/s line rates. We do not enable and RxDMA interrupt coalescing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) if ((phydev->speed == SPEED_100) || (phydev->speed == SPEED_10)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) writel(0, &adapter->regs->rxdma.max_pkt_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) writel(1, &adapter->regs->rxdma.num_pkt_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /* nic_return_rfd - Recycle a RFD and put it back onto the receive list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static void nic_return_rfd(struct et131x_adapter *adapter, struct rfd *rfd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) struct rx_ring *rx_local = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct rxdma_regs __iomem *rx_dma = &adapter->regs->rxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) u16 buff_index = rfd->bufferindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) u8 ring_index = rfd->ringindex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) struct fbr_lookup *fbr = rx_local->fbr[ring_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) /* We don't use any of the OOB data besides status. Otherwise, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) * need to clean up OOB data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (buff_index < fbr->num_entries) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) u32 free_buff_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) u32 __iomem *offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct fbr_desc *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (ring_index == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) offset = &rx_dma->fbr0_full_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) offset = &rx_dma->fbr1_full_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) next = (struct fbr_desc *)(fbr->ring_virtaddr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) INDEX10(fbr->local_full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) /* Handle the Free Buffer Ring advancement here. Write
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * the PA / Buffer Index for the returned buffer into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) * the oldest (next to be freed)FBR entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) next->addr_hi = fbr->bus_high[buff_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) next->addr_lo = fbr->bus_low[buff_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) next->word2 = buff_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) free_buff_ring = bump_free_buff_ring(&fbr->local_full,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) fbr->num_entries - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) writel(free_buff_ring, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) "%s illegal Buffer Index returned\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) /* The processing on this RFD is done, so put it back on the tail of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) * our list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) spin_lock_irqsave(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) list_add_tail(&rfd->list_node, &rx_local->recv_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) rx_local->num_ready_recv++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) spin_unlock_irqrestore(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) WARN_ON(rx_local->num_ready_recv > rx_local->num_rfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /* nic_rx_pkts - Checks the hardware for available packets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * Checks the hardware for available packets, using completion ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) * If packets are available, it gets an RFD from the recv_list, attaches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) * the packet to it, puts the RFD in the RecvPendList, and also returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) * the pointer to the RFD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) static struct rfd *nic_rx_pkts(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) struct rx_ring *rx_local = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) struct rx_status_block *status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) struct pkt_stat_desc *psr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) struct rfd *rfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) struct list_head *element;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) u8 ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) u16 buff_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) u32 word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) u32 word1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct fbr_lookup *fbr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) /* RX Status block is written by the DMA engine prior to every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) * interrupt. It contains the next to be used entry in the Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) * Status Ring, and also the two Free Buffer rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) status = rx_local->rx_status_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) word1 = status->word1 >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) /* Check the PSR and wrap bits do not match */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) if ((word1 & 0x1FFF) == (rx_local->local_psr_full & 0x1FFF))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) return NULL; /* Looks like this ring is not updated yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) /* The packet status ring indicates that data is available. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) psr = (struct pkt_stat_desc *)(rx_local->ps_ring_virtaddr) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) (rx_local->local_psr_full & 0xFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) /* Grab any information that is required once the PSR is advanced,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) * since we can no longer rely on the memory being accurate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) len = psr->word1 & 0xFFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) ring_index = (psr->word1 >> 26) & 0x03;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) fbr = rx_local->fbr[ring_index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) buff_index = (psr->word1 >> 16) & 0x3FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) word0 = psr->word0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) /* Indicate that we have used this PSR entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) /* FIXME wrap 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) add_12bit(&rx_local->local_psr_full, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) if ((rx_local->local_psr_full & 0xFFF) > rx_local->psr_entries - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) /* Clear psr full and toggle the wrap bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) rx_local->local_psr_full &= ~0xFFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) rx_local->local_psr_full ^= 0x1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) writel(rx_local->local_psr_full, &adapter->regs->rxdma.psr_full_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) if (ring_index > 1 || buff_index > fbr->num_entries - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) /* Illegal buffer or ring index cannot be used by S/W*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) "NICRxPkts PSR Entry %d indicates length of %d and/or bad bi(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) rx_local->local_psr_full & 0xFFF, len, buff_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /* Get and fill the RFD. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) spin_lock_irqsave(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) element = rx_local->recv_list.next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) rfd = list_entry(element, struct rfd, list_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (!rfd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) spin_unlock_irqrestore(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) list_del(&rfd->list_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) rx_local->num_ready_recv--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) spin_unlock_irqrestore(&adapter->rcv_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) rfd->bufferindex = buff_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) rfd->ringindex = ring_index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) /* In V1 silicon, there is a bug which screws up filtering of runt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) * packets. Therefore runt packet filtering is disabled in the MAC and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) * the packets are dropped here. They are also counted here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) if (len < (NIC_MIN_PACKET_SIZE + 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) adapter->stats.rx_other_errs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) rfd->len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) if ((word0 & ALCATEL_MULTICAST_PKT) && !(word0 & ALCATEL_BROADCAST_PKT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) adapter->stats.multicast_pkts_rcvd++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) rfd->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) skb = dev_alloc_skb(rfd->len + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) if (!skb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) adapter->netdev->stats.rx_bytes += rfd->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) skb_put_data(skb, fbr->virt[buff_index], rfd->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) skb->protocol = eth_type_trans(skb, adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) skb->ip_summed = CHECKSUM_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) netif_receive_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) nic_return_rfd(adapter, rfd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) return rfd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static int et131x_handle_recv_pkts(struct et131x_adapter *adapter, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct rfd *rfd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) int limit = budget;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) bool done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) struct rx_ring *rx_ring = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) if (budget > MAX_PACKETS_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) limit = MAX_PACKETS_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /* Process up to available RFD's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) while (count < limit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (list_empty(&rx_ring->recv_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) WARN_ON(rx_ring->num_ready_recv != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) done = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) rfd = nic_rx_pkts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) if (rfd == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) /* Do not receive any packets until a filter has been set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) * Do not receive any packets until we have link.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) * If length is zero, return the RFD in order to advance the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) * Free buffer ring.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) if (!adapter->packet_filter ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) !netif_carrier_ok(adapter->netdev) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) rfd->len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) adapter->netdev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) if (rx_ring->num_ready_recv < RFD_LOW_WATER_MARK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) dev_warn(&adapter->pdev->dev, "RFD's are running out\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (count == limit || !done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) rx_ring->unfinished_receives = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) &adapter->regs->global.watchdog_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /* Watchdog timer will disable itself if appropriate. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) rx_ring->unfinished_receives = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) /* et131x_tx_dma_memory_alloc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) * Allocates memory that will be visible both to the device and to the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) * The OS will pass us packets, pointers to which we will insert in the Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) * Descriptor queue. The device will read this queue to find the packets in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) * memory. The device will update the "status" in memory each time it xmits a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) * packet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) static int et131x_tx_dma_memory_alloc(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) int desc_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* Allocate memory for the TCB's (Transmit Control Block) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) tx_ring->tcb_ring = kcalloc(NUM_TCB, sizeof(struct tcb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) GFP_KERNEL | GFP_DMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) if (!tx_ring->tcb_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) tx_ring->tx_desc_ring = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) &tx_ring->tx_desc_ring_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) if (!tx_ring->tx_desc_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) "Cannot alloc memory for Tx Ring\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) tx_ring->tx_status = dma_alloc_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) &tx_ring->tx_status_pa,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) if (!tx_ring->tx_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) "Cannot alloc memory for Tx status block\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) static void et131x_tx_dma_memory_free(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) int desc_size = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) if (tx_ring->tx_desc_ring) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) /* Free memory relating to Tx rings here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) desc_size = (sizeof(struct tx_desc) * NUM_DESC_PER_RING_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) desc_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) tx_ring->tx_desc_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) tx_ring->tx_desc_ring_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) tx_ring->tx_desc_ring = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) /* Free memory for the Tx status block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (tx_ring->tx_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) dma_free_coherent(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) sizeof(u32),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) tx_ring->tx_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) tx_ring->tx_status_pa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) tx_ring->tx_status = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) /* Free the memory for the tcb structures */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) kfree(tx_ring->tcb_ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) /* nic_send_packet - NIC specific send handler for version B silicon. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) static int nic_send_packet(struct et131x_adapter *adapter, struct tcb *tcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) struct tx_desc desc[24];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) u32 frag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) u32 thiscopy, remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) struct sk_buff *skb = tcb->skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) u32 nr_frags = skb_shinfo(skb)->nr_frags + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) skb_frag_t *frags = &skb_shinfo(skb)->frags[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) /* Part of the optimizations of this send routine restrict us to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) * sending 24 fragments at a pass. In practice we should never see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) * more than 5 fragments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) /* nr_frags should be no more than 18. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) BUILD_BUG_ON(MAX_SKB_FRAGS + 1 > 23);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) memset(desc, 0, sizeof(struct tx_desc) * (nr_frags + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) for (i = 0; i < nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) /* If there is something in this element, lets get a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) * descriptor from the ring and get the necessary data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) /* If the fragments are smaller than a standard MTU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) * then map them to a single descriptor in the Tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) * Desc ring. However, if they're larger, as is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) * possible with support for jumbo packets, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) * split them each across 2 descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) * This will work until we determine why the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) * doesn't seem to like large fragments.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) if (skb_headlen(skb) <= 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* Low 16bits are length, high is vlan and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * unused currently so zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) desc[frag].len_vlan = skb_headlen(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) dma_addr = dma_map_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) skb_headlen(skb),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) desc[frag].addr_lo = lower_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) desc[frag].addr_hi = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) desc[frag].len_vlan = skb_headlen(skb) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) dma_addr = dma_map_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) skb_headlen(skb) / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) desc[frag].addr_lo = lower_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) desc[frag].addr_hi = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) desc[frag].len_vlan = skb_headlen(skb) / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) dma_addr = dma_map_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) skb->data +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) skb_headlen(skb) / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) skb_headlen(skb) / 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) desc[frag].addr_lo = lower_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) desc[frag].addr_hi = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) desc[frag].len_vlan = skb_frag_size(&frags[i - 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) dma_addr = skb_frag_dma_map(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) &frags[i - 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) desc[frag].len_vlan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) desc[frag].addr_lo = lower_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) desc[frag].addr_hi = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) frag++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) if (phydev && phydev->speed == SPEED_1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) if (++tx_ring->since_irq == PARM_TX_NUM_BUFS_DEF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) /* Last element & Interrupt flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) desc[frag - 1].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) tx_ring->since_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) } else { /* Last element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) desc[frag - 1].flags = TXDESC_FLAG_LASTPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) desc[frag - 1].flags =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) TXDESC_FLAG_INTPROC | TXDESC_FLAG_LASTPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) desc[0].flags |= TXDESC_FLAG_FIRSTPKT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) tcb->index_start = tx_ring->send_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) tcb->stale = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) thiscopy = NUM_DESC_PER_RING_TX - INDEX10(tx_ring->send_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) if (thiscopy >= frag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) remainder = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) thiscopy = frag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) remainder = frag - thiscopy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) memcpy(tx_ring->tx_desc_ring + INDEX10(tx_ring->send_idx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) sizeof(struct tx_desc) * thiscopy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) add_10bit(&tx_ring->send_idx, thiscopy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (INDEX10(tx_ring->send_idx) == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) INDEX10(tx_ring->send_idx) == NUM_DESC_PER_RING_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) tx_ring->send_idx &= ~ET_DMA10_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) tx_ring->send_idx ^= ET_DMA10_WRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) memcpy(tx_ring->tx_desc_ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) desc + thiscopy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) sizeof(struct tx_desc) * remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) add_10bit(&tx_ring->send_idx, remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (INDEX10(tx_ring->send_idx) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) if (tx_ring->send_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) tcb->index = NUM_DESC_PER_RING_TX - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) tcb->index = ET_DMA10_WRAP|(NUM_DESC_PER_RING_TX - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) tcb->index = tx_ring->send_idx - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) spin_lock(&adapter->tcb_send_qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) if (tx_ring->send_tail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) tx_ring->send_tail->next = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) tx_ring->send_head = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) tx_ring->send_tail = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) WARN_ON(tcb->next != NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) tx_ring->used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) spin_unlock(&adapter->tcb_send_qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) /* Write the new write pointer back to the device. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) writel(tx_ring->send_idx, &adapter->regs->txdma.service_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) /* For Gig only, we use Tx Interrupt coalescing. Enable the software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) * timer to wake us up if this packet isn't followed by N more.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (phydev && phydev->speed == SPEED_1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) writel(PARM_TX_TIME_INT_DEF * NANO_IN_A_MICRO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) &adapter->regs->global.watchdog_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) static int send_packet(struct sk_buff *skb, struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) struct tcb *tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) /* All packets must have at least a MAC address and a protocol type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) if (skb->len < ETH_HLEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) tcb = tx_ring->tcb_qhead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (tcb == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) tx_ring->tcb_qhead = tcb->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) if (tx_ring->tcb_qhead == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) tx_ring->tcb_qtail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) tcb->skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) tcb->next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) status = nic_send_packet(adapter, tcb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (status != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (tx_ring->tcb_qtail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) tx_ring->tcb_qtail->next = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) /* Apparently ready Q is empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) tx_ring->tcb_qhead = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) tx_ring->tcb_qtail = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) WARN_ON(tx_ring->used > NUM_TCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) /* free_send_packet - Recycle a struct tcb */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) static inline void free_send_packet(struct et131x_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) struct tcb *tcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) struct tx_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) struct net_device_stats *stats = &adapter->netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) u64 dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (tcb->skb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) stats->tx_bytes += tcb->skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) /* Iterate through the TX descriptors on the ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) * corresponding to this packet and umap the fragments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) * they point to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) desc = tx_ring->tx_desc_ring +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) INDEX10(tcb->index_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) dma_addr = desc->addr_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) dma_addr |= (u64)desc->addr_hi << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) dma_unmap_single(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) desc->len_vlan, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) add_10bit(&tcb->index_start, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) if (INDEX10(tcb->index_start) >=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) NUM_DESC_PER_RING_TX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) tcb->index_start &= ~ET_DMA10_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) tcb->index_start ^= ET_DMA10_WRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) } while (desc != tx_ring->tx_desc_ring + INDEX10(tcb->index));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) dev_kfree_skb_any(tcb->skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) memset(tcb, 0, sizeof(struct tcb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) /* Add the TCB to the Ready Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) spin_lock_irqsave(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) stats->tx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) if (tx_ring->tcb_qtail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) tx_ring->tcb_qtail->next = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) else /* Apparently ready Q is empty. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) tx_ring->tcb_qhead = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) tx_ring->tcb_qtail = tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) spin_unlock_irqrestore(&adapter->tcb_ready_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) WARN_ON(tx_ring->used < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) /* et131x_free_busy_send_packets - Free and complete the stopped active sends */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) static void et131x_free_busy_send_packets(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) struct tcb *tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) u32 freed = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) /* Any packets being sent? Check the first TCB on the send list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) while (tcb != NULL && freed < NUM_TCB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) struct tcb *next = tcb->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) tx_ring->send_head = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) if (next == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) tx_ring->send_tail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) tx_ring->used--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) freed++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) free_send_packet(adapter, tcb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) WARN_ON(freed == NUM_TCB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) tx_ring->used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) /* et131x_handle_send_pkts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) * Re-claim the send resources, complete sends and get more to send from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) * the send wait queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) static void et131x_handle_send_pkts(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) u32 serviced;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) struct tcb *tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) u32 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) serviced = readl(&adapter->regs->txdma.new_service_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) index = INDEX10(serviced);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) /* Has the ring wrapped? Process any descriptors that do not have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) * the same "wrap" indicator as the current completion indicator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) while (tcb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) ((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) index < INDEX10(tcb->index)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) tx_ring->used--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) tx_ring->send_head = tcb->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) if (tcb->next == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) tx_ring->send_tail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) free_send_packet(adapter, tcb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) /* Goto the next packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) while (tcb &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) !((serviced ^ tcb->index) & ET_DMA10_WRAP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) index > (tcb->index & ET_DMA10_MASK)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) tx_ring->used--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) tx_ring->send_head = tcb->next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) if (tcb->next == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) tx_ring->send_tail = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) free_send_packet(adapter, tcb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) /* Goto the next packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) /* Wake up the queue when we hit a low-water mark */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) if (tx_ring->used <= NUM_TCB / 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) netif_wake_queue(adapter->netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) static int et131x_get_regs_len(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) #define ET131X_REGS_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) return ET131X_REGS_LEN * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) static void et131x_get_regs(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) struct ethtool_regs *regs, void *regs_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) struct address_map __iomem *aregs = adapter->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) u32 *regs_buff = regs_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) u32 num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) u16 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) memset(regs_data, 0, et131x_get_regs_len(netdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) regs->version = (1 << 24) | (adapter->pdev->revision << 16) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) adapter->pdev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) /* PHY regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) et131x_mii_read(adapter, MII_BMCR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) et131x_mii_read(adapter, MII_BMSR, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) et131x_mii_read(adapter, MII_PHYSID1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) et131x_mii_read(adapter, MII_PHYSID2, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) et131x_mii_read(adapter, MII_ADVERTISE, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) et131x_mii_read(adapter, MII_LPA, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) et131x_mii_read(adapter, MII_EXPANSION, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) /* Autoneg next page transmit reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) et131x_mii_read(adapter, 0x07, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) /* Link partner next page reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) et131x_mii_read(adapter, 0x08, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) et131x_mii_read(adapter, MII_CTRL1000, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) et131x_mii_read(adapter, MII_STAT1000, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) et131x_mii_read(adapter, 0x0b, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) et131x_mii_read(adapter, 0x0c, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) et131x_mii_read(adapter, MII_MMD_CTRL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) et131x_mii_read(adapter, MII_MMD_DATA, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) et131x_mii_read(adapter, MII_ESTATUS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) et131x_mii_read(adapter, PHY_INDEX_REG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) et131x_mii_read(adapter, PHY_DATA_REG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) et131x_mii_read(adapter, PHY_LOOPBACK_CONTROL + 1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) et131x_mii_read(adapter, PHY_REGISTER_MGMT_CONTROL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) et131x_mii_read(adapter, PHY_CONFIG, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) et131x_mii_read(adapter, PHY_PHY_CONTROL, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) et131x_mii_read(adapter, PHY_INTERRUPT_MASK, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) et131x_mii_read(adapter, PHY_INTERRUPT_STATUS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) et131x_mii_read(adapter, PHY_PHY_STATUS, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) et131x_mii_read(adapter, PHY_LED_1, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) et131x_mii_read(adapter, PHY_LED_2, &tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) regs_buff[num++] = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) /* Global regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) regs_buff[num++] = readl(&aregs->global.txq_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) regs_buff[num++] = readl(&aregs->global.txq_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) regs_buff[num++] = readl(&aregs->global.rxq_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) regs_buff[num++] = readl(&aregs->global.rxq_end_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) regs_buff[num++] = readl(&aregs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) regs_buff[num++] = adapter->stats.interrupt_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) regs_buff[num++] = readl(&aregs->global.int_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) regs_buff[num++] = readl(&aregs->global.int_alias_clr_en);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) regs_buff[num++] = readl(&aregs->global.int_status_alias);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) regs_buff[num++] = readl(&aregs->global.sw_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) regs_buff[num++] = readl(&aregs->global.slv_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) regs_buff[num++] = readl(&aregs->global.msi_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) regs_buff[num++] = readl(&aregs->global.loopback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) regs_buff[num++] = readl(&aregs->global.watchdog_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) /* TXDMA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) regs_buff[num++] = readl(&aregs->txdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) regs_buff[num++] = readl(&aregs->txdma.pr_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) regs_buff[num++] = readl(&aregs->txdma.pr_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) regs_buff[num++] = readl(&aregs->txdma.pr_num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) regs_buff[num++] = readl(&aregs->txdma.txq_wr_addr_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) regs_buff[num++] = readl(&aregs->txdma.txq_rd_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) regs_buff[num++] = readl(&aregs->txdma.dma_wb_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) regs_buff[num++] = readl(&aregs->txdma.service_request);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) regs_buff[num++] = readl(&aregs->txdma.service_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) regs_buff[num++] = readl(&aregs->txdma.cache_rd_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) regs_buff[num++] = readl(&aregs->txdma.cache_wr_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) regs_buff[num++] = readl(&aregs->txdma.tx_dma_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) regs_buff[num++] = readl(&aregs->txdma.desc_abort_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) regs_buff[num++] = readl(&aregs->txdma.payload_abort_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) regs_buff[num++] = readl(&aregs->txdma.writeback_abort_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) regs_buff[num++] = readl(&aregs->txdma.desc_timeout_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) regs_buff[num++] = readl(&aregs->txdma.payload_timeout_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) regs_buff[num++] = readl(&aregs->txdma.writeback_timeout_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) regs_buff[num++] = readl(&aregs->txdma.desc_error_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) regs_buff[num++] = readl(&aregs->txdma.payload_error_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) regs_buff[num++] = readl(&aregs->txdma.writeback_error_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) regs_buff[num++] = readl(&aregs->txdma.dropped_tlp_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) regs_buff[num++] = readl(&aregs->txdma.new_service_complete);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) regs_buff[num++] = readl(&aregs->txdma.ethernet_packet_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) /* RXDMA regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) regs_buff[num++] = readl(&aregs->rxdma.csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) regs_buff[num++] = readl(&aregs->rxdma.dma_wb_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) regs_buff[num++] = readl(&aregs->rxdma.num_pkt_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) regs_buff[num++] = readl(&aregs->rxdma.max_pkt_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) regs_buff[num++] = readl(&aregs->rxdma.rxq_rd_addr_ext);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) regs_buff[num++] = readl(&aregs->rxdma.rxq_wr_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) regs_buff[num++] = readl(&aregs->rxdma.psr_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) regs_buff[num++] = readl(&aregs->rxdma.psr_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) regs_buff[num++] = readl(&aregs->rxdma.psr_num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) regs_buff[num++] = readl(&aregs->rxdma.psr_avail_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) regs_buff[num++] = readl(&aregs->rxdma.psr_full_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) regs_buff[num++] = readl(&aregs->rxdma.psr_access_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) regs_buff[num++] = readl(&aregs->rxdma.psr_min_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) regs_buff[num++] = readl(&aregs->rxdma.fbr0_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) regs_buff[num++] = readl(&aregs->rxdma.fbr0_num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) regs_buff[num++] = readl(&aregs->rxdma.fbr0_avail_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) regs_buff[num++] = readl(&aregs->rxdma.fbr0_full_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) regs_buff[num++] = readl(&aregs->rxdma.fbr0_rd_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) regs_buff[num++] = readl(&aregs->rxdma.fbr0_min_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) regs_buff[num++] = readl(&aregs->rxdma.fbr1_base_hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) regs_buff[num++] = readl(&aregs->rxdma.fbr1_num_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) regs_buff[num++] = readl(&aregs->rxdma.fbr1_avail_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) regs_buff[num++] = readl(&aregs->rxdma.fbr1_full_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) regs_buff[num++] = readl(&aregs->rxdma.fbr1_rd_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) regs_buff[num++] = readl(&aregs->rxdma.fbr1_min_des);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) static void et131x_get_drvinfo(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) strlcpy(info->driver, DRIVER_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) strlcpy(info->bus_info, pci_name(adapter->pdev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) static const struct ethtool_ops et131x_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .get_drvinfo = et131x_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .get_regs_len = et131x_get_regs_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .get_regs = et131x_get_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .get_link_ksettings = phy_ethtool_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) .set_link_ksettings = phy_ethtool_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) /* et131x_hwaddr_init - set up the MAC Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) static void et131x_hwaddr_init(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) /* If have our default mac from init and no mac address from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) * EEPROM then we need to generate the last octet and set it on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) * device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) if (is_zero_ether_addr(adapter->rom_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) /* We need to randomly generate the last octet so we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) * decrease our chances of setting the mac address to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) * same as another one of our cards in the system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) get_random_bytes(&adapter->addr[5], 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) /* We have the default value in the register we are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) * working with so we need to copy the current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) * address into the permanent address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) ether_addr_copy(adapter->rom_addr, adapter->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) /* We do not have an override address, so set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) * current address to the permanent address and add
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) * it to the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) ether_addr_copy(adapter->addr, adapter->rom_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) static int et131x_pci_init(struct et131x_adapter *adapter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) u16 max_payload;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) int i, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) rc = et131x_init_eeprom(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) if (!pci_is_pcie(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) dev_err(&pdev->dev, "Missing PCIe capabilities\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) /* Program the Ack/Nak latency and replay timers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) max_payload = pdev->pcie_mpss;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) if (max_payload < 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) static const u16 acknak[2] = { 0x76, 0xD0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) static const u16 replay[2] = { 0x1E0, 0x2ED };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) if (pci_write_config_word(pdev, ET1310_PCI_ACK_NACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) acknak[max_payload])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) "Could not write PCI config space for ACK/NAK\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) if (pci_write_config_word(pdev, ET1310_PCI_REPLAY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) replay[max_payload])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) "Could not write PCI config space for Replay Timer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* l0s and l1 latency timers. We are using default values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) * Representing 001 for L0s and 010 for L1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) if (pci_write_config_byte(pdev, ET1310_PCI_L0L1LATENCY, 0x11)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) "Could not write PCI config space for Latency Timers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) /* Change the max read size to 2k */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) if (pcie_set_readrq(pdev, 2048)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) "Couldn't change PCI config space for Max read size\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) /* Get MAC address from config space if an eeprom exists, otherwise
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) * the MAC address there will not be valid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) if (!adapter->has_eeprom) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) et131x_hwaddr_init(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) for (i = 0; i < ETH_ALEN; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (pci_read_config_byte(pdev, ET1310_PCI_MAC_ADDRESS + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) adapter->rom_addr + i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) dev_err(&pdev->dev, "Could not read PCI config space for MAC address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) ether_addr_copy(adapter->addr, adapter->rom_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) /* et131x_error_timer_handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) * @data: timer-specific variable; here a pointer to our adapter structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) * The routine called when the error timer expires, to track the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) * recurring errors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) static void et131x_error_timer_handler(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) struct et131x_adapter *adapter = from_timer(adapter, t, error_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) struct phy_device *phydev = adapter->netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) if (et1310_in_phy_coma(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) /* Bring the device immediately out of coma, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) * prevent it from sleeping indefinitely, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) * mechanism could be improved!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) et1310_disable_phy_coma(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) adapter->boot_coma = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) et1310_update_macstat_host_counters(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) if (!phydev->link && adapter->boot_coma < 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) adapter->boot_coma++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) if (adapter->boot_coma == 10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) if (!phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) if (!et1310_in_phy_coma(adapter)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) /* NOTE - This was originally a 'sync with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) * interrupt'. How to do that under Linux?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) et131x_enable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) et1310_enable_phy_coma(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) /* This is a periodic timer, so reschedule */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) mod_timer(&adapter->error_timer, jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) msecs_to_jiffies(TX_ERROR_PERIOD));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) static void et131x_adapter_memory_free(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) et131x_tx_dma_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117) et131x_rx_dma_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) static int et131x_adapter_memory_alloc(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) status = et131x_tx_dma_memory_alloc(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) "et131x_tx_dma_memory_alloc FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) et131x_tx_dma_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) status = et131x_rx_dma_memory_alloc(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) dev_err(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) "et131x_rx_dma_memory_alloc FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) et131x_adapter_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) status = et131x_init_recv(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) if (status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) dev_err(&adapter->pdev->dev, "et131x_init_recv FAILED\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) et131x_adapter_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) static void et131x_adjust_link(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) struct phy_device *phydev = netdev->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) if (!phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) if (phydev->link == adapter->link)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) /* Check to see if we are in coma mode and if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) * so, disable it because we will not be able
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) * to read PHY values until we are out.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) if (et1310_in_phy_coma(adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) et1310_disable_phy_coma(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) adapter->link = phydev->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) phy_print_status(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) if (phydev->link) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) adapter->boot_coma = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) if (phydev->speed == SPEED_10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) u16 register18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) ®ister18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) PHY_MPHY_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) register18 | 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) PHY_INDEX_REG, register18 | 0x8402);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) PHY_DATA_REG, register18 | 511);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) PHY_MPHY_CONTROL_REG, register18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) et1310_config_flow_control(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) if (phydev->speed == SPEED_1000 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) adapter->registry_jumbo_packet > 2048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) et131x_mii_read(adapter, PHY_CONFIG, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) reg &= ~ET_PHY_CONFIG_TX_FIFO_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) reg |= ET_PHY_CONFIG_FIFO_DEPTH_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) PHY_CONFIG, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) et131x_set_rx_dma_timer(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) et1310_config_mac_regs2(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) adapter->boot_coma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) if (phydev->speed == SPEED_10) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) u16 register18;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) et131x_mii_read(adapter, PHY_MPHY_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) ®ister18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) PHY_MPHY_CONTROL_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) register18 | 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) PHY_INDEX_REG, register18 | 0x8402);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) PHY_DATA_REG, register18 | 511);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) et131x_mii_write(adapter, phydev->mdio.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) PHY_MPHY_CONTROL_REG, register18);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) et131x_free_busy_send_packets(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) et131x_init_send(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /* Bring the device back to the state it was during
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) * init prior to autonegotiation being complete. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) * way, when we get the auto-neg complete interrupt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) * we can complete init by calling config_mac_regs2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) et131x_soft_reset(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) et131x_adapter_setup(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) et131x_disable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) et131x_enable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) static int et131x_mii_probe(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) struct phy_device *phydev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) phydev = phy_find_first(adapter->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) if (!phydev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) dev_err(&adapter->pdev->dev, "no PHY found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) phydev = phy_connect(netdev, phydev_name(phydev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) &et131x_adjust_link, PHY_INTERFACE_MODE_MII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) if (IS_ERR(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) dev_err(&adapter->pdev->dev, "Could not attach to PHY\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) return PTR_ERR(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) phy_set_max_speed(phydev, SPEED_100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) if (adapter->pdev->device != ET131X_PCI_DEVICE_ID_FAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) phy_set_max_speed(phydev, SPEED_1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) phydev->autoneg = AUTONEG_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) phy_attached_info(phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) static struct et131x_adapter *et131x_adapter_init(struct net_device *netdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) static const u8 default_mac[] = { 0x00, 0x05, 0x3d, 0x00, 0x02, 0x00 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) struct et131x_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) adapter->pdev = pci_dev_get(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) adapter->netdev = netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) spin_lock_init(&adapter->tcb_send_qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) spin_lock_init(&adapter->tcb_ready_qlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) spin_lock_init(&adapter->rcv_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) adapter->registry_jumbo_packet = 1514; /* 1514-9216 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) ether_addr_copy(adapter->addr, default_mac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) return adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) static void et131x_pci_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) unregister_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) netif_napi_del(&adapter->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) phy_disconnect(netdev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) mdiobus_unregister(adapter->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) mdiobus_free(adapter->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) et131x_adapter_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) iounmap(adapter->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) static void et131x_up(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) et131x_enable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) phy_start(netdev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) static void et131x_down(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) /* Save the timestamp for the TX watchdog, prevent a timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) netif_trans_update(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) phy_stop(netdev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) et131x_disable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) static int et131x_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (netif_running(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) netif_device_detach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) et131x_down(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) static int et131x_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) struct pci_dev *pdev = to_pci_dev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) struct net_device *netdev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) if (netif_running(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) et131x_up(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) netif_device_attach(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) static SIMPLE_DEV_PM_OPS(et131x_pm_ops, et131x_suspend, et131x_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) static irqreturn_t et131x_isr(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) bool handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) bool enable_interrupts = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) struct net_device *netdev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) struct address_map __iomem *iomem = adapter->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) struct rx_ring *rx_ring = &adapter->rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) if (!netif_device_present(netdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) enable_interrupts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) et131x_disable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) status = readl(&adapter->regs->global.int_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) status &= ~INT_MASK_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) status &= ~INT_MASK_ENABLE_NO_FLOW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) /* Make sure this is our interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) if (!status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) et131x_enable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) /* This is our interrupt, so process accordingly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) if (status & ET_INTR_WATCHDOG) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) struct tcb *tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) if (tcb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) if (++tcb->stale > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) status |= ET_INTR_TXDMA_ISR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) if (rx_ring->unfinished_receives)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) status |= ET_INTR_RXDMA_XFR_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) else if (tcb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) writel(0, &adapter->regs->global.watchdog_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) status &= ~ET_INTR_WATCHDOG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) if (status & (ET_INTR_RXDMA_XFR_DONE | ET_INTR_TXDMA_ISR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) enable_interrupts = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) napi_schedule(&adapter->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) status &= ~(ET_INTR_TXDMA_ISR | ET_INTR_RXDMA_XFR_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) if (status & ET_INTR_TXDMA_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) /* Following read also clears the register (COR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) u32 txdma_err = readl(&iomem->txdma.tx_dma_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) "TXDMA_ERR interrupt, error = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) txdma_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) if (status & (ET_INTR_RXDMA_FB_R0_LOW | ET_INTR_RXDMA_FB_R1_LOW)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) /* This indicates the number of unused buffers in RXDMA free
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) * buffer ring 0 is <= the limit you programmed. Free buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) * resources need to be returned. Free buffers are consumed as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) * packets are passed from the network to the host. The host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) * becomes aware of the packets from the contents of the packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) * status ring. This ring is queried when the packet done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) * interrupt occurs. Packets are then passed to the OS. When
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) * the OS is done with the packets the resources can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) * returned to the ET1310 for re-use. This interrupt is one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) * method of returning resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) /* If the user has flow control on, then we will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) * send a pause packet, otherwise just exit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) if (adapter->flow == FLOW_TXONLY || adapter->flow == FLOW_BOTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) /* Tell the device to send a pause packet via the back
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443) * pressure register (bp req and bp xon/xoff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) if (!et1310_in_phy_coma(adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) writel(3, &iomem->txmac.bp_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) /* Handle Packet Status Ring Low Interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) if (status & ET_INTR_RXDMA_STAT_LOW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) /* Same idea as with the two Free Buffer Rings. Packets going
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) * from the network to the host each consume a free buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) * resource and a packet status resource. These resources are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) * passed to the OS. When the OS is done with the resources,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) * they need to be returned to the ET1310. This is one method
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) * of returning the resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) if (status & ET_INTR_RXDMA_ERR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) /* The rxdma_error interrupt is sent when a time-out on a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) * request issued by the JAGCore has occurred or a completion is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) * returned with an un-successful status. In both cases the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) * request is considered complete. The JAGCore will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) * automatically re-try the request in question. Normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) * information on events like these are sent to the host using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) * the "Advanced Error Reporting" capability. This interrupt is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) * another way of getting similar information. The only thing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) * required is to clear the interrupt by reading the ISR in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) * global resources. The JAGCore will do a re-try on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) * request. Normally you should never see this interrupt. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) * you start to see this interrupt occurring frequently then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) * something bad has occurred. A reset might be the thing to do.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) /* TRAP();*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) dev_warn(&adapter->pdev->dev, "RxDMA_ERR interrupt, error %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) readl(&iomem->txmac.tx_test));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) /* Handle the Wake on LAN Event */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) if (status & ET_INTR_WOL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) /* This is a secondary interrupt for wake on LAN. The driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) * should never see this, if it does, something serious is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) * wrong.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) dev_err(&adapter->pdev->dev, "WAKE_ON_LAN interrupt\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) if (status & ET_INTR_TXMAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492) u32 err = readl(&iomem->txmac.err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) /* When any of the errors occur and TXMAC generates an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) * interrupt to report these errors, it usually means that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) * TXMAC has detected an error in the data stream retrieved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) * from the on-chip Tx Q. All of these errors are catastrophic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) * and TXMAC won't be able to recover data when these errors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) * occur. In a nutshell, the whole Tx path will have to be reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500) * and re-configured afterwards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) dev_warn(&adapter->pdev->dev, "TXMAC interrupt, error 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) /* If we are debugging, we want to see this error, otherwise we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) * just want the device to be reset and continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) if (status & ET_INTR_RXMAC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) /* These interrupts are catastrophic to the device, what we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) * to do is disable the interrupts and set the flag to cause us
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) * to reset so we can solve this issue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) "RXMAC interrupt, error 0x%08x. Requesting reset\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) readl(&iomem->rxmac.err_reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) "Enable 0x%08x, Diag 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) readl(&iomem->rxmac.ctrl),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) readl(&iomem->rxmac.rxq_diag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) /* If we are debugging, we want to see this error, otherwise we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) * just want the device to be reset and continue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) if (status & ET_INTR_MAC_STAT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) /* This means at least one of the un-masked counters in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) * MAC_STAT block has rolled over. Use this to maintain the top,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) * software managed bits of the counter(s).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) et1310_handle_macstat_interrupt(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) if (status & ET_INTR_SLV_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) /* This means a timeout has occurred on a read or write request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) * to one of the JAGCore registers. The Global Resources block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) * has terminated the request and on a read request, returned a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) * "fake" value. The most likely reasons are: Bad Address or the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) * addressed module is in a power-down state and can't respond.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) if (enable_interrupts)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) et131x_enable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) static int et131x_poll(struct napi_struct *napi, int budget)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) struct et131x_adapter *adapter =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) container_of(napi, struct et131x_adapter, napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) int work_done = et131x_handle_recv_pkts(adapter, budget);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) et131x_handle_send_pkts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) if (work_done < budget) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) napi_complete_done(&adapter->napi, work_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563) et131x_enable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) return work_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569) /* et131x_stats - Return the current device statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) static struct net_device_stats *et131x_stats(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) struct net_device_stats *stats = &adapter->netdev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574) struct ce_stats *devstat = &adapter->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) stats->rx_errors = devstat->rx_length_errs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) devstat->rx_align_errs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) devstat->rx_crc_errs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579) devstat->rx_code_violations +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) devstat->rx_other_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) stats->tx_errors = devstat->tx_max_pkt_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) stats->multicast = devstat->multicast_pkts_rcvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) stats->collisions = devstat->tx_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) stats->rx_length_errors = devstat->rx_length_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) stats->rx_over_errors = devstat->rx_overflows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) stats->rx_crc_errors = devstat->rx_crc_errs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588) stats->rx_dropped = devstat->rcvd_pkts_dropped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) /* NOTE: Not used, can't find analogous statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) /* stats->rx_frame_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592) /* stats->rx_fifo_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) /* stats->rx_missed_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) /* stats->tx_aborted_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) /* stats->tx_carrier_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597) /* stats->tx_fifo_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) /* stats->tx_heartbeat_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) /* stats->tx_window_errors = devstat->; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) return stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603) static int et131x_open(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606) struct pci_dev *pdev = adapter->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) unsigned int irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) int result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) /* Start the timer to track NIC errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) timer_setup(&adapter->error_timer, et131x_error_timer_handler, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) adapter->error_timer.expires = jiffies +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613) msecs_to_jiffies(TX_ERROR_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) add_timer(&adapter->error_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) result = request_irq(irq, et131x_isr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617) IRQF_SHARED, netdev->name, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) if (result) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) dev_err(&pdev->dev, "could not register IRQ %d\n", irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) adapter->flags |= FMP_ADAPTER_INTERRUPT_IN_USE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) napi_enable(&adapter->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) et131x_up(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) static int et131x_close(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) et131x_down(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) napi_disable(&adapter->napi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) adapter->flags &= ~FMP_ADAPTER_INTERRUPT_IN_USE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) free_irq(adapter->pdev->irq, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) /* Stop the error timer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) return del_timer_sync(&adapter->error_timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) /* et131x_set_packet_filter - Configures the Rx Packet filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647) static int et131x_set_packet_filter(struct et131x_adapter *adapter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) int filter = adapter->packet_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) u32 pf_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) ctrl = readl(&adapter->regs->rxmac.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) pf_ctrl = readl(&adapter->regs->rxmac.pf_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) /* Default to disabled packet filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) ctrl |= 0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) /* Set us to be in promiscuous mode so we receive everything, this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) * is also true when we get a packet filter of 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) if ((filter & ET131X_PACKET_TYPE_PROMISCUOUS) || filter == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663) pf_ctrl &= ~7; /* Clear filter bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) /* Set us up with Multicast packet filtering. Three cases are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) * possible - (1) we have a multi-cast list, (2) we receive ALL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) * multicast entries or (3) we receive none.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669) if (filter & ET131X_PACKET_TYPE_ALL_MULTICAST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) pf_ctrl &= ~2; /* Multicast filter bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) et1310_setup_device_for_multicast(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) pf_ctrl |= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) ctrl &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677) /* Set us up with Unicast packet filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) if (filter & ET131X_PACKET_TYPE_DIRECTED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) et1310_setup_device_for_unicast(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) pf_ctrl |= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) ctrl &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) /* Set us up with Broadcast packet filtering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) if (filter & ET131X_PACKET_TYPE_BROADCAST) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686) pf_ctrl |= 1; /* Broadcast filter bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) ctrl &= ~0x04;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) pf_ctrl &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) /* Setup the receive mac configuration registers - Packet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) * Filter control + the enable / disable for packet filter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) * in the control reg.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696) writel(pf_ctrl, &adapter->regs->rxmac.pf_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) writel(ctrl, &adapter->regs->rxmac.ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702) static void et131x_multicast(struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) int packet_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) struct netdev_hw_addr *ha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) /* Before we modify the platform-independent filter flags, store them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) * locally. This allows us to determine if anything's changed and if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) * we even need to bother the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) packet_filter = adapter->packet_filter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) /* Clear the 'multicast' flag locally; because we only have a single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) * flag to check multicast, and multiple multicast addresses can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717) * set, this is the easiest way to determine if more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) * multicast address is being set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) /* Check the net_device flags and set the device independent flags
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) * accordingly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) if (netdev->flags & IFF_PROMISC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) adapter->packet_filter |= ET131X_PACKET_TYPE_PROMISCUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) adapter->packet_filter &= ~ET131X_PACKET_TYPE_PROMISCUOUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) if ((netdev->flags & IFF_ALLMULTI) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) (netdev_mc_count(netdev) > NIC_MAX_MCAST_LIST))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732) adapter->packet_filter |= ET131X_PACKET_TYPE_ALL_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734) if (netdev_mc_count(netdev) < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) adapter->packet_filter &= ~ET131X_PACKET_TYPE_ALL_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) adapter->packet_filter &= ~ET131X_PACKET_TYPE_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) adapter->packet_filter |= ET131X_PACKET_TYPE_MULTICAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741) /* Set values in the private adapter struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) netdev_for_each_mc_addr(ha, netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) if (i == NIC_MAX_MCAST_LIST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) ether_addr_copy(adapter->multicast_list[i++], ha->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) adapter->multicast_addr_count = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750) /* Are the new flags different from the previous ones? If not, then no
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) * action is required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753) * NOTE - This block will always update the multicast_list with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) * hardware, even if the addresses aren't the same.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) if (packet_filter != adapter->packet_filter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757) et131x_set_packet_filter(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) static netdev_tx_t et131x_tx(struct sk_buff *skb, struct net_device *netdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) /* stop the queue if it's getting full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) if (tx_ring->used >= NUM_TCB - 1 && !netif_queue_stopped(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) netif_stop_queue(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) /* Save the timestamp for the TX timeout watchdog */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770) netif_trans_update(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) /* TCB is not available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) if (tx_ring->used >= NUM_TCB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) goto drop_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) if ((adapter->flags & FMP_ADAPTER_FAIL_SEND_MASK) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) !netif_carrier_ok(netdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) goto drop_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780) if (send_packet(skb, adapter))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) goto drop_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) drop_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) adapter->netdev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) /* et131x_tx_timeout - Timeout handler
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) * The handler called when a Tx request times out. The timeout period is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) * specified by the 'tx_timeo" element in the net_device structure (see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795) * et131x_alloc_device() to see how this value is set).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) static void et131x_tx_timeout(struct net_device *netdev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) struct tx_ring *tx_ring = &adapter->tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801) struct tcb *tcb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) /* If the device is closed, ignore the timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805) if (!(adapter->flags & FMP_ADAPTER_INTERRUPT_IN_USE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) /* Any nonrecoverable hardware error?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) * Checks adapter->flags for any failure in phy reading
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811) if (adapter->flags & FMP_ADAPTER_NON_RECOVER_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) /* Hardware failure? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) if (adapter->flags & FMP_ADAPTER_HARDWARE_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) dev_err(&adapter->pdev->dev, "hardware error - reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) /* Is send stuck? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) spin_lock_irqsave(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822) tcb = tx_ring->send_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) spin_unlock_irqrestore(&adapter->tcb_send_qlock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) if (tcb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) tcb->count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828) if (tcb->count > NIC_SEND_HANG_THRESHOLD) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830) "Send stuck - reset. tcb->WrIndex %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) tcb->index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) adapter->netdev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) /* perform reset of tx/rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836) et131x_disable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) et131x_enable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) static int et131x_change_mtu(struct net_device *netdev, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) int result = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) struct et131x_adapter *adapter = netdev_priv(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) et131x_disable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) netdev->mtu = new_mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) et131x_adapter_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) /* Set the config parameter for Jumbo Packet support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) adapter->registry_jumbo_packet = new_mtu + 14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) et131x_soft_reset(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) result = et131x_adapter_memory_alloc(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) if (result != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859) dev_warn(&adapter->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) "Change MTU failed; couldn't re-alloc DMA memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) et131x_init_send(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865) et131x_hwaddr_init(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) ether_addr_copy(netdev->dev_addr, adapter->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) /* Init the device with the new settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) et131x_adapter_setup(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870) et131x_enable_txrx(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) return result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875) static const struct net_device_ops et131x_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) .ndo_open = et131x_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) .ndo_stop = et131x_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878) .ndo_start_xmit = et131x_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) .ndo_set_rx_mode = et131x_multicast,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) .ndo_tx_timeout = et131x_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) .ndo_change_mtu = et131x_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) .ndo_get_stats = et131x_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) .ndo_do_ioctl = phy_do_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888) static int et131x_pci_setup(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) struct et131x_adapter *adapter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) dev_err(&pdev->dev, "pci_enable_device() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) /* Perform some basic PCI checks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) dev_err(&pdev->dev, "Can't find PCI device's base address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904) rc = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) rc = pci_request_regions(pdev, DRIVER_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) dev_err(&pdev->dev, "Can't get PCI resources\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) goto err_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) /* Check the DMA addressing support of this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) dev_err(&pdev->dev, "No usable DMA addressing method\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) rc = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) goto err_release_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924) netdev = alloc_etherdev(sizeof(struct et131x_adapter));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) if (!netdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) dev_err(&pdev->dev, "Couldn't alloc netdev struct\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) goto err_release_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) netdev->watchdog_timeo = ET131X_TX_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) netdev->netdev_ops = &et131x_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) netdev->min_mtu = ET131X_MIN_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) netdev->max_mtu = ET131X_MAX_MTU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) SET_NETDEV_DEV(netdev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) netdev->ethtool_ops = &et131x_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) adapter = et131x_adapter_init(netdev, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) rc = et131x_pci_init(adapter, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) goto err_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) /* Map the bus-relative registers to system virtual memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) adapter->regs = pci_ioremap_bar(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) if (!adapter->regs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) dev_err(&pdev->dev, "Cannot map device registers\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) goto err_free_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) /* If Phy COMA mode was enabled when we went down, disable it here. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) writel(ET_PMCSR_INIT, &adapter->regs->global.pm_csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) et131x_soft_reset(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) et131x_disable_interrupts(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) rc = et131x_adapter_memory_alloc(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961) dev_err(&pdev->dev, "Could not alloc adapter memory (DMA)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) et131x_init_send(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) netif_napi_add(netdev, &adapter->napi, et131x_poll, 64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) ether_addr_copy(netdev->dev_addr, adapter->addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) adapter->mii_bus = mdiobus_alloc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974) if (!adapter->mii_bus) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) dev_err(&pdev->dev, "Alloc of mii_bus struct failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) goto err_mem_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) adapter->mii_bus->name = "et131x_eth_mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) snprintf(adapter->mii_bus->id, MII_BUS_ID_SIZE, "%x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) (adapter->pdev->bus->number << 8) | adapter->pdev->devfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) adapter->mii_bus->priv = netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) adapter->mii_bus->read = et131x_mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) adapter->mii_bus->write = et131x_mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) rc = mdiobus_register(adapter->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) dev_err(&pdev->dev, "failed to register MII bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989) goto err_mdio_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) rc = et131x_mii_probe(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994) dev_err(&pdev->dev, "failed to probe MII bus\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) goto err_mdio_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) et131x_adapter_setup(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) /* Init variable for counting how long we do not have link status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) adapter->boot_coma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) et1310_disable_phy_coma(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) /* We can enable interrupts now
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) * NOTE - Because registration of interrupt handler is done in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007) * device's open(), defer enabling device interrupts to that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) * point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) rc = register_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) if (rc < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013) dev_err(&pdev->dev, "register_netdev() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) goto err_phy_disconnect;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) /* Register the net_device struct with the PCI subsystem. Save a copy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) * of the PCI config space for this device now that the device has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019) * been initialized, just in case it needs to be quickly restored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) pci_set_drvdata(pdev, netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025) err_phy_disconnect:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) phy_disconnect(netdev->phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) err_mdio_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) mdiobus_unregister(adapter->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) err_mdio_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) mdiobus_free(adapter->mii_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) err_mem_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) et131x_adapter_memory_free(adapter);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) iounmap(adapter->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) err_free_dev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) pci_dev_put(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) free_netdev(netdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038) err_release_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) err_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) static const struct pci_device_id et131x_pci_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_GIG), 0UL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) { PCI_VDEVICE(ATT, ET131X_PCI_DEVICE_ID_FAST), 0UL},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) { 0,}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) MODULE_DEVICE_TABLE(pci, et131x_pci_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) static struct pci_driver et131x_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) .id_table = et131x_pci_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) .probe = et131x_pci_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) .remove = et131x_pci_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) .driver.pm = &et131x_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060) module_pci_driver(et131x_driver);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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