^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef GRETH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define GRETH_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /* Register bits and masks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define GRETH_RESET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define GRETH_MII_BUSY 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define GRETH_MII_NVALID 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define GRETH_CTRL_FD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define GRETH_CTRL_PR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define GRETH_CTRL_SP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define GRETH_CTRL_GB 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define GRETH_CTRL_PSTATIEN 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GRETH_CTRL_MCEN 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GRETH_CTRL_DISDUPLEX 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define GRETH_STATUS_PHYSTAT 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define GRETH_BD_EN 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define GRETH_BD_WR 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define GRETH_BD_IE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define GRETH_BD_LEN 0x7FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define GRETH_TXEN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define GRETH_INT_TE 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define GRETH_INT_TX 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define GRETH_TXI 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define GRETH_TXBD_STATUS 0x0001C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GRETH_TXBD_MORE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define GRETH_TXBD_IPCS 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define GRETH_TXBD_TCPCS 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define GRETH_TXBD_UDPCS 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define GRETH_TXBD_CSALL (GRETH_TXBD_IPCS | GRETH_TXBD_TCPCS | GRETH_TXBD_UDPCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GRETH_TXBD_ERR_LC 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GRETH_TXBD_ERR_UE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GRETH_TXBD_ERR_AL 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define GRETH_INT_RE 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GRETH_INT_RX 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define GRETH_RXEN 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define GRETH_RXI 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define GRETH_RXBD_STATUS 0xFFFFC000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define GRETH_RXBD_ERR_AE 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define GRETH_RXBD_ERR_FT 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define GRETH_RXBD_ERR_CRC 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define GRETH_RXBD_ERR_OE 0x20000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define GRETH_RXBD_ERR_LE 0x40000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define GRETH_RXBD_IP 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define GRETH_RXBD_IP_CSERR 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GRETH_RXBD_UDP 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GRETH_RXBD_UDP_CSERR 0x400000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GRETH_RXBD_TCP 0x800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GRETH_RXBD_TCP_CSERR 0x1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GRETH_RXBD_IP_FRAG 0x2000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GRETH_RXBD_MCAST 0x4000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Descriptor parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GRETH_TXBD_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GRETH_TX_BUF_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GRETH_RXBD_NUM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GRETH_RX_BUF_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Buffers per page */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GRETH_RX_BUF_PPGAE (PAGE_SIZE/GRETH_RX_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GRETH_TX_BUF_PPGAE (PAGE_SIZE/GRETH_TX_BUF_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* How many pages are needed for buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GRETH_RX_BUF_PAGE_NUM (GRETH_RXBD_NUM/GRETH_RX_BUF_PPGAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GRETH_TX_BUF_PAGE_NUM (GRETH_TXBD_NUM/GRETH_TX_BUF_PPGAE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Buffer size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * Gbit MAC uses tagged maximum frame size which is 1518 excluding CRC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Set to 1520 to make all buffers word aligned for non-gbit MAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MAX_FRAME_SIZE 1520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* GRETH APB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct greth_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 esa_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 esa_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 tx_desc_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 rx_desc_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 edclip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 hash_msb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 hash_lsb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* GRETH buffer descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct greth_bd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct greth_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct sk_buff *rx_skbuff[GRETH_RXBD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) struct sk_buff *tx_skbuff[GRETH_TXBD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned char *tx_bufs[GRETH_TXBD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned char *rx_bufs[GRETH_RXBD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u16 tx_bufs_length[GRETH_TXBD_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u16 tx_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u16 tx_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u16 tx_free; /* only used on 10/100Mbit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u16 rx_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct greth_regs *regs; /* Address of controller registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct greth_bd *rx_bd_base; /* Address of Rx BDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct greth_bd *tx_bd_base; /* Address of Tx BDs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dma_addr_t rx_bd_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dma_addr_t tx_bd_base_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct device *dev; /* Pointer to platform_device->dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct net_device *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct napi_struct napi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) spinlock_t devlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct mii_bus *mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 msg_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u8 phyaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u8 multicast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) u8 gbit_mac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u8 mdio_int_en;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 edcl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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