^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Support for ColdFire CPU based boards using a NS8390 Ethernet device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Derived from the many other 8390 drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * (C) Copyright 2012, Greg Ungerer <gerg@uclinux.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * This file is subject to the terms and conditions of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * License. See the file COPYING in the main directory of the Linux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * distribution for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <asm/mcf8390.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "mcf8390.c: (15-06-2012) Greg Ungerer <gerg@uclinux.org>";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define NE_CMD 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define NE_DATAPORT 0x10 /* NatSemi-defined port window offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define NE_RESET 0x1f /* Issue a read to reset ,a write to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NE_EN0_ISR 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define NE_EN0_DCFG 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define NE_EN0_RSARLO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define NE_EN0_RSARHI 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define NE_EN0_RCNTLO 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define NE_EN0_RXCR 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define NE_EN0_TXCR 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define NE_EN0_RCNTHI 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define NE_EN0_IMR 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define NESM_START_PG 0x40 /* First page of TX buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define NESM_STOP_PG 0x80 /* Last page +1 of RX ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifdef NE2000_ODDOFFSET
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * A lot of the ColdFire boards use a separate address region for odd offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * register addresses. The following functions convert and map as required.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * Note that the data port accesses are treated a little differently, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * always accessed via the insX/outsX functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) static inline u32 NE_PTR(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) if (addr & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) return addr - 1 + NE2000_ODDOFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) static inline u32 NE_DATA_PTR(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) void ei_outb(u32 val, u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) NE2000_BYTE *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) rp = (NE2000_BYTE *) NE_PTR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *rp = RSWAP(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ei_inb ei_inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u8 ei_inb(u32 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) NE2000_BYTE *rp, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) rp = (NE2000_BYTE *) NE_PTR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) val = *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) return (u8) (RSWAP(val) & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) void ei_insb(u32 addr, void *vbuf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) NE2000_BYTE *rp, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) buf = (u8 *) vbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) rp = (NE2000_BYTE *) NE_DATA_PTR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) for (; (len > 0); len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) val = *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) *buf++ = RSWAP(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) void ei_insw(u32 addr, void *vbuf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) volatile u16 *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u16 w, *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) buf = (u16 *) vbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) rp = (volatile u16 *) NE_DATA_PTR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) for (; (len > 0); len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) w = *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *buf++ = BSWAP(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) void ei_outsb(u32 addr, const void *vbuf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) NE2000_BYTE *rp, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u8 *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) buf = (u8 *) vbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) rp = (NE2000_BYTE *) NE_DATA_PTR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) for (; (len > 0); len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) val = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) *rp = RSWAP(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void ei_outsw(u32 addr, const void *vbuf, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) volatile u16 *rp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u16 w, *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) buf = (u16 *) vbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) rp = (volatile u16 *) NE_DATA_PTR(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) for (; (len > 0); len--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) w = *buf++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) *rp = BSWAP(w);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #else /* !NE2000_ODDOFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ei_inb inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ei_outb outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ei_insb insb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ei_insw insw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ei_outsb outsb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ei_outsw outsw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #endif /* !NE2000_ODDOFFSET */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ei_inb_p ei_inb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ei_outb_p ei_outb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #include "lib8390.c"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * Hard reset the card. This used to pause for the same period that a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * 8390 reset command required, but that shouldn't be necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void mcf8390_reset_8390(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long reset_start_time = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 addr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct ei_device *ei_local = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) netif_dbg(ei_local, hw, dev, "resetting the 8390 t=%ld...\n", jiffies);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) ei_outb(ei_inb(addr + NE_RESET), addr + NE_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) ei_status.txing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) ei_status.dmaing = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* This check _should_not_ be necessary, omit eventually. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) while ((ei_inb(addr + NE_EN0_ISR) & ENISR_RESET) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (time_after(jiffies, reset_start_time + 2 * HZ / 100)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) netdev_warn(dev, "%s: did not complete\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ei_outb(ENISR_RESET, addr + NE_EN0_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * This *shouldn't* happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * If it does, it's the last thing you'll see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) static void mcf8390_dmaing_err(const char *func, struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct ei_device *ei_local)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) netdev_err(dev, "%s: DMAing conflict [DMAstat:%d][irqlock:%d]\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) func, ei_local->dmaing, ei_local->irqlock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * Grab the 8390 specific header. Similar to the block_input routine, but
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * we don't need to be concerned with ring wrap as the header will be at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * the start of a page, so we optimize accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static void mcf8390_get_8390_hdr(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct e8390_pkt_hdr *hdr, int ring_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct ei_device *ei_local = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 addr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (ei_local->dmaing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) mcf8390_dmaing_err(__func__, dev, ei_local);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ei_local->dmaing |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ei_outb(E8390_NODMA + E8390_PAGE0 + E8390_START, addr + NE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ei_outb(ENISR_RDC, addr + NE_EN0_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ei_outb(sizeof(struct e8390_pkt_hdr), addr + NE_EN0_RCNTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ei_outb(0, addr + NE_EN0_RCNTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ei_outb(0, addr + NE_EN0_RSARLO); /* On page boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) ei_outb(ring_page, addr + NE_EN0_RSARHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ei_outb(E8390_RREAD + E8390_START, addr + NE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ei_insw(addr + NE_DATAPORT, hdr, sizeof(struct e8390_pkt_hdr) >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) outb(ENISR_RDC, addr + NE_EN0_ISR); /* Ack intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ei_local->dmaing &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) hdr->count = cpu_to_le16(hdr->count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * Block input and output, similar to the Crynwr packet driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * If you are porting to a new ethercard, look at the packet driver source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * for hints. The NEx000 doesn't share the on-board packet memory --
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * you have to put the packet out through the "remote DMA" dataport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * using z_writeb.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void mcf8390_block_input(struct net_device *dev, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct sk_buff *skb, int ring_offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) struct ei_device *ei_local = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 addr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) char *buf = skb->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (ei_local->dmaing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mcf8390_dmaing_err(__func__, dev, ei_local);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) ei_local->dmaing |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) ei_outb(E8390_NODMA + E8390_PAGE0 + E8390_START, addr + NE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) ei_outb(ENISR_RDC, addr + NE_EN0_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) ei_outb(count & 0xff, addr + NE_EN0_RCNTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ei_outb(count >> 8, addr + NE_EN0_RCNTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ei_outb(ring_offset & 0xff, addr + NE_EN0_RSARLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ei_outb(ring_offset >> 8, addr + NE_EN0_RSARHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) ei_outb(E8390_RREAD + E8390_START, addr + NE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) ei_insw(addr + NE_DATAPORT, buf, count >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (count & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) buf[count - 1] = ei_inb(addr + NE_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) ei_outb(ENISR_RDC, addr + NE_EN0_ISR); /* Ack intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) ei_local->dmaing &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) static void mcf8390_block_output(struct net_device *dev, int count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) const unsigned char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) const int start_page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) struct ei_device *ei_local = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) u32 addr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) unsigned long dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Make sure we transfer all bytes if 16bit IO writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) if (count & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) if (ei_local->dmaing) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mcf8390_dmaing_err(__func__, dev, ei_local);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) ei_local->dmaing |= 0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* We should already be in page 0, but to be safe... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ei_outb(E8390_PAGE0 + E8390_START + E8390_NODMA, addr + NE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) ei_outb(ENISR_RDC, addr + NE_EN0_ISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* Now the normal output. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ei_outb(count & 0xff, addr + NE_EN0_RCNTLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ei_outb(count >> 8, addr + NE_EN0_RCNTHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ei_outb(0x00, addr + NE_EN0_RSARLO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ei_outb(start_page, addr + NE_EN0_RSARHI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) ei_outb(E8390_RWRITE + E8390_START, addr + NE_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ei_outsw(addr + NE_DATAPORT, buf, count >> 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_start = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) while ((ei_inb(addr + NE_EN0_ISR) & ENISR_RDC) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (time_after(jiffies, dma_start + 2 * HZ / 100)) { /* 20ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) netdev_warn(dev, "timeout waiting for Tx RDC\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mcf8390_reset_8390(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) __NS8390_init(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) ei_outb(ENISR_RDC, addr + NE_EN0_ISR); /* Ack intr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ei_local->dmaing &= ~0x01;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static const struct net_device_ops mcf8390_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .ndo_open = __ei_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .ndo_stop = __ei_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .ndo_start_xmit = __ei_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .ndo_tx_timeout = __ei_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .ndo_get_stats = __ei_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .ndo_set_rx_mode = __ei_set_multicast_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .ndo_poll_controller = __ei_poll,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static int mcf8390_init(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static u32 offsets[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 0x08, 0x09, 0x0a, 0x0b, 0x0c, 0x0d, 0x0e, 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct ei_device *ei_local = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned char SA_prom[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 addr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int start_page, stop_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) mcf8390_reset_8390(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * Read the 16 bytes of station address PROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * We must first initialize registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * similar to NS8390_init(eifdev, 0).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * We can't reliably read the SAPROM address without this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * (I learned the hard way!).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static const struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } program_seq[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {E8390_NODMA + E8390_PAGE0 + E8390_STOP, NE_CMD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Select page 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {0x48, NE_EN0_DCFG}, /* 0x48: Set byte-wide access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {0x00, NE_EN0_RCNTLO}, /* Clear the count regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {0x00, NE_EN0_RCNTHI},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) {0x00, NE_EN0_IMR}, /* Mask completion irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {0xFF, NE_EN0_ISR},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {E8390_RXOFF, NE_EN0_RXCR}, /* 0x20 Set to monitor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {E8390_TXOFF, NE_EN0_TXCR}, /* 0x02 and loopback mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {32, NE_EN0_RCNTLO},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {0x00, NE_EN0_RCNTHI},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {0x00, NE_EN0_RSARLO}, /* DMA starting at 0x0000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) {0x00, NE_EN0_RSARHI},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {E8390_RREAD + E8390_START, NE_CMD},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) for (i = 0; i < ARRAY_SIZE(program_seq); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) ei_outb(program_seq[i].value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) addr + program_seq[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) for (i = 0; i < 16; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) SA_prom[i] = ei_inb(addr + NE_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ei_inb(addr + NE_DATAPORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* We must set the 8390 for word mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ei_outb(0x49, addr + NE_EN0_DCFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) start_page = NESM_START_PG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) stop_page = NESM_STOP_PG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Install the Interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) ret = request_irq(dev->irq, __ei_interrupt, 0, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) for (i = 0; i < ETH_ALEN; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) dev->dev_addr[i] = SA_prom[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) netdev_dbg(dev, "Found ethernet address: %pM\n", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) ei_local->name = "mcf8390";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) ei_local->tx_start_page = start_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) ei_local->stop_page = stop_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) ei_local->word16 = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) ei_local->rx_start_page = start_page + TX_PAGES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) ei_local->reset_8390 = mcf8390_reset_8390;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) ei_local->block_input = mcf8390_block_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ei_local->block_output = mcf8390_block_output;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) ei_local->get_8390_hdr = mcf8390_get_8390_hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) ei_local->reg_offset = offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dev->netdev_ops = &mcf8390_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __NS8390_init(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) ret = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) netdev_info(dev, "addr=0x%08x irq=%d, Ethernet Address %pM\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) addr, dev->irq, dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) static int mcf8390_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) resource_size_t msize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) int ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_err(&pdev->dev, "no IRQ specified?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (mem == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_err(&pdev->dev, "no memory address specified?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) msize = resource_size(mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!request_mem_region(mem->start, msize, pdev->name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev = ____alloc_ei_netdev(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (dev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) release_mem_region(mem->start, msize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) SET_NETDEV_DEV(dev, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) dev->base_addr = mem->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) ret = mcf8390_init(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) release_mem_region(mem->start, msize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int mcf8390_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) struct net_device *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (mem)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) release_mem_region(mem->start, resource_size(mem));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static struct platform_driver mcf8390_drv = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .name = "mcf8390",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .probe = mcf8390_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .remove = mcf8390_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) module_platform_driver(mcf8390_drv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) MODULE_DESCRIPTION("MCF8390 ColdFire NS8390 driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) MODULE_AUTHOR("Greg Ungerer <gerg@uclinux.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) MODULE_ALIAS("platform:mcf8390");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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