^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* EtherLinkXL.c: A 3Com EtherLink PCI III/XL ethernet driver for linux. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Written 1996-1999 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) This software may be used and distributed according to the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) of the GNU General Public License, incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) This driver is for the 3Com "Vortex" and "Boomerang" series ethercards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Members of the series include Fast EtherLink 3c590/3c592/3c595/3c597
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) and the EtherLink XL 3c900 and 3c905 cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Problem reports and questions should be directed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) vortex@scyld.com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The author may be reached as becker@scyld.com, or C/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Scyld Computing Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 410 Severn Ave., Suite 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Annapolis MD 21403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * FIXME: This driver _could_ support MTU changing, but doesn't. See Don's hamachi.c implementation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * as well as other drivers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * NOTE: If you make 'vortex_debug' a constant (#define vortex_debug 0) the driver shrinks by 2k
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * due to dead code elimination. There will be some performance benefits from this due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * elimination of all the tests and reduced cache footprint.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRV_NAME "3c59x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* A few values that may be tweaked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Keep the ring sizes a power of two for efficiency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TX_RING_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define RX_RING_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* "Knobs" that adjust features and parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Setting to > 1512 effectively disables this feature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #ifndef __arm__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int rx_copybreak = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* ARM systems perform better by disregarding the bus-master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) transfer capability of these cards. -- rmk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) static int rx_copybreak = 1513;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) static const int mtu = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) static int max_interrupt_work = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* Tx timeout interval (millisecs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int watchdog = 5000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Allow aggregation of Tx interrupts. Saves CPU load at the cost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * of possible Tx stalls if the system is blocking interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * somewhere else. Undefine this to disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define tx_interrupt_mitigation 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Put out somewhat more debugging messages. (0: no msg, 1 minimal .. 6). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define vortex_debug debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #ifdef VORTEX_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static int vortex_debug = VORTEX_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int vortex_debug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include <linux/mii.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #include <linux/eisa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #include <asm/irq.h> /* For nr_irqs only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Kernel compatibility defines, some common to David Hinds' PCMCIA package.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) This is only in the support-all-kernels source code. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define RUN_AT(x) (jiffies + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static const char version[] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) DRV_NAME ": Donald Becker and others.\n";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Operational parameter that usually are not changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* The Vortex size is twice that of the original EtherLinkIII series: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) runtime register window, window 1, is now always mapped in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) The Boomerang size is twice as large as the Vortex -- it has additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bus master control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VORTEX_TOTAL_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BOOMERANG_TOTAL_SIZE 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Set iff a MII transceiver on any interface requires mdio preamble.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) This only set with the original DP83840 on older 3c905 boards, so the extra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) code size of a per-interface flag is not worthwhile. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) static char mii_preamble_required;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PFX DRV_NAME ": "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) Theory of Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) I. Board Compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) This device driver is designed for the 3Com FastEtherLink and FastEtherLink
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) XL, 3Com's PCI to 10/100baseT adapters. It also works with the 10Mbs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) versions of the FastEtherLink cards. The supported product IDs are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 3c590, 3c592, 3c595, 3c597, 3c900, 3c905
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) The related ISA 3c515 is supported with a separate driver, 3c515.c, included
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) with the kernel source or available from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) cesdis.gsfc.nasa.gov:/pub/linux/drivers/3c515.html
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) II. Board-specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) PCI bus devices are configured by the system at boot time, so no jumpers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) need to be set on the board. The system BIOS should be set to assign the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) PCI INTA signal to an otherwise unused system IRQ line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) The EEPROM settings for media type and forced-full-duplex are observed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) The EEPROM media type should be left at the default "autoselect" unless using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 10base2 or AUI connections which cannot be reliably detected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) III. Driver operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) The 3c59x series use an interface that's very similar to the previous 3c5x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) series. The primary interface is two programmed-I/O FIFOs, with an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) alternate single-contiguous-region bus-master transfer (see next).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) The 3c900 "Boomerang" series uses a full-bus-master interface with separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) DEC Tulip and Intel Speedo3. The first chip version retains a compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) programmed-I/O interface that has been removed in 'B' and subsequent board
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) revisions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) One extension that is advertised in a very large font is that the adapters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) are capable of being bus masters. On the Vortex chip this capability was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) only for a single contiguous region making it far less useful than the full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bus master capability. There is a significant performance impact of taking
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) an extra interrupt or polling for the completion of each transfer, as well
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) as difficulty sharing the single transfer engine between the transmit and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) receive threads. Using DMA transfers is a win only with large blocks or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) with the flawed versions of the Intel Orion motherboard PCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) The Boomerang chip's full-bus-master interface is useful, and has the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) currently-unused advantages over other similar chips that queued transmit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) packets may be reordered and receive buffer groups are associated with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) single frame.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) With full-bus-master support, this driver uses a "RX_COPYBREAK" scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Rather than a fixed intermediate receive buffer, this scheme allocates
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) full-sized skbuffs as receive buffers. The value RX_COPYBREAK is used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) the copying breakpoint: it is chosen to trade-off the memory wasted by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) passing the full-sized skbuff to the queue layer for all frames vs. the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) copying cost of copying a frame to a correctly-sized skbuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) IIIC. Synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) The driver runs as two independent, single-threaded flows of control. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) is the send-packet routine, which enforces single-threaded use by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dev->tbusy flag. The other thread is the interrupt handler, which is single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) threaded by the hardware and other software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) IV. Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) Thanks to Cameron Spitzer and Terry Murphy of 3Com for providing development
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 3c590, 3c595, and 3c900 boards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) The name "Vortex" is the internal 3Com project name for the PCI ASIC, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) the EISA version is called "Demon". According to Terry these names come
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) from rides at the local amusement park.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) The new chips support both ethernet (1.5K) and FDDI (4.5K) packet sizes!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) This driver only supports ethernet packets because of the skbuff allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) limit of 4K.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* This table drives the PCI probe routines. It's mostly boilerplate in all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) of the drivers, and will likely be provided by some future kernel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) enum pci_flags_bit {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) PCI_USES_MASTER=4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) EEPROM_8BIT=0x10, /* AKPM: Uses 0x230 as the base bitmaps for EEPROM reads */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) enum vortex_chips {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) CH_3C590 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) CH_3C592,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) CH_3C597,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) CH_3C595_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CH_3C595_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) CH_3C595_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) CH_3C900_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) CH_3C900_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) CH_3C900_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) CH_3C900_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) CH_3C900_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) CH_3C900B_FL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) CH_3C905_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) CH_3C905_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) CH_3C905B_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) CH_3C905B_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) CH_3C905B_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) CH_3C905B_FX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) CH_3C905C,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) CH_3C9202,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) CH_3C980,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) CH_3C9805,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) CH_3CSOHO100_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) CH_3C555,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) CH_3C556,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) CH_3C556B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) CH_3C575,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) CH_3C575_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) CH_3CCFE575,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) CH_3CCFE575CT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) CH_3CCFE656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) CH_3CCFEM656,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) CH_3CCFEM656_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) CH_3C450,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) CH_3C920,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) CH_3C982A,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) CH_3C982B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) CH_905BT4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) CH_920B_EMB_WNM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* note: this array directly indexed by above enums, and MUST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * be kept in sync with both the enums above, and the PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * table below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) static struct vortex_chip_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int drv_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) } vortex_info_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {"3c590 Vortex 10Mbps",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) PCI_USES_MASTER, IS_VORTEX, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {"3c592 EISA 10Mbps Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) PCI_USES_MASTER, IS_VORTEX, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) {"3c597 EISA Fast Demon/Vortex", /* AKPM: from Don's 3c59x_cb.c 0.49H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) PCI_USES_MASTER, IS_VORTEX, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {"3c595 Vortex 100baseTx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) PCI_USES_MASTER, IS_VORTEX, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {"3c595 Vortex 100baseT4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) PCI_USES_MASTER, IS_VORTEX, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {"3c595 Vortex 100base-MII",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) PCI_USES_MASTER, IS_VORTEX, 32, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) {"3c900 Boomerang 10baseT",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {"3c900 Boomerang 10Mbps Combo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {"3c900 Cyclone 10Mbps TPO", /* AKPM: from Don's 0.99M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {"3c900 Cyclone 10Mbps Combo",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {"3c900 Cyclone 10Mbps TPC", /* AKPM: from Don's 0.99M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {"3c900B-FL Cyclone 10base-FL",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) {"3c905 Boomerang 100baseTx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {"3c905 Boomerang 100baseT4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) {"3C905B-TX Fast Etherlink XL PCI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) {"3c905B Cyclone 100baseTx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {"3c905B Cyclone 10/100/BNC",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {"3c905B-FX Cyclone 100baseFx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) {"3c905C Tornado",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {"3c980 Cyclone",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {"3c980C Python-T",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) {"3cSOHO100-TX Hurricane",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {"3c555 Laptop Hurricane",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {"3c556 Laptop Tornado",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) {"3c556B Laptop Hurricane",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) WNO_XCVR_PWR|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {"3c575 [Megahertz] 10/100 LAN CardBus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {"3c575 Boomerang CardBus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {"3CCFE575BT Cyclone CardBus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) INVERT_LED_PWR|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {"3CCFE575CT Tornado CardBus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {"3CCFE656 Cyclone CardBus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) INVERT_LED_PWR|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {"3CCFEM656B Cyclone+Winmodem CardBus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) INVERT_LED_PWR|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {"3CXFEM656C Tornado+Winmodem CardBus", /* From pcmcia-cs-3.1.5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {"3c450 HomePNA Tornado", /* AKPM: from Don's 0.99Q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {"3c920 Tornado",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) {"3c982 Hydra Dual Port A",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {"3c982 Hydra Dual Port B",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {"3c905B-T4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {"3c920B-EMB-WNM Tornado",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {NULL,}, /* NULL terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const struct pci_device_id vortex_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) {0,} /* 0 terminated list. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Operational definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) These are not used by other compilation units and thus are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) exported in a ".h" file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) First the windows. There are eight register windows, with the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) and status registers available in each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define EL3_CMD 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define EL3_STATUS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /* The top five bits written to EL3_CMD are a command, the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 11 bits are the parameter, if applicable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) Note that 11 parameters bits was fine for ethernet, but the new chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) can handle FDDI length frames (~4500 octets) and now parameters count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 32-bit 'Dwords' rather than octets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) enum vortex_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) UpStall = 6<<11, UpUnstall = (6<<11)+1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) SetTxThreshold = 18<<11, SetTxStart = 19<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /* The SetRxFilter command accepts the following classes: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) enum RxFilter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Bits in the general status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) enum vortex_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) IntReq = 0x0040, StatsFull = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) DMAInProgress = 1<<11, /* DMA controller is still busy.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) CmdInProgress = 1<<12, /* EL3_CMD is still busy.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /* Register window 1 offsets, the window used in normal operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) On the Vortex this window is always mapped at offsets 0x10-0x1f. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) enum Window1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) enum Window0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) Wn0EepromData = 12, /* Window 0: EEPROM results register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) IntrStatus=0x0E, /* Valid in all windows. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) enum Win0_EEPROM_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* EEPROM locations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) enum eeprom_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) DriverTune=13, Checksum=15};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) enum Window2 { /* Window 2. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) Wn2_ResetOptions=12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) enum Window3 { /* Window 3: MAC/config bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define BFEXT(value, offset, bitcount) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define BFINS(lhs, rhs, offset, bitcount) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define RAM_SIZE(v) BFEXT(v, 0, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define RAM_WIDTH(v) BFEXT(v, 3, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define RAM_SPEED(v) BFEXT(v, 4, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define ROM_SIZE(v) BFEXT(v, 6, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define RAM_SPLIT(v) BFEXT(v, 16, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define XCVR(v) BFEXT(v, 20, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define AUTOSELECT(v) BFEXT(v, 24, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) enum Window4 { /* Window 4: Xcvr/media bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) enum Win4_Media_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) Media_LnkBeat = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) enum Window7 { /* Window 7: Bus Master control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) Wn7_MasterStatus = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /* Boomerang bus master control registers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) enum MasterCtrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* The Rx and Tx descriptor lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) alignment contraint on tx_ring[] and rx_ring[]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define LAST_FRAG 0x80000000 /* Last Addr/Len pair in descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define DN_COMPLETE 0x00010000 /* This packet has been downloaded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct boom_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) __le32 next; /* Last entry points to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) __le32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) __le32 addr; /* Up to 63 addr/len pairs possible. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) __le32 length; /* Set LAST_FRAG to indicate last pair. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /* Values for the Rx status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) enum rx_desc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) RxDComplete=0x00008000, RxDError=0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) /* See boomerang_rx() for actual error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #ifdef MAX_SKB_FRAGS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define DO_ZEROCOPY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define DO_ZEROCOPY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) struct boom_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) __le32 next; /* Last entry points to 0. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) __le32 status; /* bits 0:12 length, others see below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #if DO_ZEROCOPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) } frag[1+MAX_SKB_FRAGS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) __le32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) __le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Values for the Tx status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) enum tx_desc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) CRCDisable=0x2000, TxDComplete=0x8000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) TxIntrUploaded=0x80000000, /* IRQ when in FIFO, but maybe not sent. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) /* Chip features we care about in vp->capabilities, read from the EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct vortex_extra_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) unsigned long tx_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) unsigned long tx_max_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned long tx_multiple_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned long tx_single_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned long rx_bad_ssd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct vortex_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* The Rx and Tx rings should be quad-word-aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) struct boom_rx_desc* rx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct boom_tx_desc* tx_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dma_addr_t rx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dma_addr_t tx_ring_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /* The addresses of transmit- and receive-in-place skbuffs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct sk_buff* rx_skbuff[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct sk_buff* tx_skbuff[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int cur_rx, cur_tx; /* The next free ring entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int dirty_tx; /* The ring entries to be free()ed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct vortex_extra_stats xstats; /* NIC-specific extra stats */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dma_addr_t tx_skb_dma; /* Allocated DMA address for bus master ctrl DMA. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /* PCI configuration space information. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct device *gendev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) void __iomem *ioaddr; /* IO address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) void __iomem *cb_fn_base; /* CardBus function status addr space. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /* Some values here only for performance evaluation and path-coverage */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) int card_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* The remainder are related to chip state, mostly media selection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct timer_list timer; /* Media selection timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int options; /* User-settable misc. driver options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned int media_override:4, /* Passed-in media type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) default_media:4, /* Read from the EEPROM/Wn3_Config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) full_duplex:1, autoselect:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) bus_master:1, /* Vortex can only do a fragment bus-m. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) full_bus_master_tx:1, full_bus_master_rx:2, /* Boomerang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) flow_ctrl:1, /* Use 802.3x flow control (PAUSE only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) partner_flow_ctrl:1, /* Partner supports flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) has_nway:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) enable_wol:1, /* Wake-on-LAN is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) pm_state_valid:1, /* pci_dev->saved_config_space has sane contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) open:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) medialock:1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) large_frames:1, /* accept large frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) handling_irq:1; /* private in_irq indicator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) /* {get|set}_wol operations are already serialized by rtnl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) * no additional locking is required for the enable_wol and acpi_set_WOL()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) int drv_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u16 status_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u16 intr_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u16 available_media; /* From Wn3_Options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) u16 capabilities, info1, info2; /* Various, from EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) u16 advertising; /* NWay media advertisement */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) unsigned char phys[2]; /* MII device addresses. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) u16 deferred; /* Resend these interrupts when we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) * bale from the ISR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) u16 io_size; /* Size of PCI region (for release_region) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* Serialises access to hardware other than MII and variables below.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) * The lock hierarchy is rtnl_lock > {lock, mii_lock} > window_lock. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) spinlock_t mii_lock; /* Serialises access to MII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct mii_if_info mii; /* MII lib hooks/info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) spinlock_t window_lock; /* Serialises access to windowed regs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) int window; /* Register window */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static void window_set(struct vortex_private *vp, int window)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (window != vp->window) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) vp->window = window;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define DEFINE_WINDOW_IO(size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) static u ## size \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) window_read ## size(struct vortex_private *vp, int window, int addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u ## size ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) spin_lock_irqsave(&vp->window_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) window_set(vp, window); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) ret = ioread ## size(vp->ioaddr + addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) spin_unlock_irqrestore(&vp->window_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static void \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) window_write ## size(struct vortex_private *vp, u ## size value, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int window, int addr) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) spin_lock_irqsave(&vp->window_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) window_set(vp, window); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) iowrite ## size(value, vp->ioaddr + addr); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) spin_unlock_irqrestore(&vp->window_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) DEFINE_WINDOW_IO(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) DEFINE_WINDOW_IO(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) DEFINE_WINDOW_IO(32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) #define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) #define DEVICE_PCI(dev) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define VORTEX_PCI(vp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define DEVICE_EISA(dev) NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) #define VORTEX_EISA(vp) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) /* The action to take with a media selection timer tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) Note that we deviate from the 3Com order by checking 10base2 before AUI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) enum xcvr_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static const struct media_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) mask:8, /* The transceiver-present bit in Wn3_Config.*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) next:8; /* The media type to try next. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int wait; /* Time before we check media status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } media_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) { "undefined", 0, 0x80, XCVR_10baseT, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) { "undefined", 0, 0x01, XCVR_10baseT, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) { "Default", 0, 0xFF, XCVR_10baseT, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) static struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) const char str[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } ethtool_stats_keys[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) { "tx_deferred" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) { "tx_max_collisions" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) { "tx_multiple_collisions" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) { "tx_single_collisions" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) { "rx_bad_ssd" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* number of ETHTOOL_GSTATS u64's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) #define VORTEX_NUM_STATS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int chip_idx, int card_idx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) static int vortex_up(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static void vortex_down(struct net_device *dev, int final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) static int vortex_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static void mdio_sync(struct vortex_private *vp, int bits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) static int mdio_read(struct net_device *dev, int phy_id, int location);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) static void vortex_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static int vortex_rx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) static int boomerang_rx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static irqreturn_t vortex_boomerang_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) static irqreturn_t _vortex_interrupt(int irq, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static irqreturn_t _boomerang_interrupt(int irq, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static int vortex_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) static void dump_tx_ring(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) static void update_stats(void __iomem *ioaddr, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static struct net_device_stats *vortex_get_stats(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static void set_rx_mode(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) static void vortex_tx_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) static void acpi_set_WOL(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static const struct ethtool_ops vortex_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static void set_8021q_mode(struct net_device *dev, int enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) /* Option count limit only -- unlimited interfaces are supported. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) #define MAX_UNITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) static int global_options = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int global_full_duplex = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) static int global_enable_wol = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) static int global_use_mmio = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* Variables to work-around the Compaq PCI BIOS32 problem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static struct net_device *compaq_net_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) static int vortex_cards_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) module_param(global_options, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) module_param_array(options, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) module_param(global_full_duplex, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) module_param_array(full_duplex, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) module_param_array(hw_checksums, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) module_param_array(flow_ctrl, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) module_param(global_enable_wol, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) module_param_array(enable_wol, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) module_param(rx_copybreak, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) module_param(max_interrupt_work, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) module_param_hw(compaq_ioaddr, int, ioport, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) module_param_hw(compaq_irq, int, irq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) module_param(compaq_device_id, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) module_param(watchdog, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) module_param(global_use_mmio, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) module_param_array(use_mmio, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) static void poll_vortex(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) vortex_boomerang_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static int vortex_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (!ndev || !netif_running(ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) netif_device_detach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) vortex_down(ndev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) static int vortex_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct net_device *ndev = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) if (!ndev || !netif_running(ndev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) err = vortex_up(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) netif_device_attach(ndev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct dev_pm_ops vortex_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) .suspend = vortex_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .resume = vortex_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) .freeze = vortex_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) .thaw = vortex_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) .poweroff = vortex_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) .restore = vortex_resume,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define VORTEX_PM_OPS (&vortex_pm_ops)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #else /* !CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define VORTEX_PM_OPS NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #endif /* !CONFIG_PM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) static const struct eisa_device_id vortex_eisa_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) { "TCM5920", CH_3C592 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) { "TCM5970", CH_3C597 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) { "" }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static int vortex_eisa_probe(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct eisa_device *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) edev = to_eisa_device(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) edev->id.driver_data, vortex_cards_found)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) vortex_cards_found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) static int vortex_eisa_remove(struct device *device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) struct eisa_device *edev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct vortex_private *vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) edev = to_eisa_device(device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) dev = eisa_get_drvdata(edev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) pr_err("vortex_eisa_remove called for Compaq device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) static struct eisa_driver vortex_eisa_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) .id_table = vortex_eisa_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .name = "3c59x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) .probe = vortex_eisa_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) .remove = vortex_eisa_remove
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) #endif /* CONFIG_EISA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* returns count found (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) static int __init vortex_eisa_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) int eisa_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int orig_cards_found = vortex_cards_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) err = eisa_driver_register (&vortex_eisa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) * Because of the way EISA bus is probed, we cannot assume
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) * any device have been found when we exit from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) * eisa_driver_register (the bus root driver may not be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) * initialized yet). So we blindly assume something was
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) * found, and let the sysfs magic happened...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) eisa_found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) /* Special code to work-around the Compaq PCI BIOS32 problem. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) if (compaq_ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) compaq_irq, compaq_device_id, vortex_cards_found++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return vortex_cards_found - orig_cards_found + eisa_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) /* returns count (>= 0), or negative on error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) static int vortex_init_one(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) const struct pci_device_id *ent)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) int rc, unit, pci_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct vortex_chip_info *vci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) /* wake up and enable device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) rc = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) rc = pci_request_regions(pdev, DRV_NAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) goto out_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unit = vortex_cards_found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) /* Determine the default if the user didn't override us */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) vci = &vortex_info_tbl[ent->driver_data];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) pci_bar = use_mmio[unit] ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) pci_bar = global_use_mmio ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) ioaddr = pci_iomap(pdev, pci_bar, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (!ioaddr) /* If mapping fails, fall-back to BAR 0... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) ioaddr = pci_iomap(pdev, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) if (!ioaddr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) rc = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) goto out_release;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) ent->driver_data, unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (rc < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) goto out_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) vortex_cards_found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) out_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) pci_iounmap(pdev, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) out_release:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) out_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static const struct net_device_ops boomrang_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) .ndo_open = vortex_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) .ndo_stop = vortex_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) .ndo_start_xmit = boomerang_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) .ndo_tx_timeout = vortex_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) .ndo_get_stats = vortex_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) .ndo_do_ioctl = vortex_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) .ndo_set_rx_mode = set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .ndo_poll_controller = poll_vortex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) static const struct net_device_ops vortex_netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) .ndo_open = vortex_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) .ndo_stop = vortex_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) .ndo_start_xmit = vortex_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) .ndo_tx_timeout = vortex_tx_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) .ndo_get_stats = vortex_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) .ndo_do_ioctl = vortex_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) .ndo_set_rx_mode = set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #ifdef CONFIG_NET_POLL_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .ndo_poll_controller = poll_vortex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) * Start up the PCI/EISA device which is described by *gendev.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) * Return 0 on success.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) * NOTE: pdev can be NULL, for the case of a Compaq device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) int chip_idx, int card_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct vortex_private *vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) int option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int i, step;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static int printed_version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int retval, print_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) const char *print_name = "3c59x";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct pci_dev *pdev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) struct eisa_device *edev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (!printed_version) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) pr_info("%s", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) printed_version = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (gendev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if ((pdev = DEVICE_PCI(gendev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) print_name = pci_name(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if ((edev = DEVICE_EISA(gendev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) print_name = dev_name(&edev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev = alloc_etherdev(sizeof(*vp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) SET_NETDEV_DEV(dev, gendev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) option = global_options;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) /* The lower four bits are the media type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) if (dev->mem_start) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) * The 'options' param is passed in as the third arg to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) * LILO 'ether=' argument for non-modular use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) option = dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) else if (card_idx < MAX_UNITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (options[card_idx] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) option = options[card_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) if (option > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (option & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) vortex_debug = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) if (option & 0x4000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) vortex_debug = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) if (option & 0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) vp->enable_wol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) print_info = (vortex_debug > 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (print_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) pr_info("See Documentation/networking/device_drivers/ethernet/3com/vortex.rst\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) pr_info("%s: 3Com %s %s at %p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) print_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) pdev ? "PCI" : "EISA",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) vci->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) dev->base_addr = (unsigned long)ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dev->mtu = mtu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) vp->ioaddr = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) vp->large_frames = mtu > 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) vp->drv_flags = vci->drv_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) vp->io_size = vci->io_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) vp->card_idx = card_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) vp->window = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* module list only for Compaq device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (gendev == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) compaq_net_device = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) /* PCI-only startup logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) if (pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* enable bus-mastering if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (vci->flags & PCI_USES_MASTER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) if (vci->drv_flags & IS_VORTEX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) u8 pci_latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) u8 new_latency = 248;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) /* Check the PCI latency value. On the 3c590 series the latency timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) must be set to the maximum value to avoid data corruption that occurs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) when the timer expires during a transfer. This bug exists the Vortex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) chip only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (pci_latency < new_latency) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) print_name, pci_latency, new_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) spin_lock_init(&vp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) spin_lock_init(&vp->mii_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) spin_lock_init(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) vp->gendev = gendev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) vp->mii.dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) vp->mii.mdio_read = mdio_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) vp->mii.mdio_write = mdio_write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) vp->mii.phy_id_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) vp->mii.reg_num_mask = 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) /* Makes sure rings are at least 16 byte aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) vp->rx_ring = dma_alloc_coherent(gendev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) &vp->rx_ring_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) if (!vp->rx_ring)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) goto free_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) /* if we are a PCI driver, we store info in pdev->driver_data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) * instead of a module list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) if (pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (edev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) eisa_set_drvdata(edev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) vp->media_override = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (option >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) if (vp->media_override != 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) vp->medialock = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) vp->full_duplex = (option & 0x200) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) vp->bus_master = (option & 16) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) if (global_full_duplex > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) vp->full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) if (global_enable_wol > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) vp->enable_wol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) if (card_idx < MAX_UNITS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (full_duplex[card_idx] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) vp->full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) if (flow_ctrl[card_idx] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) vp->flow_ctrl = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (enable_wol[card_idx] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) vp->enable_wol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) vp->mii.force_media = vp->full_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) vp->options = option;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /* Read the station address from the EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (vci->drv_flags & EEPROM_8BIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) base = 0x230;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) else if (vci->drv_flags & EEPROM_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) base = EEPROM_Read + 0x30;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) base = EEPROM_Read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) for (i = 0; i < 0x40; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) int timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) window_write16(vp, base + i, 0, Wn0EepromCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) /* Pause for at least 162 us. for the read to take place. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) for (timer = 10; timer >= 0; timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) udelay(162);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if ((window_read16(vp, 0, Wn0EepromCmd) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) 0x8000) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) eeprom[i] = window_read16(vp, 0, Wn0EepromData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) for (i = 0; i < 0x18; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) checksum ^= eeprom[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) checksum = (checksum ^ (checksum >> 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (checksum != 0x00) { /* Grrr, needless incompatible change 3Com. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) while (i < 0x21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) checksum ^= eeprom[i++];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) checksum = (checksum ^ (checksum >> 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) if (print_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pr_cont(" %pM", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) /* Unfortunately an all zero eeprom passes the checksum and this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) gets found in the wild in failure cases. Crypto is hard 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) if (!is_valid_ether_addr(dev->dev_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) retval = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) pr_err("*** EEPROM MAC address is invalid.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) goto free_ring; /* With every pack */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) window_write8(vp, dev->dev_addr[i], 2, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (print_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) pr_cont(", IRQ %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) /* Tell them about an invalid IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (dev->irq <= 0 || dev->irq >= nr_irqs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (print_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (pdev && vci->drv_flags & HAS_CB_FNS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) unsigned short n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) vp->cb_fn_base = pci_iomap(pdev, 2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) if (!vp->cb_fn_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) goto free_ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (print_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) print_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) (unsigned long long)pci_resource_start(pdev, 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) vp->cb_fn_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) if (vp->drv_flags & INVERT_LED_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) n |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (vp->drv_flags & INVERT_MII_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) n |= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) window_write16(vp, n, 2, Wn2_ResetOptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (vp->drv_flags & WNO_XCVR_PWR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) window_write16(vp, 0x0800, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) /* Extract our information from the EEPROM data. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) vp->info1 = eeprom[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) vp->info2 = eeprom[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) vp->capabilities = eeprom[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (vp->info1 & 0x8000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) vp->full_duplex = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (print_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) pr_info("Full duplex capable\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) vp->available_media = window_read16(vp, 3, Wn3_Options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if ((vp->available_media & 0xff) == 0) /* Broken 3c916 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) vp->available_media = 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) config = window_read32(vp, 3, Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) if (print_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) config, window_read16(vp, 3, Wn3_Options));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) 8 << RAM_SIZE(config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) RAM_WIDTH(config) ? "word" : "byte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) ram_split[RAM_SPLIT(config)],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) AUTOSELECT(config) ? "autoselect/" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) media_tbl[XCVR(config)].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) vp->default_media = XCVR(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) if (vp->default_media == XCVR_NWAY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) vp->has_nway = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) vp->autoselect = AUTOSELECT(config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (vp->media_override != 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) pr_info("%s: Media override to transceiver type %d (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) print_name, vp->media_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) media_tbl[vp->media_override].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dev->if_port = vp->media_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) dev->if_port = vp->default_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) int phy, phy_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) mii_preamble_required++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (vp->drv_flags & EXTRA_PREAMBLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mii_preamble_required++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) mdio_sync(vp, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) mdio_read(dev, 24, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) int mii_status, phyx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * For the 3c905CX we look at index 24 first, because it bogusly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) * reports an external PHY at all indices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) if (phy == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) phyx = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) else if (phy <= 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) phyx = phy - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) phyx = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) mii_status = mdio_read(dev, phyx, MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) if (mii_status && mii_status != 0xffff) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) vp->phys[phy_idx++] = phyx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) if (print_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) pr_info(" MII transceiver found at address %d, status %4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) phyx, mii_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) if ((mii_status & 0x0040) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) mii_preamble_required++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) mii_preamble_required--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) if (phy_idx == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) pr_warn(" ***WARNING*** No MII transceivers found!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) vp->phys[0] = 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) if (vp->full_duplex) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) /* Only advertise the FD media types. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) vp->advertising &= ~0x02A0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) mdio_write(dev, vp->phys[0], 4, vp->advertising);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) vp->mii.phy_id = vp->phys[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) if (vp->capabilities & CapBusMaster) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) vp->full_bus_master_tx = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (print_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) pr_info(" Enabling bus-master transmits and %s receives.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) (vp->info2 & 1) ? "early" : "whole-frame" );
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) vp->bus_master = 0; /* AKPM: vortex only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* The 3c59x-specific entries in the device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (vp->full_bus_master_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) dev->netdev_ops = &boomrang_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) /* Actually, it still should work with iommu. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) if (card_idx < MAX_UNITS &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) hw_checksums[card_idx] == 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev->netdev_ops = &vortex_netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) if (print_info) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) print_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) (dev->features & NETIF_F_SG) ? "en":"dis",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev->ethtool_ops = &vortex_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) dev->watchdog_timeo = (watchdog * HZ) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) if (pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) vp->pm_state_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) pci_save_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) acpi_set_WOL(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) retval = register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (retval == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) free_ring:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) sizeof(struct boom_rx_desc) * RX_RING_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) sizeof(struct boom_tx_desc) * TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) vp->rx_ring, vp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) free_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) issue_and_wait(struct net_device *dev, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) iowrite16(cmd, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) for (i = 0; i < 2000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) /* OK, that didn't work. Do it the slow way. One second */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) for (i = 0; i < 100000; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) pr_info("%s: command 0x%04x took %d usecs\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) dev->name, cmd, i * 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) vortex_set_duplex(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pr_info("%s: setting %s-duplex.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) dev->name, (vp->full_duplex) ? "full" : "half");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) /* Set the full-duplex bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) window_write16(vp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) (vp->large_frames ? 0x40 : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) 0x100 : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) 3, Wn3_MAC_Ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) static void vortex_check_media(struct net_device *dev, unsigned int init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) unsigned int ok_to_print = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (vortex_debug > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) ok_to_print = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) if (mii_check_media(&vp->mii, ok_to_print, init)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) vp->full_duplex = vp->mii.full_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) vortex_set_duplex(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) } else if (init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) vortex_set_duplex(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) vortex_up(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) int i, mii_reg5, err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (VORTEX_PCI(vp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) pci_set_power_state(VORTEX_PCI(vp), PCI_D0); /* Go active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) if (vp->pm_state_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) pci_restore_state(VORTEX_PCI(vp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) err = pci_enable_device(VORTEX_PCI(vp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) pr_warn("%s: Could not enable device\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /* Before initializing select the active media port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) config = window_read32(vp, 3, Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) if (vp->media_override != 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) pr_info("%s: Media override to transceiver %d (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) dev->name, vp->media_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) media_tbl[vp->media_override].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) dev->if_port = vp->media_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) } else if (vp->autoselect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) if (vp->has_nway) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) pr_info("%s: using NWAY device table, not %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) dev->name, dev->if_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) dev->if_port = XCVR_NWAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* Find first available media type, starting with 100baseTx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) dev->if_port = XCVR_100baseTx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) while (! (vp->available_media & media_tbl[dev->if_port].mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) dev->if_port = media_tbl[dev->if_port].next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) pr_info("%s: first available media type: %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) dev->if_port = vp->default_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) pr_info("%s: using default media %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) timer_setup(&vp->timer, vortex_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) mod_timer(&vp->timer, RUN_AT(media_tbl[dev->if_port].wait));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) pr_debug("%s: Initial media type %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) vp->full_duplex = vp->mii.force_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) config = BFINS(config, dev->if_port, 20, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) if (vortex_debug > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) window_write32(vp, config, 3, Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) mdio_read(dev, vp->phys[0], MII_BMSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) vp->mii.full_duplex = vp->full_duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) vortex_check_media(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) vortex_set_duplex(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) issue_and_wait(dev, TxReset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * Don't reset the PHY - that upsets autonegotiation during DHCP operations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) issue_and_wait(dev, RxReset|0x04);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) if (vortex_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) /* Set the station address and mask in window 2 each time opened. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) window_write8(vp, dev->dev_addr[i], 2, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) for (; i < 12; i+=2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) window_write16(vp, 0, 2, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) if (vp->cb_fn_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) if (vp->drv_flags & INVERT_LED_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) n |= 0x10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (vp->drv_flags & INVERT_MII_PWR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) n |= 0x4000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) window_write16(vp, n, 2, Wn2_ResetOptions);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) if (dev->if_port == XCVR_10base2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* Start the thinnet transceiver. We should really wait 50ms...*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) iowrite16(StartCoax, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (dev->if_port != XCVR_NWAY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) window_write16(vp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) (window_read16(vp, 4, Wn4_Media) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) ~(Media_10TP|Media_SQE)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) media_tbl[dev->if_port].media_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) 4, Wn4_Media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) /* Switch to the stats window, and clear all stats by reading. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) iowrite16(StatsDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) for (i = 0; i < 10; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) window_read8(vp, 6, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) window_read16(vp, 6, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) window_read16(vp, 6, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* New: On the Vortex we must also clear the BadSSD counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) window_read8(vp, 4, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) /* ..and on the Boomerang we enable the extra statistics bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) window_write16(vp, 0x0040, 4, Wn4_NetDiag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (vp->full_bus_master_rx) { /* Boomerang bus master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) vp->cur_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) /* Initialize the RxEarly register as recommended. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) iowrite32(0x0020, ioaddr + PktStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) vp->cur_tx = vp->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) if (vp->drv_flags & IS_BOOMERANG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold); /* Room for a packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) /* Clear the Rx, Tx rings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) for (i = 0; i < RX_RING_SIZE; i++) /* AKPM: this is done in vortex_open, too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) vp->rx_ring[i].status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) vp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) iowrite32(0, ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) /* Set receiver mode: presumably accept b-case and phys addr only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* enable 802.1q tagged frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) set_8021q_mode(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) iowrite16(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) iowrite16(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) iowrite16(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) /* Allow status bits to be seen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) (vp->full_bus_master_rx ? UpComplete : RxComplete) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) (vp->bus_master ? DMADone : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) (vp->full_bus_master_rx ? 0 : RxComplete) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) StatsFull | HostError | TxComplete | IntReq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) iowrite16(vp->status_enable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) /* Ack all pending events, and set active indicator mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) iowrite32(0x8000, vp->cb_fn_base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) netif_start_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) netdev_reset_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) vortex_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) /* Use the now-standard shared IRQ implementation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) if ((retval = request_irq(dev->irq, vortex_boomerang_interrupt, IRQF_SHARED, dev->name, dev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (vp->full_bus_master_rx) { /* Boomerang bus master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) if (vortex_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) pr_debug("%s: Filling in the Rx ring.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) vp->rx_ring[i].status = 0; /* Clear complete bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) vp->rx_skbuff[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) break; /* Bad news! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) skb_reserve(skb, NET_IP_ALIGN); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) dma = dma_map_single(vp->gendev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) if (dma_mapping_error(vp->gendev, dma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) vp->rx_ring[i].addr = cpu_to_le32(dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) if (i != RX_RING_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) pr_emerg("%s: no memory for rx ring\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) retval = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) goto err_free_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) /* Wrap the ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) retval = vortex_up(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (!retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) err_free_skb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) if (vp->rx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) dev_kfree_skb(vp->rx_skbuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) vp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) vortex_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct vortex_private *vp = from_timer(vp, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct net_device *dev = vp->mii.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) int next_tick = 60*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) int ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) int media_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) if (vortex_debug > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) pr_debug("%s: Media selection timer tick happened, %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) media_status = window_read16(vp, 4, Wn4_Media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) switch (dev->if_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) if (media_status & Media_LnkBeat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) netif_carrier_on(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) pr_debug("%s: Media %s has link beat, %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) dev->name, media_tbl[dev->if_port].name, media_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) netif_carrier_off(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (vortex_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) pr_debug("%s: Media %s has no link beat, %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) dev->name, media_tbl[dev->if_port].name, media_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) case XCVR_MII: case XCVR_NWAY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) vortex_check_media(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) default: /* Other media types handled by Tx timeouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) pr_debug("%s: Media %s has no indication, %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) dev->name, media_tbl[dev->if_port].name, media_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) next_tick = 5*HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (vp->medialock)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) goto leave_media_alone;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) if (!ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) unsigned int config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) spin_lock_irq(&vp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) dev->if_port = media_tbl[dev->if_port].next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) if (dev->if_port == XCVR_Default) { /* Go back to default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) dev->if_port = vp->default_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) pr_debug("%s: Media selection failing, using default %s port.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) pr_debug("%s: Media selection failed, now trying %s port.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) next_tick = media_tbl[dev->if_port].wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) window_write16(vp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) (media_status & ~(Media_10TP|Media_SQE)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) media_tbl[dev->if_port].media_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) 4, Wn4_Media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) config = window_read32(vp, 3, Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) config = BFINS(config, dev->if_port, 20, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) window_write32(vp, config, 3, Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) pr_debug("wrote 0x%08x to Wn3_Config\n", config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) /* AKPM: FIXME: Should reset Rx & Tx here. P60 of 3c90xc.pdf */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) spin_unlock_irq(&vp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) leave_media_alone:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) if (vortex_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) pr_debug("%s: Media selection timer finished, %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) mod_timer(&vp->timer, RUN_AT(next_tick));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) if (vp->deferred)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) iowrite16(FakeIntr, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) static void vortex_tx_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) dev->name, ioread8(ioaddr + TxStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) ioread16(ioaddr + EL3_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) window_read16(vp, 4, Wn4_NetDiag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) window_read16(vp, 4, Wn4_Media),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) ioread32(ioaddr + PktStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) window_read16(vp, 4, Wn4_FIFODiag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* Slight code bloat to be user friendly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) pr_err("%s: Transmitter encountered 16 collisions --"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) " network cable problem?\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) pr_err("%s: Interrupt posted but not delivered --"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) " IRQ blocked by another device?\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) /* Bad idea here.. but we might as well handle a few events. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) vortex_boomerang_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (vortex_debug > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) dump_tx_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) issue_and_wait(dev, TxReset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (vp->full_bus_master_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) netif_wake_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) netdev_reset_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) if (vp->drv_flags & IS_BOOMERANG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) iowrite16(DownUnstall, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) netdev_reset_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) /* Issue Tx Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) iowrite16(TxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) * Handle uncommon interrupt sources. This is a separate routine to minimize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) * the cache impact.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) vortex_error(struct net_device *dev, int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) int do_tx_reset = 0, reset_mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) unsigned char tx_status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (vortex_debug > 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) if (status & TxComplete) { /* Really "TxError" for us. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) tx_status = ioread8(ioaddr + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /* Presumably a tx-timeout. We must merely re-enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) if (vortex_debug > 2 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) (tx_status != 0x88 && vortex_debug > 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) pr_err("%s: Transmit error, Tx status register %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) dev->name, tx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) if (tx_status == 0x82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) pr_err("Probably a duplex mismatch. See "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) "Documentation/networking/device_drivers/ethernet/3com/vortex.rst\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) dump_tx_ring(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) iowrite8(0, ioaddr + TxStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) if (tx_status & 0x30) { /* txJabber or txUnderrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) do_tx_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) { /* maxCollisions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) do_tx_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) reset_mask = 0x0108; /* Reset interface logic, but not download logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) } else { /* Merely re-enable the transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) iowrite16(TxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (status & RxEarly) /* Rx early is unused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) if (status & StatsFull) { /* Empty statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) static int DoneDidThat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) pr_debug("%s: Updating stats.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) update_stats(ioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) /* HACK: Disable statistics as an interrupt source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* This occurs when we have the wrong media type! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) if (DoneDidThat == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) ioread16(ioaddr + EL3_STATUS) & StatsFull) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) iowrite16(SetIntrEnb |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) (window_read16(vp, 5, 10) & ~StatsFull),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) vp->intr_enable &= ~StatsFull;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) DoneDidThat++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) if (status & IntReq) { /* Restore all interrupt sources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) iowrite16(vp->status_enable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (status & HostError) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) u16 fifo_diag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) dev->name, fifo_diag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) /* Adapter failure requires Tx/Rx reset and reinit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (vp->full_bus_master_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) int bus_status = ioread32(ioaddr + PktStatus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) /* 0x80000000 PCI master abort. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) /* 0x40000000 PCI target abort. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (vortex_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* In this case, blow the card away */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* Must not enter D3 or we can't legally issue the reset! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) vortex_down(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) issue_and_wait(dev, TotalReset | 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) vortex_up(dev); /* AKPM: bug. vortex_up() assumes that the rx ring is full. It may not be. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) } else if (fifo_diag & 0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) do_tx_reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) if (fifo_diag & 0x3000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* Reset Rx fifo and upload logic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) issue_and_wait(dev, RxReset|0x07);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* Set the Rx filter to the current state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* enable 802.1q VLAN tagged frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) set_8021q_mode(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) iowrite16(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (do_tx_reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) issue_and_wait(dev, TxReset|reset_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) iowrite16(TxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) if (!vp->full_bus_master_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) int skblen = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) /* Put out the doubleword header... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) iowrite32(skb->len, ioaddr + TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) if (vp->bus_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) /* Set the bus-master controller to transfer the packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) int len = (skb->len + 3) & ~3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) vp->tx_skb_dma = dma_map_single(vp->gendev, skb->data, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) if (dma_mapping_error(vp->gendev, vp->tx_skb_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) dev_kfree_skb_any(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) spin_lock_irq(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) window_set(vp, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) iowrite16(len, ioaddr + Wn7_MasterLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) spin_unlock_irq(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) vp->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) iowrite16(StartDMADown, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) /* netif_wake_queue() will be called at the DMADone interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) /* ... and the packet rounded to a doubleword. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) dev_consume_skb_any (skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (ioread16(ioaddr + TxFree) > 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) netif_start_queue (dev); /* AKPM: redundant? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* Interrupt us when the FIFO has room for max-sized packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) netdev_sent_queue(dev, skblen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) /* Clear the Tx status stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) int tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) int i = 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) if (vortex_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) pr_debug("%s: Tx error, status %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) dev->name, tx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) if (tx_status & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) issue_and_wait(dev, TxReset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) iowrite16(TxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) iowrite8(0x00, ioaddr + TxStatus); /* Pop the status stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) static netdev_tx_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) /* Calculate the next Tx descriptor entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) int entry = vp->cur_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) int skblen = skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (vortex_debug > 6) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) pr_debug("boomerang_start_xmit()\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) pr_debug("%s: Trying to send a packet, Tx index %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) dev->name, vp->cur_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) * We can't allow a recursion from our interrupt handler back into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) * tx routine, as they take the same spin lock, and that causes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) * deadlock. Just return NETDEV_TX_BUSY and let the stack try again in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) * a bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) if (vp->handling_irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) if (vortex_debug > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) vp->tx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) vp->tx_ring[entry].next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) #if DO_ZEROCOPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (skb->ip_summed != CHECKSUM_PARTIAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) if (!skb_shinfo(skb)->nr_frags) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) dma_addr = dma_map_single(vp->gendev, skb->data, skb->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) if (dma_mapping_error(vp->gendev, dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) goto out_dma_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dma_addr = dma_map_single(vp->gendev, skb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) skb_headlen(skb), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) if (dma_mapping_error(vp->gendev, dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) goto out_dma_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) dma_addr = skb_frag_dma_map(vp->gendev, frag,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) skb_frag_size(frag),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (dma_mapping_error(vp->gendev, dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) for(i = i-1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) dma_unmap_page(vp->gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) dma_unmap_single(vp->gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) le32_to_cpu(vp->tx_ring[entry].frag[0].length),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) goto out_dma_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) vp->tx_ring[entry].frag[i+1].addr =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) if (i == skb_shinfo(skb)->nr_frags-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) dma_addr = dma_map_single(vp->gendev, skb->data, skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) if (dma_mapping_error(vp->gendev, dma_addr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) goto out_dma_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) spin_lock_irqsave(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) /* Wait for the stall to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) issue_and_wait(dev, DownStall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (ioread32(ioaddr + DownListPtr) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) vp->queued_packet++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) vp->cur_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) netdev_sent_queue(dev, skblen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) netif_stop_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) } else { /* Clear previous interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) #if defined(tx_interrupt_mitigation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) /* Dubious. If in boomeang_interrupt "faster" cyclone ifdef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) * were selected, this would corrupt DN_COMPLETE. No?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) skb_tx_timestamp(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) iowrite16(DownUnstall, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) spin_unlock_irqrestore(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) out_dma_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) dev_err(vp->gendev, "Error mapping dma buffer\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) /* The interrupt handler does all of the Rx thread work and cleans up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) after the Tx thread. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) * This is the ISR for the vortex series chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) * full_bus_master_tx == 0 && full_bus_master_rx == 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) _vortex_interrupt(int irq, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) int work_done = max_interrupt_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) unsigned int bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) status = ioread16(ioaddr + EL3_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (vortex_debug > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) pr_debug("vortex_interrupt(). status=0x%4x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) if ((status & IntLatch) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) goto handler_exit; /* No interrupt: shared IRQs cause this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) if (status & IntReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) status |= vp->deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) vp->deferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) if (status == 0xffff) /* h/w no longer present (hotplug)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) goto handler_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) dev->name, status, ioread8(ioaddr + Timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) spin_lock(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) window_set(vp, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) if (vortex_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) pr_debug("%s: In interrupt loop, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) if (status & RxComplete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) vortex_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) if (status & TxAvailable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) if (vortex_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) pr_debug(" TX room bit was handled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* There's room in the FIFO for a full-sized packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) netif_wake_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) if (status & DMADone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) iowrite16(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) dma_unmap_single(vp->gendev, vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) bytes_compl += vp->tx_skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) dev_consume_skb_irq(vp->tx_skb); /* Release the transferred buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) if (ioread16(ioaddr + TxFree) > 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) * AKPM: FIXME: I don't think we need this. If the queue was stopped due to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) * insufficient FIFO room, the TxAvailable test will succeed and call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) * netif_wake_queue()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) } else { /* Interrupt when FIFO has room for max-sized packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) /* Check for all uncommon interrupts at once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) if (status == 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) if (status & RxEarly)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) vortex_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) spin_unlock(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) vortex_error(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) spin_lock(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) window_set(vp, 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) if (--work_done < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) pr_warn("%s: Too much work in interrupt, status %4.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) /* Disable all pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) vp->deferred |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) /* The timer will reenable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) mod_timer(&vp->timer, jiffies + 1*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) /* Acknowledge the IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) netdev_completed_queue(dev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) spin_unlock(&vp->window_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) pr_debug("%s: exiting interrupt, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) handler_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) * This is the ISR for the boomerang series chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) * full_bus_master_tx == 1 && full_bus_master_rx == 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) _boomerang_interrupt(int irq, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) int work_done = max_interrupt_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) int handled = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) unsigned int bytes_compl = 0, pkts_compl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) vp->handling_irq = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) status = ioread16(ioaddr + EL3_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) if (vortex_debug > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) pr_debug("boomerang_interrupt. status=0x%4x\n", status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) if ((status & IntLatch) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) goto handler_exit; /* No interrupt: shared IRQs can cause this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) handled = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) if (status == 0xffff) { /* h/w no longer present (hotplug)? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (vortex_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) pr_debug("boomerang_interrupt(1): status = 0xffff\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) goto handler_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) if (status & IntReq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) status |= vp->deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) vp->deferred = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) dev->name, status, ioread8(ioaddr + Timer));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) if (vortex_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) pr_debug("%s: In interrupt loop, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) if (status & UpComplete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (vortex_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) pr_debug("boomerang_interrupt->boomerang_rx\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) boomerang_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) if (status & DownComplete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) unsigned int dirty_tx = vp->dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) while (vp->cur_tx - dirty_tx > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) int entry = dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) #if 1 /* AKPM: the latter is faster, but cyclone-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) if (ioread32(ioaddr + DownListPtr) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) break; /* It still hasn't been processed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) break; /* It still hasn't been processed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (vp->tx_skbuff[entry]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) struct sk_buff *skb = vp->tx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) #if DO_ZEROCOPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) dma_unmap_single(vp->gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) le32_to_cpu(vp->tx_ring[entry].frag[0].length)&0xFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) for (i=1; i<=skb_shinfo(skb)->nr_frags; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) dma_unmap_page(vp->gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) dma_unmap_single(vp->gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) le32_to_cpu(vp->tx_ring[entry].addr), skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) pkts_compl++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) bytes_compl += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) dev_consume_skb_irq(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) vp->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) pr_debug("boomerang_interrupt: no skb!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) /* dev->stats.tx_packets++; Counted below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) dirty_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) vp->dirty_tx = dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (vortex_debug > 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) pr_debug("boomerang_interrupt: wake queue\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) netif_wake_queue (dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) /* Check for all uncommon interrupts at once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) vortex_error(dev, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) if (--work_done < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) pr_warn("%s: Too much work in interrupt, status %4.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) /* Disable all pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) vp->deferred |= status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) /* The timer will reenable interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) mod_timer(&vp->timer, jiffies + 1*HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) /* Acknowledge the IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) if (vp->cb_fn_base) /* The PCMCIA people are idiots. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) iowrite32(0x8000, vp->cb_fn_base + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) netdev_completed_queue(dev, pkts_compl, bytes_compl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) pr_debug("%s: exiting interrupt, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) handler_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) vp->handling_irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) return IRQ_RETVAL(handled);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) static irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) vortex_boomerang_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) irqreturn_t ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) spin_lock_irqsave(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) if (vp->full_bus_master_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) ret = _boomerang_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) ret = _vortex_interrupt(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) spin_unlock_irqrestore(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) static int vortex_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) short rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) if (vortex_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (rx_status & 0x4000) { /* Error, update stats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) unsigned char rx_error = ioread8(ioaddr + RxErrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) if (vortex_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) pr_debug(" Rx error: status %2.2x.\n", rx_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) if (rx_error & 0x01) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) if (rx_error & 0x02) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) if (rx_error & 0x04) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) if (rx_error & 0x08) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) if (rx_error & 0x10) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) /* The packet length: up to 4.5K!. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) int pkt_len = rx_status & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) skb = netdev_alloc_skb(dev, pkt_len + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) pr_debug("Receiving packet size %d status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) pkt_len, rx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) if (skb != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) /* 'skb_put()' points to the start of sk_buff data area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (vp->bus_master &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) dma_addr_t dma = dma_map_single(vp->gendev, skb_put(skb, pkt_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) pkt_len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) iowrite32(dma, ioaddr + Wn7_MasterAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) iowrite16(StartDMAUp, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) dma_unmap_single(vp->gendev, dma, pkt_len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ioread32_rep(ioaddr + RX_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) skb_put(skb, pkt_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) (pkt_len + 3) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) iowrite16(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) /* Wait a limited time to go to next packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) for (i = 200; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) } else if (vortex_debug > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) dev->name, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) issue_and_wait(dev, RxDiscard);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) boomerang_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) int entry = vp->cur_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) int rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) int rx_work_limit = RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) if (vortex_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (--rx_work_limit < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (rx_status & RxDError) { /* Error, update stats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) unsigned char rx_error = rx_status >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) if (vortex_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) pr_debug(" Rx error: status %2.2x.\n", rx_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (rx_error & 0x01) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) if (rx_error & 0x02) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (rx_error & 0x04) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) if (rx_error & 0x08) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) if (rx_error & 0x10) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) /* The packet length: up to 4.5K!. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) int pkt_len = rx_status & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) struct sk_buff *skb, *newskb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) dma_addr_t newdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) if (vortex_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) pr_debug("Receiving packet size %d status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) pkt_len, rx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) /* Check if the packet is long enough to just accept without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) copying to a properly sized skbuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) if (pkt_len < rx_copybreak &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) dma_sync_single_for_cpu(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) /* 'skb_put()' points to the start of sk_buff data area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) skb_put_data(skb, vp->rx_skbuff[entry]->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) dma_sync_single_for_device(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) vp->rx_copy++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) /* Pre-allocate the replacement skb. If it or its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) * mapping fails then recycle the buffer thats already
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) * in place
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) newskb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) if (!newskb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) goto clear_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) newdma = dma_map_single(vp->gendev, newskb->data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) if (dma_mapping_error(vp->gendev, newdma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) consume_skb(newskb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) goto clear_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) /* Pass up the skbuff already on the Rx ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) skb = vp->rx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) vp->rx_skbuff[entry] = newskb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) vp->rx_ring[entry].addr = cpu_to_le32(newdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) dma_unmap_single(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) vp->rx_nocopy++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) { /* Use hardware checksum info. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) int csum_bits = rx_status & 0xee000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) if (csum_bits &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) (csum_bits == (IPChksumValid | TCPChksumValid) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) csum_bits == (IPChksumValid | UDPChksumValid))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) skb->ip_summed = CHECKSUM_UNNECESSARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) vp->rx_csumhits++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) clear_complete:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) vp->rx_ring[entry].status = 0; /* Clear complete bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) iowrite16(UpUnstall, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) entry = (++vp->cur_rx) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) vortex_down(struct net_device *dev, int final_down)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) netdev_reset_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) del_timer_sync(&vp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) /* Turn off statistics ASAP. We update dev->stats below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) iowrite16(StatsDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) /* Disable the receiver and transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) iowrite16(RxDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) iowrite16(TxDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) /* Disable receiving 802.1q tagged frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) set_8021q_mode(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (dev->if_port == XCVR_10base2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) /* Turn off thinnet power. Green! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) iowrite16(StopCoax, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) update_stats(ioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (vp->full_bus_master_rx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) iowrite32(0, ioaddr + UpListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) if (vp->full_bus_master_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) iowrite32(0, ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (final_down && VORTEX_PCI(vp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) vp->pm_state_valid = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) pci_save_state(VORTEX_PCI(vp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) acpi_set_WOL(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) vortex_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) if (netif_device_present(dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) vortex_down(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (vortex_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) " tx_queued %d Rx pre-checksummed %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) #if DO_ZEROCOPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) if (vp->rx_csumhits &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) (vp->drv_flags & HAS_HWCKSM) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) pr_warn("%s supports hardware checksums, and we're not using them!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) for (i = 0; i < RX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) if (vp->rx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) dma_unmap_single(vp->gendev, le32_to_cpu(vp->rx_ring[i].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) PKT_BUF_SZ, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) dev_kfree_skb(vp->rx_skbuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) vp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) if (vp->tx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) struct sk_buff *skb = vp->tx_skbuff[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) #if DO_ZEROCOPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) int k;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) dma_unmap_single(vp->gendev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) le32_to_cpu(vp->tx_ring[i].frag[k].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) dma_unmap_single(vp->gendev, le32_to_cpu(vp->tx_ring[i].addr), skb->len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) vp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) dump_tx_ring(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) if (vortex_debug > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) if (vp->full_bus_master_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) int stalled = ioread32(ioaddr + PktStatus) & 0x04; /* Possible racy. But it's only debug stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) vp->full_bus_master_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) pr_err(" Transmit list %8.8x vs. %p.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) ioread32(ioaddr + DownListPtr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) issue_and_wait(dev, DownStall);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) unsigned int length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) #if DO_ZEROCOPY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) length = le32_to_cpu(vp->tx_ring[i].length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) pr_err(" %d: @%p length %8.8x status %8.8x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) i, &vp->tx_ring[i], length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) le32_to_cpu(vp->tx_ring[i].status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) if (!stalled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) iowrite16(DownUnstall, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) static struct net_device_stats *vortex_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) if (netif_device_present(dev)) { /* AKPM: Used to be netif_running */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) spin_lock_irqsave (&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) update_stats(ioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) spin_unlock_irqrestore (&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) /* Update statistics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) Unlike with the EL3 we need not worry about interrupts changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) the window setting from underneath us, but we must still guard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) against a race condition with a StatsUpdate interrupt updating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) table. This is done by checking that the ASM (!) code generated uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) atomic updates with '+='.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) static void update_stats(void __iomem *ioaddr, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) /* Switch to the stats window, and read everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) dev->stats.tx_window_errors += window_read8(vp, 6, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) dev->stats.tx_packets += window_read8(vp, 6, 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) dev->stats.tx_packets += (window_read8(vp, 6, 9) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) 0x30) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) /* Rx packets */ window_read8(vp, 6, 7); /* Must read to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) /* Don't bother with register 9, an extension of registers 6&7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) If we do use the 6&7 values the atomic update assumption above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) is invalid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) dev->stats.rx_bytes += window_read16(vp, 6, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) dev->stats.tx_bytes += window_read16(vp, 6, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) /* Extra stats for get_ethtool_stats() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) vp->xstats.tx_deferred += window_read8(vp, 6, 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) dev->stats.collisions = vp->xstats.tx_multiple_collisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) + vp->xstats.tx_single_collisions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) + vp->xstats.tx_max_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) u8 up = window_read8(vp, 4, 13);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) dev->stats.rx_bytes += (up & 0x0f) << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) dev->stats.tx_bytes += (up & 0xf0) << 12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static int vortex_nway_reset(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) return mii_nway_restart(&vp->mii);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) static int vortex_get_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) mii_ethtool_get_link_ksettings(&vp->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) static int vortex_set_link_ksettings(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) const struct ethtool_link_ksettings *cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) return mii_ethtool_set_link_ksettings(&vp->mii, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) static u32 vortex_get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) return vortex_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) vortex_debug = dbg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) static int vortex_get_sset_count(struct net_device *dev, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) switch (sset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) return VORTEX_NUM_STATS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) static void vortex_get_ethtool_stats(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) struct ethtool_stats *stats, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) spin_lock_irqsave(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) update_stats(ioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) spin_unlock_irqrestore(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) data[0] = vp->xstats.tx_deferred;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) data[1] = vp->xstats.tx_max_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) data[2] = vp->xstats.tx_multiple_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) data[3] = vp->xstats.tx_single_collisions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) data[4] = vp->xstats.rx_bad_ssd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) switch (stringset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) case ETH_SS_STATS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) static void vortex_get_drvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) if (VORTEX_PCI(vp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) if (VORTEX_EISA(vp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) strlcpy(info->bus_info, dev_name(vp->gendev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) sizeof(info->bus_info));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) snprintf(info->bus_info, sizeof(info->bus_info),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) "EISA 0x%lx %d", dev->base_addr, dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) if (!VORTEX_PCI(vp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) wol->supported = WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) wol->wolopts = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) if (vp->enable_wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) wol->wolopts |= WAKE_MAGIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (!VORTEX_PCI(vp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) if (wol->wolopts & ~WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) if (wol->wolopts & WAKE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) vp->enable_wol = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) vp->enable_wol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) acpi_set_WOL(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) static const struct ethtool_ops vortex_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .get_drvinfo = vortex_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .get_strings = vortex_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .get_msglevel = vortex_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .set_msglevel = vortex_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .get_ethtool_stats = vortex_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .get_sset_count = vortex_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .get_link = ethtool_op_get_link,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .nway_reset = vortex_nway_reset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) .get_wol = vortex_get_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) .set_wol = vortex_set_wol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .get_ts_info = ethtool_op_get_ts_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .get_link_ksettings = vortex_get_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .set_link_ksettings = vortex_set_link_ksettings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) #ifdef CONFIG_PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) * Must power the device up to do MDIO operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) pci_power_t state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) if(VORTEX_PCI(vp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) state = VORTEX_PCI(vp)->current_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) /* The kernel core really should have pci_get_power_state() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) if(state != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) if(state != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) pci_set_power_state(VORTEX_PCI(vp), state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) /* Pre-Cyclone chips have no documented multicast filter, so the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) multicast setting is to receive all multicast frames. At least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) the chip has a very clean way to set the mode, unlike many others. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) static void set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) int new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) if (vortex_debug > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) pr_notice("%s: Setting promiscuous mode.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) new_mode = SetRxFilter | RxStation | RxBroadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) iowrite16(new_mode, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) #if IS_ENABLED(CONFIG_VLAN_8021Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) /* Setup the card so that it can receive frames with an 802.1q VLAN tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) Note that this must be done after each RxReset due to some backwards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) compatibility logic in the Cyclone and Tornado ASICs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) /* The Ethernet Type used for 802.1q tagged frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) #define VLAN_ETHER_TYPE 0x8100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) static void set_8021q_mode(struct net_device *dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) int mac_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) /* cyclone and tornado chipsets can recognize 802.1q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) * tagged frames and treat them correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) int max_pkt_size = dev->mtu+14; /* MTU+Ethernet header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) if (enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) max_pkt_size += 4; /* 802.1Q VLAN tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) /* set VlanEtherType to let the hardware checksumming
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) treat tagged frames correctly */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) /* on older cards we have to enable large frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) vp->large_frames = dev->mtu > 1500 || enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) if (vp->large_frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) mac_ctrl |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) mac_ctrl &= ~0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) static void set_8021q_mode(struct net_device *dev, int enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /* MII transceiver control section.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) Read and write the MII registers using software-generated serial
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) MDIO protocol. See the MII specifications or DP83840A data sheet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) for details. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) met by back-to-back PCI I/O cycles, but we insert a delay to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) "overclocking" issues. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) static void mdio_delay(struct vortex_private *vp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) window_read32(vp, 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) #define MDIO_SHIFT_CLK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) #define MDIO_DIR_WRITE 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) #define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) #define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) #define MDIO_DATA_READ 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) #define MDIO_ENB_IN 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) /* Generate the preamble required for initial synchronization and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) a few older transceivers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) static void mdio_sync(struct vortex_private *vp, int bits)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) /* Establish sync by sending at least 32 logic ones. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) while (-- bits >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) static int mdio_read(struct net_device *dev, int phy_id, int location)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) unsigned int retval = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) spin_lock_bh(&vp->mii_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) if (mii_preamble_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) mdio_sync(vp, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) /* Shift the read command bits out. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) for (i = 14; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) window_write16(vp, dataval | MDIO_SHIFT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) /* Read the two transition, 16 data, and wire-idle bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) for (i = 19; i > 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) retval = (retval << 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) MDIO_DATA_READ) ? 1 : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) spin_unlock_bh(&vp->mii_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) spin_lock_bh(&vp->mii_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) if (mii_preamble_required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) mdio_sync(vp, 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) /* Shift the command bits out. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) for (i = 31; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) window_write16(vp, dataval | MDIO_SHIFT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) /* Leave the interface idle. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) for (i = 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) 4, Wn4_PhysicalMgmt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) mdio_delay(vp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) spin_unlock_bh(&vp->mii_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) /* ACPI: Advanced Configuration and Power Interface. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) /* Set Wake-On-LAN mode and put the board into D3 (power-down) state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) static void acpi_set_WOL(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) struct vortex_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) void __iomem *ioaddr = vp->ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) device_set_wakeup_enable(vp->gendev, vp->enable_wol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) if (vp->enable_wol) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) /* Power up on: 1==Downloaded Filter, 2==Magic Packets, 4==Link Status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) window_write16(vp, 2, 7, 0x0c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) /* The RxFilter must accept the WOL frames. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) iowrite16(RxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) vp->enable_wol = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) /* Change the power state to D3; RxEnable doesn't take effect. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) static void vortex_remove_one(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) struct net_device *dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) struct vortex_private *vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) pr_err("vortex_remove_one called for Compaq device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) if (vp->cb_fn_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267) pci_iounmap(pdev, vp->cb_fn_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) pci_set_power_state(pdev, PCI_D0); /* Go active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) if (vp->pm_state_valid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) pci_restore_state(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) /* Should really use issue_and_wait() here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) vp->ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280) pci_iounmap(pdev, vp->ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) dma_free_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) sizeof(struct boom_rx_desc) * RX_RING_SIZE +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) sizeof(struct boom_tx_desc) * TX_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) vp->rx_ring, vp->rx_ring_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) static struct pci_driver vortex_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) .name = "3c59x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) .probe = vortex_init_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) .remove = vortex_remove_one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) .id_table = vortex_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) .driver.pm = VORTEX_PM_OPS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) static int vortex_have_pci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) static int vortex_have_eisa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) static int __init vortex_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) int pci_rc, eisa_rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) pci_rc = pci_register_driver(&vortex_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) eisa_rc = vortex_eisa_init();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) if (pci_rc == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) vortex_have_pci = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) if (eisa_rc > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) vortex_have_eisa = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) static void __exit vortex_eisa_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) void __iomem *ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326) #ifdef CONFIG_EISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) /* Take care of the EISA devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) eisa_driver_unregister(&vortex_eisa_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) if (compaq_net_device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) ioaddr = ioport_map(compaq_net_device->base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) VORTEX_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) unregister_netdev(compaq_net_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) iowrite16(TotalReset, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) release_region(compaq_net_device->base_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) VORTEX_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) free_netdev(compaq_net_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) static void __exit vortex_cleanup(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) if (vortex_have_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) pci_unregister_driver(&vortex_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (vortex_have_eisa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) vortex_eisa_cleanup();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) module_init(vortex_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) module_exit(vortex_cleanup);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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