^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Written 1997-1998 by Donald Becker.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) This software may be used and distributed according to the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) of the GNU General Public License, incorporated herein by reference.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) This driver is for the 3Com ISA EtherLink XL "Corkscrew" 3c515 ethercard.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) The author may be reached as becker@scyld.com, or C/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Scyld Computing Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 410 Severn Ave., Suite 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Annapolis MD 21403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 2000/2/2- Added support for kernel-level ISAPnP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) by Stephen Frost <sfrost@snowman.net> and Alessandro Zummo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Cleaned up for 2.3.x/softnet by Jeff Garzik and Alan Cox.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 2001/11/17 - Added ethtool support (jgarzik)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 2002/10/28 - Locking updates for 2.5 (alan@lxorguk.ukuu.org.uk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRV_NAME "3c515"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CORKSCREW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* "Knobs" that adjust features and parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Setting to > 1512 effectively disables this feature. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static int rx_copybreak = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* Allow setting MTU to a larger size, bypassing the normal ethernet setup. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static const int mtu = 1500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Maximum events (Rx packets, etc.) to handle at each interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static int max_interrupt_work = 20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Enable the automatic media selection code -- usually set. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AUTOMEDIA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Allow the use of fragment bus master transfers instead of only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) programmed-I/O for Vortex cards. Full-bus-master transfers are always
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) enabled by default on Boomerang cards. If VORTEX_BUS_MASTER is defined,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) the feature may be turned on using 'options'. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define VORTEX_BUS_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* A few values that may be tweaked. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Keep the ring sizes a power of two for efficiency. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TX_RING_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define RX_RING_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #include <linux/isapnp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/in.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/ioport.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/skbuff.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/timer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/ethtool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <asm/dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define NEW_MULTICAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MAX_UNITS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) MODULE_DESCRIPTION("3Com 3c515 Corkscrew driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* "Knobs" for adjusting internal parameters. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Put out somewhat more debugging messages. (0 - no msg, 1 minimal msgs). */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DRIVER_DEBUG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Some values here only for performance evaluation and path-coverage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) debugging. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static int rx_nocopy, rx_copy, queued_packet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Number of times to check to see if the Tx FIFO has space, used in some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) limited cases. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WAIT_TX_AVAIL 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Operational parameter that usually are not changed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TX_TIMEOUT ((4*HZ)/10) /* Time in jiffies before concluding Tx hung */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* The size here is somewhat misleading: the Corkscrew also uses the ISA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) aliased registers at <base>+0x400.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CORKSCREW_TOTAL_SIZE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #ifdef DRIVER_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static int corkscrew_debug = DRIVER_DEBUG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static int corkscrew_debug = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CORKSCREW_ID 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Theory of Operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) I. Board Compatibility
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) This device driver is designed for the 3Com 3c515 ISA Fast EtherLink XL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 3Com's ISA bus adapter for Fast Ethernet. Due to the unique I/O port layout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) it's not practical to integrate this driver with the other EtherLink drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) II. Board-specific settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) The Corkscrew has an EEPROM for configuration, but no special settings are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) needed for Linux.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) III. Driver operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) The 3c515 series use an interface that's very similar to the 3c900 "Boomerang"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PCI cards, with the bus master interface extensively modified to work with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) the ISA bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) The card is capable of full-bus-master transfers with separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) lists of transmit and receive descriptors, similar to the AMD LANCE/PCnet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) DEC Tulip and Intel Speedo3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) This driver uses a "RX_COPYBREAK" scheme rather than a fixed intermediate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) receive buffer. This scheme allocates full-sized skbuffs as receive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) buffers. The value RX_COPYBREAK is used as the copying breakpoint: it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) chosen to trade-off the memory wasted by passing the full-sized skbuff to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) the queue layer for all frames vs. the copying cost of copying a frame to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) correctly-sized skbuff.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) IIIC. Synchronization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) The driver runs as two independent, single-threaded flows of control. One
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) is the send-packet routine, which enforces single-threaded use by the netif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) layer. The other thread is the interrupt handler, which is single
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) threaded by the hardware and other software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) IV. Notes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) Thanks to Terry Murphy of 3Com for providing documentation and a development
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) board.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) The names "Vortex", "Boomerang" and "Corkscrew" are the internal 3Com
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) project names. I use these names to eliminate confusion -- 3Com product
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) numbers and names are very similar and often confused.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) The new chips support both ethernet (1.5K) and FDDI (4.5K) frame sizes!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) This driver only supports ethernet frames because of the recent MTU limit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) of 1.5K, but the changes to support 4.5K are minimal.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* Operational definitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) These are not used by other compilation units and thus are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) exported in a ".h" file.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) First the windows. There are eight register windows, with the command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) and status registers available in each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EL3WINDOW(win_num) outw(SelectWindow + (win_num), ioaddr + EL3_CMD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EL3_CMD 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EL3_STATUS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* The top five bits written to EL3_CMD are a command, the lower
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 11 bits are the parameter, if applicable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) Note that 11 parameters bits was fine for ethernet, but the new chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) can handle FDDI length frames (~4500 octets) and now parameters count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 32-bit 'Dwords' rather than octets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) enum corkscrew_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) TotalReset = 0 << 11, SelectWindow = 1 << 11, StartCoax = 2 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) RxDisable = 3 << 11, RxEnable = 4 << 11, RxReset = 5 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) UpStall = 6 << 11, UpUnstall = (6 << 11) + 1, DownStall = (6 << 11) + 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) DownUnstall = (6 << 11) + 3, RxDiscard = 8 << 11, TxEnable = 9 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) TxDisable = 10 << 11, TxReset = 11 << 11, FakeIntr = 12 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) AckIntr = 13 << 11, SetIntrEnb = 14 << 11, SetStatusEnb = 15 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) SetRxFilter = 16 << 11, SetRxThreshold = 17 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) SetTxThreshold = 18 << 11, SetTxStart = 19 << 11, StartDMAUp = 20 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) StartDMADown = (20 << 11) + 1, StatsEnable = 21 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) StatsDisable = 22 << 11, StopCoax = 23 << 11,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* The SetRxFilter command accepts the following classes: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum RxFilter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* Bits in the general status register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) enum corkscrew_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) IntLatch = 0x0001, AdapterFailure = 0x0002, TxComplete = 0x0004,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IntReq = 0x0040, StatsFull = 0x0080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) DMADone = 1 << 8, DownComplete = 1 << 9, UpComplete = 1 << 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) DMAInProgress = 1 << 11, /* DMA controller is still busy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) CmdInProgress = 1 << 12, /* EL3_CMD is still busy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Register window 1 offsets, the window used in normal operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) On the Corkscrew this window is always mapped at offsets 0x10-0x1f. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) enum Window1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) RxStatus = 0x18, Timer = 0x1A, TxStatus = 0x1B,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) TxFree = 0x1C, /* Remaining free bytes in Tx buffer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) enum Window0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) Wn0IRQ = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #if defined(CORKSCREW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) Wn0EepromCmd = 0x200A, /* Corkscrew EEPROM command register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) Wn0EepromData = 0x200C, /* Corkscrew EEPROM results register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) Wn0EepromCmd = 10, /* Window 0: EEPROM command register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) Wn0EepromData = 12, /* Window 0: EEPROM results register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum Win0_EEPROM_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) EEPROM_EWENB = 0x30, /* Enable erasing/writing for 10 msec. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) EEPROM_EWDIS = 0x00, /* Disable EWENB before 10 msec timeout. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* EEPROM locations. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum eeprom_offset {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) PhysAddr01 = 0, PhysAddr23 = 1, PhysAddr45 = 2, ModelID = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) EtherLink3ID = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum Window3 { /* Window 3: MAC/config bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) Wn3_Config = 0, Wn3_MAC_Ctrl = 6, Wn3_Options = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) enum wn3_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) Ram_size = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) Ram_width = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) Ram_speed = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) Rom_size = 0xc0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) Ram_split_shift = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) Ram_split = 3 << Ram_split_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) Xcvr_shift = 20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) Xcvr = 7 << Xcvr_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) Autoselect = 0x1000000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) enum Window4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) Wn4_NetDiag = 6, Wn4_Media = 10, /* Window 4: Xcvr/media bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum Win4_Media_bits {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) Media_SQE = 0x0008, /* Enable SQE error counting for AUI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) Media_10TP = 0x00C0, /* Enable link beat and jabber for 10baseT. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) Media_Lnk = 0x0080, /* Enable just link beat for 100TX/100FX. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) Media_LnkBeat = 0x0800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum Window7 { /* Window 7: Bus Master control. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) Wn7_MasterAddr = 0, Wn7_MasterLen = 6, Wn7_MasterStatus = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Boomerang-style bus master control registers. Note ISA aliases! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) enum MasterCtrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PktStatus = 0x400, DownListPtr = 0x404, FragAddr = 0x408, FragLen =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 0x40c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) TxFreeThreshold = 0x40f, UpPktStatus = 0x410, UpListPtr = 0x418,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* The Rx and Tx descriptor lists.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) Caution Alpha hackers: these types are 32 bits! Note also the 8 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) alignment contraint on tx_ring[] and rx_ring[]. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct boom_rx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) s32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) s32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Values for the Rx status entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) enum rx_desc_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) RxDComplete = 0x00008000, RxDError = 0x4000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* See boomerang_rx() for actual error bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct boom_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) s32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) s32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct corkscrew_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) const char *product_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct net_device *our_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* The Rx and Tx rings are here to keep them quad-word-aligned. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct boom_rx_desc rx_ring[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct boom_tx_desc tx_ring[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* The addresses of transmit- and receive-in-place skbuffs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct sk_buff *rx_skbuff[RX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct sk_buff *tx_skbuff[TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) unsigned int cur_rx, cur_tx; /* The next free ring entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) unsigned int dirty_rx, dirty_tx;/* The ring entries to be free()ed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct sk_buff *tx_skb; /* Packet being eaten by bus master ctrl. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct timer_list timer; /* Media selection timer. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int capabilities ; /* Adapter capabilities word. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int options; /* User-settable misc. driver options. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int last_rx_packets; /* For media autoselection. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) unsigned int available_media:8, /* From Wn3_Options */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) media_override:3, /* Passed-in media type. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) default_media:3, /* Read from the EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) full_duplex:1, autoselect:1, bus_master:1, /* Vortex can only do a fragment bus-m. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) full_bus_master_tx:1, full_bus_master_rx:1, /* Boomerang */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tx_full:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* The action to take with a media selection timer tick.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) Note that we deviate from the 3Com order by checking 10base2 before AUI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) enum xcvr_types {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) XCVR_10baseT = 0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) XCVR_100baseFx, XCVR_MII = 6, XCVR_Default = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static struct media_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) mask:8, /* The transceiver-present bit in Wn3_Config. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) next:8; /* The media type to try next. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) short wait; /* Time before we check media status. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) } media_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) { "10baseT", Media_10TP, 0x08, XCVR_10base2, (14 * HZ) / 10 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1 * HZ) / 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) { "undefined", 0, 0x80, XCVR_10baseT, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) { "10base2", 0, 0x10, XCVR_AUI, (1 * HZ) / 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14 * HZ) / 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14 * HZ) / 10},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) { "MII", 0, 0x40, XCVR_10baseT, 3 * HZ},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) { "undefined", 0, 0x01, XCVR_10baseT, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) { "Default", 0, 0xFF, XCVR_10baseT, 10000},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #ifdef __ISAPNP__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) static struct isapnp_device_id corkscrew_isapnp_adapters[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) { ISAPNP_ANY_ID, ISAPNP_ANY_ID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ISAPNP_VENDOR('T', 'C', 'M'), ISAPNP_FUNCTION(0x5051),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) (long) "3Com Fast EtherLink ISA" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) { } /* terminate list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) MODULE_DEVICE_TABLE(isapnp, corkscrew_isapnp_adapters);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static int nopnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #endif /* __ISAPNP__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static struct net_device *corkscrew_scan(int unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) static int corkscrew_setup(struct net_device *dev, int ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct pnp_dev *idev, int card_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) static int corkscrew_open(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) static void corkscrew_timer(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static netdev_tx_t corkscrew_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) static int corkscrew_rx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void corkscrew_timeout(struct net_device *dev, unsigned int txqueue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int boomerang_rx(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static irqreturn_t corkscrew_interrupt(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int corkscrew_close(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) static void update_stats(int addr, struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static struct net_device_stats *corkscrew_get_stats(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static void set_rx_mode(struct net_device *dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) static const struct ethtool_ops netdev_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) Unfortunately maximizing the shared code between the integrated and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) module version of the driver results in a complicated set of initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) procedures.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) init_module() -- modules / tc59x_init() -- built-in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) The wrappers for corkscrew_scan()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) corkscrew_scan() The common routine that scans for PCI and EISA cards
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) corkscrew_found_device() Allocate a device structure when we find a card.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) Different versions exist for modules and built-in.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) corkscrew_probe1() Fill in the device structure -- this is separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) so that the modules code can put it in dev->init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* This driver uses 'options' to pass the media type, full-duplex flag, etc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Note: this is the only limit on the number of cards supported!! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static int options[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) static int debug = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) module_param(debug, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) module_param_array(options, int, NULL, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) module_param(rx_copybreak, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) module_param(max_interrupt_work, int, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) MODULE_PARM_DESC(debug, "3c515 debug level (0-6)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) MODULE_PARM_DESC(options, "3c515: Bits 0-2: media type, bit 3: full duplex, bit 4: bus mastering");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) MODULE_PARM_DESC(rx_copybreak, "3c515 copy breakpoint for copy-only-tiny-frames");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) MODULE_PARM_DESC(max_interrupt_work, "3c515 maximum events handled per interrupt");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /* A list of all installed Vortex devices, for removing the driver module. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* we will need locking (and refcounting) if we ever use it for more */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static LIST_HEAD(root_corkscrew_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int init_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (debug >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) corkscrew_debug = debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) while (corkscrew_scan(-1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) found++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return found ? 0 : -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct net_device *tc515_probe(int unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct net_device *dev = corkscrew_scan(unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return ERR_PTR(-ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #endif /* not MODULE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static int check_device(unsigned ioaddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) int timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (!request_region(ioaddr, CORKSCREW_TOTAL_SIZE, "3c515"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Check the resource configuration for a matching ioaddr. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if ((inw(ioaddr + 0x2002) & 0x1f0) != (ioaddr & 0x1f0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) release_region(ioaddr, CORKSCREW_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Verify by reading the device ID from the EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) outw(EEPROM_Read + 7, ioaddr + Wn0EepromCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* Pause for at least 162 us. for the read to take place. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) for (timer = 4; timer >= 0; timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) udelay(162);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (inw(ioaddr + Wn0EepromData) != 0x6d50) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) release_region(ioaddr, CORKSCREW_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static void cleanup_card(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) list_del_init(&vp->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) if (dev->dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) free_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) outw(TotalReset, dev->base_addr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) release_region(dev->base_addr, CORKSCREW_TOTAL_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (vp->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) pnp_device_detach(to_pnp_dev(vp->dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static struct net_device *corkscrew_scan(int unit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) static int cards_found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static int ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #ifdef __ISAPNP__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) short i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) static int pnp_cards;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev = alloc_etherdev(sizeof(struct corkscrew_private));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (unit >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) sprintf(dev->name, "eth%d", unit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) netdev_boot_setup_check(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #ifdef __ISAPNP__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if(nopnp == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) goto no_pnp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) for(i=0; corkscrew_isapnp_adapters[i].vendor != 0; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) struct pnp_dev *idev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) while((idev = pnp_find_dev(NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) corkscrew_isapnp_adapters[i].vendor,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) corkscrew_isapnp_adapters[i].function,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) idev))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (pnp_device_attach(idev) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (pnp_activate_dev(idev) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) pr_warn("pnp activate failed (out of resources?)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) pnp_device_detach(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (!pnp_port_valid(idev, 0) || !pnp_irq_valid(idev, 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pnp_device_detach(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) ioaddr = pnp_port_start(idev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) irq = pnp_irq(idev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (!check_device(ioaddr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) pnp_device_detach(idev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if(corkscrew_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) pr_debug("ISAPNP reports %s at i/o 0x%x, irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) (char*) corkscrew_isapnp_adapters[i].driver_data, ioaddr, irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) pr_info("3c515 Resource configuration register %#4.4x, DCR %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) inl(ioaddr + 0x2002), inw(ioaddr + 0x2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* irq = inw(ioaddr + 0x2002) & 15; */ /* Use the irq from isapnp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) SET_NETDEV_DEV(dev, &idev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) pnp_cards++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) err = corkscrew_setup(dev, ioaddr, idev, cards_found++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) cleanup_card(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) no_pnp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #endif /* __ISAPNP__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Check all locations on the ISA bus -- evil! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) for (ioaddr = 0x100; ioaddr < 0x400; ioaddr += 0x20) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!check_device(ioaddr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) pr_info("3c515 Resource configuration register %#4.4x, DCR %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) inl(ioaddr + 0x2002), inw(ioaddr + 0x2000));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err = corkscrew_setup(dev, ioaddr, NULL, cards_found++);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cleanup_card(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) static const struct net_device_ops netdev_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) .ndo_open = corkscrew_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) .ndo_stop = corkscrew_close,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .ndo_start_xmit = corkscrew_start_xmit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .ndo_tx_timeout = corkscrew_timeout,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .ndo_get_stats = corkscrew_get_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .ndo_set_rx_mode = set_rx_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) .ndo_set_mac_address = eth_mac_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) .ndo_validate_addr = eth_validate_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) static int corkscrew_setup(struct net_device *dev, int ioaddr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct pnp_dev *idev, int card_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned int eeprom[0x40], checksum = 0; /* EEPROM contents */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #ifdef __ISAPNP__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) if (idev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) irq = pnp_irq(idev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) vp->dev = &idev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) irq = inw(ioaddr + 0x2002) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) irq = inw(ioaddr + 0x2002) & 15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev->base_addr = ioaddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) dev->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) dev->dma = inw(ioaddr + 0x2000) & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) vp->product_name = "3c515";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) vp->options = dev->mem_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) vp->our_dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (!vp->options) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (card_number >= MAX_UNITS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) vp->options = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) vp->options = options[card_number];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) if (vp->options >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) vp->media_override = vp->options & 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) if (vp->media_override == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) vp->media_override = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) vp->full_duplex = (vp->options & 8) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) vp->bus_master = (vp->options & 16) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) vp->media_override = 7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) vp->full_duplex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) vp->bus_master = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) list_add(&vp->list, &root_corkscrew_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) pr_info("%s: 3Com %s at %#3x,", dev->name, vp->product_name, ioaddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) spin_lock_init(&vp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) timer_setup(&vp->timer, corkscrew_timer, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /* Read the station address from the EEPROM. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) EL3WINDOW(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (i = 0; i < 0x18; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) __be16 *phys_addr = (__be16 *) dev->dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) int timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) outw(EEPROM_Read + i, ioaddr + Wn0EepromCmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) /* Pause for at least 162 us. for the read to take place. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) for (timer = 4; timer >= 0; timer--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) udelay(162);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) if ((inw(ioaddr + Wn0EepromCmd) & 0x0200) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) eeprom[i] = inw(ioaddr + Wn0EepromData);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) checksum ^= eeprom[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) if (i < 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) phys_addr[i] = htons(eeprom[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) checksum = (checksum ^ (checksum >> 8)) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (checksum != 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) pr_cont(" %pM", dev->dev_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (eeprom[16] == 0x11c7) { /* Corkscrew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (request_dma(dev->dma, "3c515")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) pr_cont(", DMA %d allocation failed", dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) dev->dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) pr_cont(", DMA %d", dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) pr_cont(", IRQ %d\n", dev->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /* Tell them about an invalid IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (corkscrew_debug && (dev->irq <= 0 || dev->irq > 15))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) pr_warn(" *** Warning: this IRQ is unlikely to work! ***\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static const char * const ram_split[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) "5:3", "3:1", "1:1", "3:5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) __u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) EL3WINDOW(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) vp->available_media = inw(ioaddr + Wn3_Options);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) config = inl(ioaddr + Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) pr_info(" Internal config register is %4.4x, transceivers %#x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) config, inw(ioaddr + Wn3_Options));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) 8 << config & Ram_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) config & Ram_width ? "word" : "byte",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ram_split[(config & Ram_split) >> Ram_split_shift],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) config & Autoselect ? "autoselect/" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) media_tbl[(config & Xcvr) >> Xcvr_shift].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) vp->default_media = (config & Xcvr) >> Xcvr_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) vp->autoselect = config & Autoselect ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dev->if_port = vp->default_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) if (vp->media_override != 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) pr_info(" Media override to transceiver type %d (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) vp->media_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) media_tbl[vp->media_override].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev->if_port = vp->media_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) vp->capabilities = eeprom[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) vp->full_bus_master_tx = (vp->capabilities & 0x20) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /* Rx is broken at 10mbps, so we always disable it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) /* vp->full_bus_master_rx = 0; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) vp->full_bus_master_rx = (vp->capabilities & 0x20) ? 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* The 3c51x-specific entries in the device structure. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) dev->netdev_ops = &netdev_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) dev->watchdog_timeo = (400 * HZ) / 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) dev->ethtool_ops = &netdev_ethtool_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return register_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static int corkscrew_open(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) bool armtimer = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) __u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* Before initializing select the active media port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) EL3WINDOW(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) if (vp->full_duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) outb(0x20, ioaddr + Wn3_MAC_Ctrl); /* Set the full-duplex bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) config = inl(ioaddr + Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (vp->media_override != 7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) pr_info("%s: Media override to transceiver %d (%s).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) dev->name, vp->media_override,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) media_tbl[vp->media_override].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev->if_port = vp->media_override;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) } else if (vp->autoselect) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /* Find first available media type, starting with 100baseTx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev->if_port = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) while (!(vp->available_media & media_tbl[dev->if_port].mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) dev->if_port = media_tbl[dev->if_port].next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pr_debug("%s: Initial media type %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) armtimer = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) dev->if_port = vp->default_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) config = (config & ~Xcvr) | (dev->if_port << Xcvr_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) outl(config, ioaddr + Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (corkscrew_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) pr_debug("%s: corkscrew_open() InternalConfig %8.8x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) dev->name, config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) outw(TxReset, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) for (i = 20; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) outw(RxReset, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /* Wait a few ticks for the RxReset command to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) for (i = 20; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) outw(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) /* Use the now-standard shared IRQ implementation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) if (vp->capabilities == 0x11c7) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) /* Corkscrew: Cannot share ISA resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) if (dev->irq == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) dev->dma == 0 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) request_irq(dev->irq, corkscrew_interrupt, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) vp->product_name, dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) enable_dma(dev->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) set_dma_mode(dev->dma, DMA_MODE_CASCADE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) } else if (request_irq(dev->irq, corkscrew_interrupt, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) vp->product_name, dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (armtimer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) mod_timer(&vp->timer, jiffies + media_tbl[dev->if_port].wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) if (corkscrew_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) EL3WINDOW(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) pr_debug("%s: corkscrew_open() irq %d media status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) dev->name, dev->irq, inw(ioaddr + Wn4_Media));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* Set the station address and mask in window 2 each time opened. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) EL3WINDOW(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) for (i = 0; i < 6; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) outb(dev->dev_addr[i], ioaddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) for (; i < 12; i += 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) outw(0, ioaddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (dev->if_port == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /* Start the thinnet transceiver. We should really wait 50ms... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) outw(StartCoax, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) EL3WINDOW(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) outw((inw(ioaddr + Wn4_Media) & ~(Media_10TP | Media_SQE)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) media_tbl[dev->if_port].media_bits, ioaddr + Wn4_Media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) /* Switch to the stats window, and clear all stats by reading. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) outw(StatsDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) EL3WINDOW(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) for (i = 0; i < 10; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) inb(ioaddr + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) inw(ioaddr + 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) inw(ioaddr + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /* New: On the Vortex we must also clear the BadSSD counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) EL3WINDOW(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) inb(ioaddr + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* ..and on the Boomerang we enable the extra statistics bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) outw(0x0040, ioaddr + Wn4_NetDiag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /* Switch to register set 7 for normal use. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) EL3WINDOW(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) if (vp->full_bus_master_rx) { /* Boomerang bus master. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) vp->cur_rx = vp->dirty_rx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (corkscrew_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) pr_debug("%s: Filling in the Rx ring.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) for (i = 0; i < RX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (i < (RX_RING_SIZE - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) vp->rx_ring[i].next =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) isa_virt_to_bus(&vp->rx_ring[i + 1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) vp->rx_ring[i].next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) vp->rx_ring[i].status = 0; /* Clear complete bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) vp->rx_ring[i].length = PKT_BUF_SZ | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) vp->rx_skbuff[i] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) break; /* Bad news! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) vp->rx_ring[i].addr = isa_virt_to_bus(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (i != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) vp->rx_ring[i - 1].next =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) isa_virt_to_bus(&vp->rx_ring[0]); /* Wrap the ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) outl(isa_virt_to_bus(&vp->rx_ring[0]), ioaddr + UpListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (vp->full_bus_master_tx) { /* Boomerang bus master Tx. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) vp->cur_tx = vp->dirty_tx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) outb(PKT_BUF_SZ >> 8, ioaddr + TxFreeThreshold); /* Room for a packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Clear the Tx ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) vp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) outl(0, ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /* Set receiver mode: presumably accept b-case and phys addr only. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) outw(StatsEnable, ioaddr + EL3_CMD); /* Turn on statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) netif_start_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) outw(RxEnable, ioaddr + EL3_CMD); /* Enable the receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) outw(TxEnable, ioaddr + EL3_CMD); /* Enable transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) /* Allow status bits to be seen. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) outw(SetStatusEnb | AdapterFailure | IntReq | StatsFull |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) (vp->full_bus_master_rx ? UpComplete : RxComplete) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) (vp->bus_master ? DMADone : 0), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /* Ack all pending events, and set active indicator mask. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) outw(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) outw(SetIntrEnb | IntLatch | TxAvailable | RxComplete | StatsFull
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) static void corkscrew_timer(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) #ifdef AUTOMEDIA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct corkscrew_private *vp = from_timer(vp, t, timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct net_device *dev = vp->our_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int ok = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) pr_debug("%s: Media selection timer tick happened, %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) spin_lock_irqsave(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int old_window = inw(ioaddr + EL3_CMD) >> 13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int media_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) EL3WINDOW(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) media_status = inw(ioaddr + Wn4_Media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) switch (dev->if_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) case 0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) case 5: /* 10baseT, 100baseTX, 100baseFX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (media_status & Media_LnkBeat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) pr_debug("%s: Media %s has link beat, %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) media_tbl[dev->if_port].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) media_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) } else if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) pr_debug("%s: Media %s is has no link beat, %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) media_tbl[dev->if_port].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) media_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) default: /* Other media types handled by Tx timeouts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) pr_debug("%s: Media %s is has no indication, %x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) media_tbl[dev->if_port].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) media_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) ok = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (!ok) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) __u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) dev->if_port =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) media_tbl[dev->if_port].next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) while (!(vp->available_media & media_tbl[dev->if_port].mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (dev->if_port == 8) { /* Go back to default. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dev->if_port = vp->default_media;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) pr_debug("%s: Media selection failing, using default %s port.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) pr_debug("%s: Media selection failed, now trying %s port.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) vp->timer.expires = jiffies + media_tbl[dev->if_port].wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) add_timer(&vp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) outw((media_status & ~(Media_10TP | Media_SQE)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) media_tbl[dev->if_port].media_bits,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) ioaddr + Wn4_Media);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) EL3WINDOW(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) config = inl(ioaddr + Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) config = (config & ~Xcvr) | (dev->if_port << Xcvr_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) outl(config, ioaddr + Wn3_Config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) outw(dev->if_port == 3 ? StartCoax : StopCoax,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) EL3WINDOW(old_window);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) spin_unlock_irqrestore(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) if (corkscrew_debug > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) pr_debug("%s: Media selection timer finished, %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) dev->name, media_tbl[dev->if_port].name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif /* AUTOMEDIA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static void corkscrew_timeout(struct net_device *dev, unsigned int txqueue)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) pr_warn("%s: transmit timed out, tx_status %2.2x status %4.4x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) dev->name, inb(ioaddr + TxStatus),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) inw(ioaddr + EL3_STATUS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) /* Slight code bloat to be user friendly. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) if ((inb(ioaddr + TxStatus) & 0x88) == 0x88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) pr_warn("%s: Transmitter encountered 16 collisions -- network cable problem?\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) #ifndef final_version
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) pr_debug(" Flags; bus-master %d, full %d; dirty %d current %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) vp->full_bus_master_tx, vp->tx_full, vp->dirty_tx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) vp->cur_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pr_debug(" Down list %8.8x vs. %p.\n", inl(ioaddr + DownListPtr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) &vp->tx_ring[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (i = 0; i < TX_RING_SIZE; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) pr_debug(" %d: %p length %8.8x status %8.8x\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) &vp->tx_ring[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) vp->tx_ring[i].length, vp->tx_ring[i].status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) /* Issue TX_RESET and TX_START commands. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) outw(TxReset, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) for (i = 20; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) outw(TxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) netif_trans_update(dev); /* prevent tx timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dev->stats.tx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) dev->stats.tx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) static netdev_tx_t corkscrew_start_xmit(struct sk_buff *skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) /* Block a timer-based transmit from overlapping. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (vp->full_bus_master_tx) { /* BOOMERANG bus-master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) /* Calculate the next Tx descriptor entry. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) int entry = vp->cur_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct boom_tx_desc *prev_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) if (vp->tx_full) /* No room to transmit with */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) return NETDEV_TX_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (vp->cur_tx != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) prev_entry = &vp->tx_ring[(vp->cur_tx - 1) % TX_RING_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) prev_entry = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (corkscrew_debug > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) pr_debug("%s: Trying to send a packet, Tx index %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) dev->name, vp->cur_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) /* vp->tx_full = 1; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) vp->tx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) vp->tx_ring[entry].next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) vp->tx_ring[entry].addr = isa_virt_to_bus(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) vp->tx_ring[entry].length = skb->len | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) vp->tx_ring[entry].status = skb->len | 0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) spin_lock_irqsave(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) outw(DownStall, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) /* Wait for the stall to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) for (i = 20; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) if ((inw(ioaddr + EL3_STATUS) & CmdInProgress) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) if (prev_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) prev_entry->next = isa_virt_to_bus(&vp->tx_ring[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) if (inl(ioaddr + DownListPtr) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) outl(isa_virt_to_bus(&vp->tx_ring[entry]),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) queued_packet++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) outw(DownUnstall, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) spin_unlock_irqrestore(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) vp->cur_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) vp->tx_full = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) else { /* Clear previous interrupt enable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) if (prev_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) prev_entry->status &= ~0x80000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) /* Put out the doubleword header... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) outl(skb->len, ioaddr + TX_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) dev->stats.tx_bytes += skb->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) #ifdef VORTEX_BUS_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (vp->bus_master) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) /* Set the bus-master controller to transfer the packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) outl((int) (skb->data), ioaddr + Wn7_MasterAddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) outw((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) vp->tx_skb = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) outw(StartDMADown, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* queue will be woken at the DMADone interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* ... and the packet rounded to a doubleword. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (inw(ioaddr + TxFree) > 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /* Interrupt us when the FIFO has room for max-sized packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) outw(SetTxThreshold + (1536 >> 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) /* ... and the packet rounded to a doubleword. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) outsl(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) dev_kfree_skb(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) if (inw(ioaddr + TxFree) > 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) /* Interrupt us when the FIFO has room for max-sized packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) outw(SetTxThreshold + (1536 >> 2), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) #endif /* bus master */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) /* Clear the Tx status stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) short tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) int i = 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) while (--i > 0 && (tx_status = inb(ioaddr + TxStatus)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (tx_status & 0x3C) { /* A Tx-disabling error occurred. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (corkscrew_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) pr_debug("%s: Tx error, status %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) dev->name, tx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (tx_status & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dev->stats.tx_fifo_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) if (tx_status & 0x38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) dev->stats.tx_aborted_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (tx_status & 0x30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) int j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) outw(TxReset, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) for (j = 20; j >= 0; j--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) outw(TxEnable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) outb(0x00, ioaddr + TxStatus); /* Pop the status stack. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) return NETDEV_TX_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) /* The interrupt handler does all of the Rx thread work and cleans up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) after the Tx thread. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static irqreturn_t corkscrew_interrupt(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /* Use the now-standard shared IRQ implementation. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) struct net_device *dev = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct corkscrew_private *lp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int ioaddr, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) int latency;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int i = max_interrupt_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) latency = inb(ioaddr + Timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) spin_lock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) status = inw(ioaddr + EL3_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (corkscrew_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pr_debug("%s: interrupt, status %4.4x, timer %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev->name, status, latency);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if ((status & 0xE000) != 0xE000) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) static int donedidthis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* Some interrupt controllers store a bogus interrupt from boot-time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) Ignore a single early interrupt, but don't hang the machine for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) other interrupt problems. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (donedidthis++ > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) pr_err("%s: Bogus interrupt, bailing. Status %4.4x, start=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev->name, status, netif_running(dev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dev->irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (corkscrew_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) pr_debug("%s: In interrupt loop, status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (status & RxComplete)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) corkscrew_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) if (status & TxAvailable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (corkscrew_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) pr_debug(" TX room bit was handled.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* There's room in the FIFO for a full-sized packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) outw(AckIntr | TxAvailable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (status & DownComplete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) unsigned int dirty_tx = lp->dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) while (lp->cur_tx - dirty_tx > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) int entry = dirty_tx % TX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if (inl(ioaddr + DownListPtr) == isa_virt_to_bus(&lp->tx_ring[entry]))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) break; /* It still hasn't been processed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (lp->tx_skbuff[entry]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) dev_consume_skb_irq(lp->tx_skbuff[entry]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) lp->tx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) dirty_tx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) lp->dirty_tx = dirty_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) outw(AckIntr | DownComplete, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (lp->tx_full && (lp->cur_tx - dirty_tx <= TX_RING_SIZE - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) lp->tx_full = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) #ifdef VORTEX_BUS_MASTER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) if (status & DMADone) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) outw(0x1000, ioaddr + Wn7_MasterStatus); /* Ack the event. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) dev_consume_skb_irq(lp->tx_skb); /* Release the transferred buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) netif_wake_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) if (status & UpComplete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) boomerang_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) outw(AckIntr | UpComplete, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (status & (AdapterFailure | RxEarly | StatsFull)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* Handle all uncommon interrupts at once. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) if (status & RxEarly) { /* Rx early is unused. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) corkscrew_rx(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) outw(AckIntr | RxEarly, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (status & StatsFull) { /* Empty statistics. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int DoneDidThat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) if (corkscrew_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pr_debug("%s: Updating stats.\n", dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) update_stats(ioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) /* DEBUG HACK: Disable statistics as an interrupt source. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) /* This occurs when we have the wrong media type! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (DoneDidThat == 0 && inw(ioaddr + EL3_STATUS) & StatsFull) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) int win, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) pr_notice("%s: Updating stats failed, disabling stats as an interrupt source.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) for (win = 0; win < 8; win++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) EL3WINDOW(win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) pr_notice("Vortex window %d:", win);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) for (reg = 0; reg < 16; reg++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pr_cont(" %2.2x", inb(ioaddr + reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) pr_cont("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) EL3WINDOW(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) outw(SetIntrEnb | TxAvailable |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) RxComplete | AdapterFailure |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) UpComplete | DownComplete |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) TxComplete, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) DoneDidThat++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (status & AdapterFailure) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) /* Adapter failure requires Rx reset and reinit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) outw(RxReset, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) /* Set the Rx filter to the current state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) set_rx_mode(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) outw(RxEnable, ioaddr + EL3_CMD); /* Re-enable the receiver. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) outw(AckIntr | AdapterFailure,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (--i < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) pr_err("%s: Too much work in interrupt, status %4.4x. Disabling functions (%4.4x).\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev->name, status, SetStatusEnb | ((~status) & 0x7FE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) /* Disable all pending interrupts. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) outw(SetStatusEnb | ((~status) & 0x7FE), ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) outw(AckIntr | 0x7FF, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* Acknowledge the IRQ. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) outw(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) } while ((status = inw(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) spin_unlock(&lp->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (corkscrew_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) pr_debug("%s: exiting interrupt, status %4.4x.\n", dev->name, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static int corkscrew_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) short rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) if (corkscrew_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) pr_debug(" In rx_packet(), status %4.4x, rx_status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) inw(ioaddr + EL3_STATUS), inw(ioaddr + RxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) while ((rx_status = inw(ioaddr + RxStatus)) > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) if (rx_status & 0x4000) { /* Error, update stats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) unsigned char rx_error = inb(ioaddr + RxErrors);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (corkscrew_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) pr_debug(" Rx error: status %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) rx_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (rx_error & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) if (rx_error & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) if (rx_error & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) if (rx_error & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (rx_error & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) /* The packet length: up to 4.5K!. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) short pkt_len = rx_status & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) skb = netdev_alloc_skb(dev, pkt_len + 5 + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (corkscrew_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) pr_debug("Receiving packet size %d status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) pkt_len, rx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) if (skb != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) /* 'skb_put()' points to the start of sk_buff data area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) insl(ioaddr + RX_FIFO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) skb_put(skb, pkt_len),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) (pkt_len + 3) >> 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) outw(RxDiscard, ioaddr + EL3_CMD); /* Pop top Rx packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) dev->stats.rx_bytes += pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) /* Wait a limited time to go to next packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) for (i = 200; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (! (inw(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) } else if (corkscrew_debug)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) pr_debug("%s: Couldn't allocate a sk_buff of size %d.\n", dev->name, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) outw(RxDiscard, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) dev->stats.rx_dropped++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) /* Wait a limited time to skip this packet. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) for (i = 200; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) if (!(inw(ioaddr + EL3_STATUS) & CmdInProgress))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static int boomerang_rx(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) int entry = vp->cur_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) int rx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (corkscrew_debug > 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) pr_debug(" In boomerang_rx(), status %4.4x, rx_status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) inw(ioaddr + EL3_STATUS), inw(ioaddr + RxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) while ((rx_status = vp->rx_ring[entry].status) & RxDComplete) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) if (rx_status & RxDError) { /* Error, update stats. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) unsigned char rx_error = rx_status >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) if (corkscrew_debug > 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) pr_debug(" Rx error: status %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) rx_error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dev->stats.rx_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) if (rx_error & 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) dev->stats.rx_over_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) if (rx_error & 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) if (rx_error & 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) dev->stats.rx_frame_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (rx_error & 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev->stats.rx_crc_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) if (rx_error & 0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) dev->stats.rx_length_errors++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) /* The packet length: up to 4.5K!. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) short pkt_len = rx_status & 0x1fff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dev->stats.rx_bytes += pkt_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) if (corkscrew_debug > 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) pr_debug("Receiving packet size %d status %4.4x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) pkt_len, rx_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) /* Check if the packet is long enough to just accept without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) copying to a properly sized skbuff. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) if (pkt_len < rx_copybreak &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) (skb = netdev_alloc_skb(dev, pkt_len + 4)) != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* 'skb_put()' points to the start of sk_buff data area. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) skb_put_data(skb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) isa_bus_to_virt(vp->rx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) rx_copy++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) void *temp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) /* Pass up the skbuff already on the Rx ring. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) skb = vp->rx_skbuff[entry];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) vp->rx_skbuff[entry] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) temp = skb_put(skb, pkt_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* Remove this checking code for final release. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) if (isa_bus_to_virt(vp->rx_ring[entry].addr) != temp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) pr_warn("%s: Warning -- the skbuff addresses do not match in boomerang_rx: %p vs. %p / %p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) dev->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) isa_bus_to_virt(vp->rx_ring[entry].addr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) skb->head, temp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) rx_nocopy++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) skb->protocol = eth_type_trans(skb, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) netif_rx(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dev->stats.rx_packets++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) entry = (++vp->cur_rx) % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) /* Refill the Rx ring buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) for (; vp->cur_rx - vp->dirty_rx > 0; vp->dirty_rx++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct sk_buff *skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) entry = vp->dirty_rx % RX_RING_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (vp->rx_skbuff[entry] == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) skb = netdev_alloc_skb(dev, PKT_BUF_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (skb == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) break; /* Bad news! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) skb_reserve(skb, 2); /* Align IP on 16 byte boundaries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) vp->rx_ring[entry].addr = isa_virt_to_bus(skb->data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) vp->rx_skbuff[entry] = skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) vp->rx_ring[entry].status = 0; /* Clear complete bit. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) static int corkscrew_close(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) netif_stop_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (corkscrew_debug > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) pr_debug("%s: corkscrew_close() status %4.4x, Tx status %2.2x.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev->name, inw(ioaddr + EL3_STATUS),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) inb(ioaddr + TxStatus));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) pr_debug("%s: corkscrew close stats: rx_nocopy %d rx_copy %d tx_queued %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev->name, rx_nocopy, rx_copy, queued_packet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) del_timer_sync(&vp->timer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) /* Turn off statistics ASAP. We update lp->stats below. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) outw(StatsDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /* Disable the receiver and transmitter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) outw(RxDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) outw(TxDisable, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (dev->if_port == XCVR_10base2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) /* Turn off thinnet power. Green! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) outw(StopCoax, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) outw(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) update_stats(ioaddr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) if (vp->full_bus_master_rx) { /* Free Boomerang bus master Rx buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) outl(0, ioaddr + UpListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) for (i = 0; i < RX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) if (vp->rx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) dev_kfree_skb(vp->rx_skbuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) vp->rx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) if (vp->full_bus_master_tx) { /* Free Boomerang bus master Tx buffers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) outl(0, ioaddr + DownListPtr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) for (i = 0; i < TX_RING_SIZE; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (vp->tx_skbuff[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_kfree_skb(vp->tx_skbuff[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) vp->tx_skbuff[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static struct net_device_stats *corkscrew_get_stats(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) struct corkscrew_private *vp = netdev_priv(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (netif_running(dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) spin_lock_irqsave(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) update_stats(dev->base_addr, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) spin_unlock_irqrestore(&vp->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return &dev->stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Update statistics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) Unlike with the EL3 we need not worry about interrupts changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) the window setting from underneath us, but we must still guard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) against a race condition with a StatsUpdate interrupt updating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) table. This is done by checking that the ASM (!) code generated uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) atomic updates with '+='.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) static void update_stats(int ioaddr, struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) /* Unlike the 3c5x9 we need not turn off stats updates while reading. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Switch to the stats window, and read everything. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) EL3WINDOW(6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) dev->stats.tx_carrier_errors += inb(ioaddr + 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) dev->stats.tx_heartbeat_errors += inb(ioaddr + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* Multiple collisions. */ inb(ioaddr + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) dev->stats.collisions += inb(ioaddr + 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) dev->stats.tx_window_errors += inb(ioaddr + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) dev->stats.rx_fifo_errors += inb(ioaddr + 5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) dev->stats.tx_packets += inb(ioaddr + 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) dev->stats.tx_packets += (inb(ioaddr + 9) & 0x30) << 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /* Rx packets */ inb(ioaddr + 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) /* Must read to clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) /* Tx deferrals */ inb(ioaddr + 8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) /* Don't bother with register 9, an extension of registers 6&7.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) If we do use the 6&7 values the atomic update assumption above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) is invalid. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) inw(ioaddr + 10); /* Total Rx and Tx octets. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) inw(ioaddr + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) /* New: On the Vortex we must also clear the BadSSD counter. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) EL3WINDOW(4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) inb(ioaddr + 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) /* We change back to window 7 (not 1) with the Vortex. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) EL3WINDOW(7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) /* This new version of set_rx_mode() supports v1.4 kernels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) The Vortex chip has no documented multicast filter, so the only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) multicast setting is to receive all multicast frames. At least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) the chip has a very clean way to set the mode, unlike many others. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static void set_rx_mode(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) int ioaddr = dev->base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) unsigned short new_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) if (dev->flags & IFF_PROMISC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (corkscrew_debug > 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) pr_debug("%s: Setting promiscuous mode.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) new_mode = SetRxFilter | RxStation | RxMulticast | RxBroadcast | RxProm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) new_mode = SetRxFilter | RxStation | RxMulticast | RxBroadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) new_mode = SetRxFilter | RxStation | RxBroadcast;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) outw(new_mode, ioaddr + EL3_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) static void netdev_get_drvinfo(struct net_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct ethtool_drvinfo *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) snprintf(info->bus_info, sizeof(info->bus_info), "ISA 0x%lx",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev->base_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) static u32 netdev_get_msglevel(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return corkscrew_debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static void netdev_set_msglevel(struct net_device *dev, u32 level)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) corkscrew_debug = level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static const struct ethtool_ops netdev_ethtool_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .get_drvinfo = netdev_get_drvinfo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .get_msglevel = netdev_get_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .set_msglevel = netdev_set_msglevel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) #ifdef MODULE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) void cleanup_module(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) while (!list_empty(&root_corkscrew_dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct net_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct corkscrew_private *vp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) vp = list_entry(root_corkscrew_dev.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) struct corkscrew_private, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) dev = vp->our_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) unregister_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) cleanup_card(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) free_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) #endif /* MODULE */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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