Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright (c) 2018, Sensor-Technik Wiedemann GmbH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2018-2019, Vladimir Oltean <olteanv@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef _SJA1105_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define _SJA1105_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dsa/sja1105.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/dsa/8021q.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "sja1105_static_config.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define SJA1105_NUM_PORTS		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SJA1105_NUM_TC			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SJA1105ET_FDB_BIN_SIZE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) /* The hardware value is in multiples of 10 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  * The passed parameter is in multiples of 1 ms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SJA1105_AGEING_TIME_MS(ms)	((ms) / 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SJA1105_NUM_L2_POLICERS		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	SPI_READ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	SPI_WRITE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) } sja1105_spi_rw_mode_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #include "sja1105_tas.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #include "sja1105_ptp.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* Keeps the different addresses between E/T and P/Q/R/S */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) struct sja1105_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 	u64 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 	u64 prod_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	u64 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	u64 port_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u64 rgu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	u64 vl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	u64 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	u64 sgmii;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	u64 rmii_pll1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	u64 ptppinst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	u64 ptppindur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	u64 ptp_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	u64 ptpclkval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	u64 ptpclkrate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	u64 ptpclkcorp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	u64 ptpsyncts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	u64 ptpschtm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	u64 ptpegr_ts[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	u64 pad_mii_tx[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	u64 pad_mii_rx[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	u64 pad_mii_id[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 	u64 cgu_idiv[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	u64 mii_tx_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	u64 mii_rx_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	u64 mii_ext_tx_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	u64 mii_ext_rx_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	u64 rgmii_tx_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	u64 rmii_ref_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	u64 rmii_ext_tx_clk[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	u64 mac[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	u64 mac_hl1[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	u64 mac_hl2[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	u64 ether_stats[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	u64 qlevel[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct sja1105_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	u64 device_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	/* Needed for distinction between P and R, and between Q and S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 * (since the parts with/without SGMII share the same
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	 * switch core and device_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	u64 part_no;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* E/T and P/Q/R/S have partial timestamps of different sizes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	 * They must be reconstructed on both families anyway to get the full
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	 * 64-bit values back.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int ptp_ts_bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 	/* Also SPI commands are of different sizes to retrieve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	 * the egress timestamps.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	int ptpegr_ts_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	int num_cbs_shapers;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	const struct sja1105_dynamic_table_ops *dyn_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	const struct sja1105_table_ops *static_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	const struct sja1105_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	/* Both E/T and P/Q/R/S have quirks when it comes to popping the S-Tag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	 * from double-tagged frames. E/T will pop it only when it's equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	 * TPID from the General Parameters Table, while P/Q/R/S will only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	 * pop it when it's equal to TPID2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u16 qinq_tpid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	int (*reset_cmd)(struct dsa_switch *ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	int (*setup_rgmii_delay)(const void *ctx, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	/* Prototypes from include/net/dsa.h */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	int (*fdb_add_cmd)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			   const unsigned char *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	int (*fdb_del_cmd)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 			   const unsigned char *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void (*ptp_cmd_packing)(u8 *buf, struct sja1105_ptp_cmd *cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 				enum packing_op op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum sja1105_key_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	SJA1105_KEY_BCAST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	SJA1105_KEY_TC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	SJA1105_KEY_VLAN_UNAWARE_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	SJA1105_KEY_VLAN_AWARE_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct sja1105_key {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	enum sja1105_key_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 		/* SJA1105_KEY_TC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			int pcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		} tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 		/* SJA1105_KEY_VLAN_UNAWARE_VL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		/* SJA1105_KEY_VLAN_AWARE_VL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 			u64 dmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 			u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 			u16 pcp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		} vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum sja1105_rule_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	SJA1105_RULE_BCAST_POLICER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	SJA1105_RULE_TC_POLICER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	SJA1105_RULE_VL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) enum sja1105_vl_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	SJA1105_VL_NONCRITICAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	SJA1105_VL_RATE_CONSTRAINED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	SJA1105_VL_TIME_TRIGGERED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct sja1105_rule {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	unsigned long cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	unsigned long port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	struct sja1105_key key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	enum sja1105_rule_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	/* Action */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		/* SJA1105_RULE_BCAST_POLICER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			int sharindx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		} bcast_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 		/* SJA1105_RULE_TC_POLICER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			int sharindx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		} tc_pol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 		/* SJA1105_RULE_VL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			enum sja1105_vl_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			unsigned long destports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			int sharindx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			int maxlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			int ipv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			u64 base_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			u64 cycle_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			int num_entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			struct action_gate_entry *entries;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			struct flow_stats stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		} vl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct sja1105_flow_block {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	struct list_head rules;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	bool l2_policer_used[SJA1105_NUM_L2_POLICERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int num_virtual_links;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct sja1105_bridge_vlan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	bool pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	bool untagged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) enum sja1105_vlan_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	SJA1105_VLAN_UNAWARE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	SJA1105_VLAN_BEST_EFFORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	SJA1105_VLAN_FILTERING_FULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sja1105_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	struct sja1105_static_config static_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	bool rgmii_rx_delay[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	bool rgmii_tx_delay[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	bool best_effort_vlan_filtering;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	const struct sja1105_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	struct spi_device *spidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	struct list_head dsa_8021q_vlans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	struct list_head bridge_vlans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	struct sja1105_flow_block flow_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	struct sja1105_port ports[SJA1105_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	/* Serializes transmission of management frames so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	 * the switch doesn't confuse them with one another.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	struct mutex mgmt_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 	struct dsa_8021q_context *dsa_8021q_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 	enum sja1105_vlan_state vlan_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	struct devlink_region **regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct sja1105_cbs_entry *cbs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct sja1105_tagger_data tagger_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct sja1105_ptp_data ptp_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	struct sja1105_tas_data tas_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #include "sja1105_dynamic_config.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct sja1105_spi_message {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	u64 access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u64 read_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	u64 address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* From sja1105_main.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) enum sja1105_reset_reason {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	SJA1105_VLAN_FILTERING = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	SJA1105_RX_HWTSTAMPING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	SJA1105_AGEING_TIME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	SJA1105_SCHEDULING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	SJA1105_BEST_EFFORT_POLICING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	SJA1105_VIRTUAL_LINKS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int sja1105_static_config_reload(struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 				 enum sja1105_reset_reason reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) int sja1105_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 			   struct switchdev_trans *trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) void sja1105_frame_memory_partitioning(struct sja1105_private *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* From sja1105_devlink.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) int sja1105_devlink_setup(struct dsa_switch *ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) void sja1105_devlink_teardown(struct dsa_switch *ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) int sja1105_devlink_param_get(struct dsa_switch *ds, u32 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 			      struct devlink_param_gset_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int sja1105_devlink_param_set(struct dsa_switch *ds, u32 id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 			      struct devlink_param_gset_ctx *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int sja1105_devlink_info_get(struct dsa_switch *ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 			     struct devlink_info_req *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 			     struct netlink_ext_ack *extack);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* From sja1105_spi.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int sja1105_xfer_buf(const struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 		     sja1105_spi_rw_mode_t rw, u64 reg_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		     u8 *buf, size_t len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) int sja1105_xfer_u32(const struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 		     sja1105_spi_rw_mode_t rw, u64 reg_addr, u32 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 		     struct ptp_system_timestamp *ptp_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int sja1105_xfer_u64(const struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 		     sja1105_spi_rw_mode_t rw, u64 reg_addr, u64 *value,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 		     struct ptp_system_timestamp *ptp_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int static_config_buf_prepare_for_upload(struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 					 void *config_buf, int buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int sja1105_static_config_upload(struct sja1105_private *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int sja1105_inhibit_tx(const struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		       unsigned long port_bitmap, bool tx_inhibited);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) extern const struct sja1105_info sja1105e_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) extern const struct sja1105_info sja1105t_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) extern const struct sja1105_info sja1105p_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) extern const struct sja1105_info sja1105q_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) extern const struct sja1105_info sja1105r_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) extern const struct sja1105_info sja1105s_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) /* From sja1105_clocking.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	XMII_MAC = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	XMII_PHY = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) } sja1105_mii_role_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	XMII_MODE_MII		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	XMII_MODE_RMII		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	XMII_MODE_RGMII		= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	XMII_MODE_SGMII		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) } sja1105_phy_interface_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) typedef enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	SJA1105_SPEED_10MBPS	= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	SJA1105_SPEED_100MBPS	= 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	SJA1105_SPEED_1000MBPS	= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	SJA1105_SPEED_AUTO	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) } sja1105_speed_t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int sja1105pqrs_setup_rgmii_delay(const void *ctx, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int sja1105_clocking_setup_port(struct sja1105_private *priv, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) int sja1105_clocking_setup(struct sja1105_private *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* From sja1105_ethtool.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) void sja1105_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) void sja1105_get_strings(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 			 u32 stringset, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int sja1105_get_sset_count(struct dsa_switch *ds, int port, int sset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* From sja1105_dynamic_config.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int sja1105_dynamic_config_read(struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 				enum sja1105_blk_idx blk_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				int index, void *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int sja1105_dynamic_config_write(struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 				 enum sja1105_blk_idx blk_idx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 				 int index, void *entry, bool keep);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) enum sja1105_iotag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	SJA1105_C_TAG = 0, /* Inner VLAN header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	SJA1105_S_TAG = 1, /* Outer VLAN header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u8 sja1105et_fdb_hash(struct sja1105_private *priv, const u8 *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int sja1105et_fdb_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		      const unsigned char *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int sja1105et_fdb_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		      const unsigned char *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int sja1105pqrs_fdb_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			const unsigned char *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int sja1105pqrs_fdb_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			const unsigned char *addr, u16 vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* From sja1105_flower.c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int sja1105_cls_flower_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			   struct flow_cls_offload *cls, bool ingress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int sja1105_cls_flower_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			   struct flow_cls_offload *cls, bool ingress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int sja1105_cls_flower_stats(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			     struct flow_cls_offload *cls, bool ingress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) void sja1105_flower_setup(struct dsa_switch *ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) void sja1105_flower_teardown(struct dsa_switch *ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct sja1105_rule *sja1105_rule_find(struct sja1105_private *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 				       unsigned long cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #endif