^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __QCA8K_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __QCA8K_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define QCA8K_NUM_PORTS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QCA8K_MAX_MTU 9000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHY_ID_QCA8337 0x004dd036
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define QCA8K_ID_QCA8337 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QCA8K_NUM_FDB_RECORDS 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QCA8K_CPU_PORT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QCA8K_PORT_VID_DEF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* Global control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define QCA8K_REG_MASK_CTRL 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QCA8K_MASK_CTRL_ID_M 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QCA8K_MASK_CTRL_ID_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QCA8K_REG_PORT0_PAD_CTRL 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define QCA8K_REG_PORT5_PAD_CTRL 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QCA8K_REG_PORT6_PAD_CTRL 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QCA8K_PORT_PAD_RGMII_EN BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ((0x8 + (x & 0x3)) << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) ((0x10 + (x & 0x3)) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QCA8K_MAX_DELAY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define QCA8K_PORT_PAD_SGMII_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QCA8K_REG_PWS 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QCA8K_PWS_SERDES_AEN_DIS BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QCA8K_REG_MODULE_EN 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QCA8K_MODULE_EN_MIB BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QCA8K_REG_MIB 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QCA8K_MIB_FLUSH BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QCA8K_MIB_CPU_KEEP BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QCA8K_MIB_BUSY BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QCA8K_MDIO_MASTER_CTRL 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QCA8K_MDIO_MASTER_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define QCA8K_MDIO_MASTER_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QCA8K_MDIO_MASTER_READ BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QCA8K_MDIO_MASTER_WRITE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QCA8K_MDIO_MASTER_SUP_PRE BIT(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QCA8K_MDIO_MASTER_PHY_ADDR(x) ((x) << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QCA8K_MDIO_MASTER_REG_ADDR(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QCA8K_MDIO_MASTER_DATA(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QCA8K_MDIO_MASTER_DATA_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QCA8K_MDIO_MASTER_MAX_PORTS 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QCA8K_MDIO_MASTER_MAX_REG 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QCA8K_GOL_MAC_ADDR0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QCA8K_GOL_MAC_ADDR1 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QCA8K_MAX_FRAME_SIZE 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QCA8K_PORT_STATUS_SPEED_10 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define QCA8K_PORT_STATUS_SPEED_100 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QCA8K_PORT_STATUS_SPEED_1000 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QCA8K_PORT_STATUS_TXMAC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QCA8K_PORT_STATUS_RXMAC BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define QCA8K_PORT_STATUS_TXFLOW BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define QCA8K_PORT_STATUS_RXFLOW BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QCA8K_PORT_STATUS_DUPLEX BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QCA8K_PORT_STATUS_LINK_UP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define QCA8K_PORT_STATUS_LINK_AUTO BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QCA8K_PORT_STATUS_FLOW_AUTO BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QCA8K_PORT_HDR_CTRL_RX_S 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QCA8K_PORT_HDR_CTRL_TX_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QCA8K_PORT_HDR_CTRL_ALL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QCA8K_PORT_HDR_CTRL_MGMT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QCA8K_PORT_HDR_CTRL_NONE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define QCA8K_REG_SGMII_CTRL 0x0e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QCA8K_SGMII_EN_PLL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QCA8K_SGMII_EN_RX BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QCA8K_SGMII_EN_TX BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QCA8K_SGMII_EN_SD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QCA8K_SGMII_CLK125M_DELAY BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QCA8K_SGMII_MODE_CTRL_MASK (BIT(22) | BIT(23))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QCA8K_SGMII_MODE_CTRL_BASEX (0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QCA8K_SGMII_MODE_CTRL_PHY (1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QCA8K_SGMII_MODE_CTRL_MAC (2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* EEE control registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QCA8K_REG_EEE_CTRL 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* ACL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QCA8K_PORT_VLAN_CVID(x) (x << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QCA8K_PORT_VLAN_SVID(x) x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Lookup registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QCA8K_REG_ATU_DATA0 0x600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QCA8K_ATU_ADDR2_S 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QCA8K_ATU_ADDR3_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QCA8K_ATU_ADDR4_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QCA8K_REG_ATU_DATA1 0x604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QCA8K_ATU_PORT_M 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QCA8K_ATU_PORT_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QCA8K_ATU_ADDR0_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QCA8K_REG_ATU_DATA2 0x608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QCA8K_ATU_VID_M 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define QCA8K_ATU_VID_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QCA8K_ATU_STATUS_M 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QCA8K_ATU_STATUS_STATIC 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QCA8K_REG_ATU_FUNC 0x60c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QCA8K_ATU_FUNC_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define QCA8K_ATU_FUNC_PORT_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QCA8K_ATU_FUNC_MULTI_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define QCA8K_ATU_FUNC_FULL BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QCA8K_ATU_FUNC_PORT_M 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QCA8K_ATU_FUNC_PORT_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QCA8K_REG_VTU_FUNC0 0x610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QCA8K_VTU_FUNC0_VALID BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QCA8K_VTU_FUNC0_IVL_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QCA8K_VTU_FUNC0_EG_MODE_S(_i) (4 + (_i) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define QCA8K_VTU_FUNC0_EG_MODE_MASK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QCA8K_VTU_FUNC0_EG_MODE_UNMOD 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QCA8K_VTU_FUNC0_EG_MODE_UNTAG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QCA8K_VTU_FUNC0_EG_MODE_TAG 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define QCA8K_VTU_FUNC0_EG_MODE_NOT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QCA8K_REG_VTU_FUNC1 0x614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define QCA8K_VTU_FUNC1_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QCA8K_VTU_FUNC1_VID_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QCA8K_VTU_FUNC1_FULL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define QCA8K_PORT_LOOKUP_VLAN_MODE GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QCA8K_PORT_LOOKUP_VLAN_MODE_NONE (0 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define QCA8K_PORT_LOOKUP_VLAN_MODE_FALLBACK (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define QCA8K_PORT_LOOKUP_VLAN_MODE_CHECK (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define QCA8K_PORT_LOOKUP_LEARN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Pkt edit registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* L3 registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define QCA8K_HROUTER_CONTROL 0xe00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define QCA8K_HNAT_CONTROL 0xe38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* MIB registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* QCA specific MII registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MII_ATH_MMD_ADDR 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MII_ATH_MMD_DATA 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) QCA8K_PORT_SPEED_10M = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) QCA8K_PORT_SPEED_100M = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) QCA8K_PORT_SPEED_1000M = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) QCA8K_PORT_SPEED_ERR = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) enum qca8k_fdb_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) QCA8K_FDB_FLUSH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) QCA8K_FDB_LOAD = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) QCA8K_FDB_PURGE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) QCA8K_FDB_NEXT = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) QCA8K_FDB_SEARCH = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) enum qca8k_vlan_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) QCA8K_VLAN_FLUSH = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) QCA8K_VLAN_LOAD = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) QCA8K_VLAN_PURGE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) QCA8K_VLAN_REMOVE_PORT = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) QCA8K_VLAN_NEXT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) QCA8K_VLAN_READ = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct ar8xxx_port_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) struct qca8k_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct regmap *regmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct mutex reg_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct dsa_switch_ops ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct gpio_desc *reset_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) unsigned int port_mtu[QCA8K_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) struct qca8k_mib_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct qca8k_fdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u8 port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u8 aging;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u8 mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #endif /* __QCA8K_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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