^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright 2019 NXP Semiconductors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This is an umbrella module for all network switches that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * register-compatible with Ocelot and that perform I/O to their host CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * through an NPI (Node Processor Interface) Ethernet port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <uapi/linux/if_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <soc/mscc/ocelot_vcap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <soc/mscc/ocelot_qsys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <soc/mscc/ocelot_sys.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <soc/mscc/ocelot_dev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <soc/mscc/ocelot_ana.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <soc/mscc/ocelot_ptp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <soc/mscc/ocelot.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/packing.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/pcs-lynx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <net/pkt_sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include "felix.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static enum dsa_tag_protocol felix_get_tag_protocol(struct dsa_switch *ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum dsa_tag_protocol mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) return DSA_TAG_PROTO_OCELOT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) static int felix_set_ageing_time(struct dsa_switch *ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) unsigned int ageing_time)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ocelot_set_ageing_time(ocelot, ageing_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static int felix_fdb_dump(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) dsa_fdb_dump_cb_t *cb, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return ocelot_fdb_dump(ocelot, port, cb, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int felix_fdb_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) const unsigned char *addr, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) return ocelot_fdb_add(ocelot, port, addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) static int felix_fdb_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) const unsigned char *addr, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return ocelot_fdb_del(ocelot, port, addr, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* This callback needs to be present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int felix_mdb_prepare(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) const struct switchdev_obj_port_mdb *mdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) static void felix_mdb_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) const struct switchdev_obj_port_mdb *mdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ocelot_port_mdb_add(ocelot, port, mdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static int felix_mdb_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) const struct switchdev_obj_port_mdb *mdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) return ocelot_port_mdb_del(ocelot, port, mdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) static void felix_bridge_stp_state_set(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return ocelot_bridge_stp_state_set(ocelot, port, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int felix_bridge_join(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct net_device *br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) return ocelot_port_bridge_join(ocelot, port, br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void felix_bridge_leave(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct net_device *br)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ocelot_port_bridge_leave(ocelot, port, br);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* This callback needs to be present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int felix_vlan_prepare(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) const struct switchdev_obj_port_vlan *vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static int felix_vlan_filtering(struct dsa_switch *ds, int port, bool enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct switchdev_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) return ocelot_port_vlan_filtering(ocelot, port, enabled, trans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) static void felix_vlan_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) const struct switchdev_obj_port_vlan *vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u16 flags = vlan->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) if (dsa_is_cpu_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) flags &= ~BRIDGE_VLAN_INFO_UNTAGGED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) err = ocelot_vlan_add(ocelot, port, vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) flags & BRIDGE_VLAN_INFO_PVID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) flags & BRIDGE_VLAN_INFO_UNTAGGED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dev_err(ds->dev, "Failed to add VLAN %d to port %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) vid, port, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) static int felix_vlan_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) const struct switchdev_obj_port_vlan *vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) for (vid = vlan->vid_begin; vid <= vlan->vid_end; vid++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) err = ocelot_vlan_del(ocelot, port, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(ds->dev, "Failed to remove VLAN %d from port %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) vid, port, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static int felix_port_enable(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct phy_device *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ocelot_port_enable(ocelot, port, phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static void felix_port_disable(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return ocelot_port_disable(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void felix_phylink_validate(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned long *supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (felix->info->phylink_validate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) felix->info->phylink_validate(ocelot, port, supported, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void felix_phylink_mac_config(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) unsigned int link_an_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct dsa_port *dp = dsa_to_port(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) if (felix->pcs[port])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) phylink_set_pcs(dp->pl, &felix->pcs[port]->pcs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static void felix_phylink_mac_link_down(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) unsigned int link_an_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) ocelot_port_rmwl(ocelot_port, 0, DEV_MAC_ENA_CFG_RX_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) DEV_MAC_ENA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ocelot_fields_write(ocelot, port, QSYS_SWITCH_PORT_MODE_PORT_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) err = ocelot_port_flush(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) dev_err(ocelot->dev, "failed to flush port %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) port, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Put the port in reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ocelot_port_writel(ocelot_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) DEV_CLOCK_CFG_MAC_TX_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) DEV_CLOCK_CFG_MAC_RX_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) DEV_CLOCK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static void felix_phylink_mac_link_up(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) unsigned int link_an_mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) int speed, int duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) bool tx_pause, bool rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 mac_fc_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Take port out of reset by clearing the MAC_TX_RST, MAC_RX_RST and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * PORT_RST bits in DEV_CLOCK_CFG. Note that the way this system is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * integrated is that the MAC speed is fixed and it's the PCS who is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * performing the rate adaptation, so we have to write "1000Mbps" into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * the LINK_SPEED field of DEV_CLOCK_CFG (which is also its default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * value).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ocelot_port_writel(ocelot_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) DEV_CLOCK_CFG_LINK_SPEED(OCELOT_SPEED_1000),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) DEV_CLOCK_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) case SPEED_2500:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_err(ocelot->dev, "Unsupported speed on port %d: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) port, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* handle Rx pause in all cases, with 2500base-X this is used for rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * adaptation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) SYS_MAC_FC_CFG_FC_LATENCY_CFG(0x7) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) SYS_MAC_FC_CFG_ZERO_PAUSE_ENA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Flow control. Link speed is only used here to evaluate the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * specification in incoming pause frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) ocelot_write_rix(ocelot, mac_fc_cfg, SYS_MAC_FC_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) ocelot_write_rix(ocelot, 0, ANA_POL_FLOWC, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Undo the effects of felix_phylink_mac_link_down:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * enable MAC module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) DEV_MAC_ENA_CFG_TX_ENA, DEV_MAC_ENA_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Enable receiving frames on the port, and activate auto-learning of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * MAC addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) ocelot_write_gix(ocelot, ANA_PORT_PORT_CFG_LEARNAUTO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) ANA_PORT_PORT_CFG_RECV_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) ANA_PORT_PORT_CFG_PORTID_VAL(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) ANA_PORT_PORT_CFG, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Core: Enable port for frame transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) ocelot_fields_write(ocelot, port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) QSYS_SWITCH_PORT_MODE_PORT_ENA, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (felix->info->port_sched_speed_set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) felix->info->port_sched_speed_set(ocelot, port, speed);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) static void felix_port_qos_map_init(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) ocelot_rmw_gix(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ANA_PORT_QOS_CFG_QOS_PCP_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ANA_PORT_QOS_CFG_QOS_PCP_ENA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) ANA_PORT_QOS_CFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) for (i = 0; i < FELIX_NUM_TC * 2; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) ocelot_rmw_ix(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) (ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL & i) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) ANA_PORT_PCP_DEI_MAP_DP_PCP_DEI_VAL |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) ANA_PORT_PCP_DEI_MAP_QOS_PCP_DEI_VAL_M,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ANA_PORT_PCP_DEI_MAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) port, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) static void felix_get_strings(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u32 stringset, u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ocelot_get_strings(ocelot, port, stringset, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static void felix_get_ethtool_stats(struct dsa_switch *ds, int port, u64 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ocelot_get_ethtool_stats(ocelot, port, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) static int felix_get_sset_count(struct dsa_switch *ds, int port, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return ocelot_get_sset_count(ocelot, port, sset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int felix_get_ts_info(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct ethtool_ts_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return ocelot_get_ts_info(ocelot, port, info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static int felix_parse_ports_node(struct felix *felix,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct device_node *ports_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) phy_interface_t *port_phy_modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct ocelot *ocelot = &felix->ocelot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct device *dev = felix->ocelot.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) for_each_available_child_of_node(ports_node, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) phy_interface_t phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) u32 port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* Get switch port number from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (of_property_read_u32(child, "reg", &port) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_err(dev, "Port number not defined in device tree "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) "(property \"reg\")\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) /* Get PHY mode from DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) err = of_get_phy_mode(child, &phy_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(dev, "Failed to read phy-mode or "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "phy-interface-type property for port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) err = felix->info->prevalidate_phy_mode(ocelot, port, phy_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) dev_err(dev, "Unsupported PHY mode %s on port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) phy_modes(phy_mode), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) of_node_put(child);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) port_phy_modes[port] = phy_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) static int felix_parse_dt(struct felix *felix, phy_interface_t *port_phy_modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) struct device *dev = felix->ocelot.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct device_node *switch_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) struct device_node *ports_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) switch_node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) ports_node = of_get_child_by_name(switch_node, "ports");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (!ports_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) dev_err(dev, "Incorrect bindings: absent \"ports\" node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) err = felix_parse_ports_node(felix, ports_node, port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) of_node_put(ports_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int felix_init_structs(struct felix *felix, int num_phys_ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct ocelot *ocelot = &felix->ocelot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) phy_interface_t *port_phy_modes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int port, i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) ocelot->num_phys_ports = num_phys_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ocelot->ports = devm_kcalloc(ocelot->dev, num_phys_ports,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) sizeof(struct ocelot_port *), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (!ocelot->ports)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) ocelot->map = felix->info->map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) ocelot->stats_layout = felix->info->stats_layout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ocelot->num_stats = felix->info->num_stats;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) ocelot->shared_queue_sz = felix->info->shared_queue_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) ocelot->num_mact_rows = felix->info->num_mact_rows;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) ocelot->vcap = felix->info->vcap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ocelot->ops = felix->info->ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) ocelot->inj_prefix = OCELOT_TAG_PREFIX_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ocelot->xtr_prefix = OCELOT_TAG_PREFIX_SHORT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) port_phy_modes = kcalloc(num_phys_ports, sizeof(phy_interface_t),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) if (!port_phy_modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) err = felix_parse_dt(felix, port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) for (i = 0; i < TARGET_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) struct regmap *target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) if (!felix->info->target_io_res[i].name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) memcpy(&res, &felix->info->target_io_res[i], sizeof(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) res.start += felix->switch_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) res.end += felix->switch_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) target = ocelot_regmap_init(ocelot, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (IS_ERR(target)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "Failed to map device memory space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return PTR_ERR(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ocelot->targets[i] = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) err = ocelot_regfields_init(ocelot, felix->info->regfields);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) dev_err(ocelot->dev, "failed to init reg fields map\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) for (port = 0; port < num_phys_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) struct ocelot_port *ocelot_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct regmap *target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 *template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ocelot_port = devm_kzalloc(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) sizeof(struct ocelot_port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!ocelot_port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) "failed to allocate port memory\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) memcpy(&res, &felix->info->port_io_res[port], sizeof(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) res.flags = IORESOURCE_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) res.start += felix->switch_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) res.end += felix->switch_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) target = ocelot_regmap_init(ocelot, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) if (IS_ERR(target)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "Failed to map memory space for port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return PTR_ERR(target);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) template = devm_kzalloc(ocelot->dev, OCELOT_TOTAL_TAG_LEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (!template) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "Failed to allocate memory for DSA tag\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) ocelot_port->phy_mode = port_phy_modes[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) ocelot_port->ocelot = ocelot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) ocelot_port->target = target;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) ocelot_port->xmit_template = template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ocelot->ports[port] = ocelot_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) felix->info->xmit_template_populate(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) kfree(port_phy_modes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) if (felix->info->mdio_bus_alloc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) err = felix->info->mdio_bus_alloc(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /* The CPU port module is connected to the Node Processor Interface (NPI). This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * is the mode through which frames can be injected from and extracted to an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) * external CPU, over Ethernet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) static void felix_npi_port_init(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) ocelot->npi = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) ocelot_write(ocelot, QSYS_EXT_CPU_CFG_EXT_CPUQ_MSK_M |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) QSYS_EXT_CPU_CFG_EXT_CPU_PORT(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) QSYS_EXT_CPU_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* NPI port Injection/Extraction configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_XTR_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ocelot->xtr_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ocelot_fields_write(ocelot, port, SYS_PORT_MODE_INCL_INJ_HDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) ocelot->inj_prefix);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Disable transmission of pause frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) ocelot_fields_write(ocelot, port, SYS_PAUSE_CFG_PAUSE_ENA, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* Hardware initialization done here so that we can allocate structures with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) * devm without fear of dsa_register_switch returning -EPROBE_DEFER and causing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * us to allocate structures twice (leak memory) and map PCI memory twice
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * (which will not work).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static int felix_setup(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int port, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) err = felix_init_structs(felix, ds->num_ports);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) err = ocelot_init(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ocelot->ptp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) err = ocelot_init_timestamp(ocelot, felix->info->ptp_caps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_err(ocelot->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) "Timestamp initialization failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) ocelot->ptp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) for (port = 0; port < ds->num_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ocelot_init_port(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (dsa_is_cpu_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) felix_npi_port_init(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /* Set the default QoS Classification based on PCP and DEI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * bits of vlan tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) felix_port_qos_map_init(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Include the CPU port module in the forwarding mask for unknown
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * unicast - the hardware default value for ANA_FLOODING_FLD_UNICAST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * excludes BIT(ocelot->num_phys_ports), and so does ocelot_init, since
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * Ocelot relies on whitelisting MAC addresses towards PGID_CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ocelot_write_rix(ocelot,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) ANA_PGID_PGID_PGID(GENMASK(ocelot->num_phys_ports, 0)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) ANA_PGID_PGID, PGID_UC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) ds->mtu_enforcement_ingress = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) ds->configure_vlan_while_not_filtering = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static void felix_teardown(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) ocelot_deinit_timestamp(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) ocelot_deinit(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) for (port = 0; port < ocelot->num_phys_ports; port++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (dsa_is_unused_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) ocelot_deinit_port(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (felix->info->mdio_bus_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) felix->info->mdio_bus_free(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) static int felix_hwtstamp_get(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ocelot_hwstamp_get(ocelot, port, ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int felix_hwtstamp_set(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return ocelot_hwstamp_set(ocelot, port, ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static bool felix_rxtstamp(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) struct sk_buff *skb, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) struct skb_shared_hwtstamps *shhwtstamps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u8 *extraction = skb->data - ETH_HLEN - OCELOT_TAG_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 tstamp_lo, tstamp_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct timespec64 ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u64 tstamp, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) ocelot_ptp_gettime64(&ocelot->ptp_info, &ts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) tstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) packing(extraction, &val, 116, 85, OCELOT_TAG_LEN, UNPACK, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) tstamp_lo = (u32)val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) tstamp_hi = tstamp >> 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if ((tstamp & 0xffffffff) < tstamp_lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) tstamp_hi--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) tstamp = ((u64)tstamp_hi << 32) | tstamp_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) shhwtstamps = skb_hwtstamps(skb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) memset(shhwtstamps, 0, sizeof(struct skb_shared_hwtstamps));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) shhwtstamps->hwtstamp = tstamp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) static bool felix_txtstamp(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct sk_buff *clone, unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct ocelot_port *ocelot_port = ocelot->ports[port];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (ocelot->ptp && (skb_shinfo(clone)->tx_flags & SKBTX_HW_TSTAMP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ocelot_port->ptp_cmd == IFH_REW_OP_TWO_STEP_PTP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) ocelot_port_add_txtstamp_skb(ocelot, port, clone);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static int felix_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ocelot_port_set_maxlen(ocelot, port, new_mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static int felix_get_max_mtu(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return ocelot_get_max_mtu(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int felix_cls_flower_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) struct flow_cls_offload *cls, bool ingress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) return ocelot_cls_flower_replace(ocelot, port, cls, ingress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static int felix_cls_flower_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct flow_cls_offload *cls, bool ingress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return ocelot_cls_flower_destroy(ocelot, port, cls, ingress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static int felix_cls_flower_stats(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct flow_cls_offload *cls, bool ingress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return ocelot_cls_flower_stats(ocelot, port, cls, ingress);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static int felix_port_policer_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct dsa_mall_policer_tc_entry *policer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct ocelot_policer pol = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .rate = div_u64(policer->rate_bytes_per_sec, 1000) * 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .burst = policer->burst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return ocelot_port_policer_add(ocelot, port, &pol);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void felix_port_policer_del(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ocelot_port_policer_del(ocelot, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int felix_port_setup_tc(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) enum tc_setup_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) void *type_data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) struct ocelot *ocelot = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) if (felix->info->port_setup_tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return felix->info->port_setup_tc(ds, port, type, type_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) const struct dsa_switch_ops felix_switch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .get_tag_protocol = felix_get_tag_protocol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .setup = felix_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .teardown = felix_teardown,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .set_ageing_time = felix_set_ageing_time,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .get_strings = felix_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .get_ethtool_stats = felix_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .get_sset_count = felix_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .get_ts_info = felix_get_ts_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .phylink_validate = felix_phylink_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .phylink_mac_config = felix_phylink_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .phylink_mac_link_down = felix_phylink_mac_link_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .phylink_mac_link_up = felix_phylink_mac_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .port_enable = felix_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .port_disable = felix_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .port_fdb_dump = felix_fdb_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .port_fdb_add = felix_fdb_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .port_fdb_del = felix_fdb_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .port_mdb_prepare = felix_mdb_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .port_mdb_add = felix_mdb_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .port_mdb_del = felix_mdb_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .port_bridge_join = felix_bridge_join,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .port_bridge_leave = felix_bridge_leave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .port_stp_state_set = felix_bridge_stp_state_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .port_vlan_prepare = felix_vlan_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) .port_vlan_filtering = felix_vlan_filtering,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) .port_vlan_add = felix_vlan_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .port_vlan_del = felix_vlan_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .port_hwtstamp_get = felix_hwtstamp_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .port_hwtstamp_set = felix_hwtstamp_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .port_rxtstamp = felix_rxtstamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .port_txtstamp = felix_txtstamp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) .port_change_mtu = felix_change_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) .port_max_mtu = felix_get_max_mtu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .port_policer_add = felix_port_policer_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .port_policer_del = felix_port_policer_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .cls_flower_add = felix_cls_flower_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .cls_flower_del = felix_cls_flower_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .cls_flower_stats = felix_cls_flower_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .port_setup_tc = felix_port_setup_tc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) struct net_device *felix_port_to_netdev(struct ocelot *ocelot, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct felix *felix = ocelot_to_felix(ocelot);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) struct dsa_switch *ds = felix->ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!dsa_is_user_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return dsa_to_port(ds, port)->slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) int felix_netdev_to_port(struct net_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct dsa_port *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dp = dsa_port_from_netdev(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) if (IS_ERR(dp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return dp->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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