Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Marvell 88E6xxx System Management Interface (SMI) support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (c) 2019 Vivien Didelot <vivien.didelot@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MV88E6XXX_SMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MV88E6XXX_SMI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* Offset 0x00: SMI Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define MV88E6XXX_SMI_CMD			0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MV88E6XXX_SMI_CMD_BUSY			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MV88E6XXX_SMI_CMD_MODE_MASK		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MV88E6XXX_SMI_CMD_MODE_45		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MV88E6XXX_SMI_CMD_MODE_22		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MV88E6XXX_SMI_CMD_OP_MASK		0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MV88E6XXX_SMI_CMD_OP_22_WRITE		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MV88E6XXX_SMI_CMD_OP_22_READ		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MV88E6XXX_SMI_CMD_OP_45_WRITE_ADDR	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MV88E6XXX_SMI_CMD_OP_45_WRITE_DATA	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MV88E6XXX_SMI_CMD_OP_45_READ_DATA	0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MV88E6XXX_SMI_CMD_OP_45_READ_DATA_INC	0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MV88E6XXX_SMI_CMD_DEV_ADDR_MASK		0x003e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MV88E6XXX_SMI_CMD_REG_ADDR_MASK		0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Offset 0x01: SMI Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MV88E6XXX_SMI_DATA			0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		       struct mii_bus *bus, int sw_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) static inline int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 				     int dev, int reg, u16 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	if (chip->smi_ops && chip->smi_ops->read)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		return chip->smi_ops->read(chip, dev, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static inline int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 				      int dev, int reg, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	if (chip->smi_ops && chip->smi_ops->write)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		return chip->smi_ops->write(chip, dev, reg, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #endif /* _MV88E6XXX_SMI_H */