Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell 88E6xxx SERDES manipulation, via SMI bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _MV88E6XXX_SERDES_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _MV88E6XXX_SERDES_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define MV88E6352_ADDR_SERDES		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define MV88E6352_SERDES_PAGE_FIBER	0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MV88E6352_SERDES_IRQ		0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MV88E6352_SERDES_INT_ENABLE	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MV88E6352_SERDES_INT_SPEED_CHANGE	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MV88E6352_SERDES_INT_DUPLEX_CHANGE	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MV88E6352_SERDES_INT_PAGE_RX		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MV88E6352_SERDES_INT_AN_COMPLETE	BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MV88E6352_SERDES_INT_LINK_CHANGE	BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MV88E6352_SERDES_INT_SYMBOL_ERROR	BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MV88E6352_SERDES_INT_FALSE_CARRIER	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MV88E6352_SERDES_INT_FIFO_OVER_UNDER	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MV88E6352_SERDES_INT_FIBRE_ENERGY	BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MV88E6352_SERDES_INT_STATUS	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MV88E6341_PORT5_LANE		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MV88E6390_PORT9_LANE0		0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define MV88E6390_PORT9_LANE1		0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define MV88E6390_PORT9_LANE2		0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define MV88E6390_PORT9_LANE3		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define MV88E6390_PORT10_LANE0		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define MV88E6390_PORT10_LANE1		0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MV88E6390_PORT10_LANE2		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MV88E6390_PORT10_LANE3		0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) /* 10GBASE-R and 10GBASE-X4/X2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define MV88E6390_10G_CTRL1		(0x1000 + MDIO_CTRL1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MV88E6390_10G_STAT1		(0x1000 + MDIO_STAT1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* 1000BASE-X and SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MV88E6390_SGMII_BMCR		(0x2000 + MII_BMCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MV88E6390_SGMII_BMSR		(0x2000 + MII_BMSR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define MV88E6390_SGMII_ADVERTISE	(0x2000 + MII_ADVERTISE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define MV88E6390_SGMII_LPA		(0x2000 + MII_LPA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MV88E6390_SGMII_INT_ENABLE	0xa001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MV88E6390_SGMII_INT_SPEED_CHANGE	BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define MV88E6390_SGMII_INT_DUPLEX_CHANGE	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define MV88E6390_SGMII_INT_PAGE_RX		BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MV88E6390_SGMII_INT_AN_COMPLETE		BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MV88E6390_SGMII_INT_LINK_DOWN		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MV88E6390_SGMII_INT_LINK_UP		BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MV88E6390_SGMII_INT_SYMBOL_ERROR	BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MV88E6390_SGMII_INT_FALSE_CARRIER	BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MV88E6390_SGMII_INT_STATUS	0xa002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MV88E6390_SGMII_PHY_STATUS	0xa003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MV88E6390_SGMII_PHY_STATUS_SPEED_MASK	GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MV88E6390_SGMII_PHY_STATUS_SPEED_1000	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MV88E6390_SGMII_PHY_STATUS_SPEED_100	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MV88E6390_SGMII_PHY_STATUS_SPEED_10	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MV88E6390_SGMII_PHY_STATUS_DUPLEX_FULL	BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MV88E6390_SGMII_PHY_STATUS_SPD_DPL_VALID BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MV88E6390_SGMII_PHY_STATUS_LINK		BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MV88E6390_SGMII_PHY_STATUS_TX_PAUSE	BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define MV88E6390_SGMII_PHY_STATUS_RX_PAUSE	BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* Packet generator pad packet checker */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MV88E6390_PG_CONTROL		0xf010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MV88E6390_PG_CONTROL_ENABLE_PC		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) u8 mv88e6341_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) u8 mv88e6352_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) u8 mv88e6390_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) u8 mv88e6390x_serdes_get_lane(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) int mv88e6352_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 				u8 lane, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 				phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 				const unsigned long *advertise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) int mv88e6390_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 				u8 lane, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 				phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 				const unsigned long *advertise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) int mv88e6352_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 				   u8 lane, struct phylink_link_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) int mv88e6390_serdes_pcs_get_state(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 				   u8 lane, struct phylink_link_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) int mv88e6352_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 				    u8 lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) int mv88e6390_serdes_pcs_an_restart(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 				    u8 lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) int mv88e6352_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 				 u8 lane, int speed, int duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) int mv88e6390_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 				 u8 lane, int speed, int duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) unsigned int mv88e6352_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 					  int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int mv88e6390_serdes_irq_mapping(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 					  int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int mv88e6352_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 			   bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int mv88e6390_serdes_power(struct mv88e6xxx_chip *chip, int port, u8 lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 			   bool on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int mv88e6352_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 				bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) int mv88e6390_serdes_irq_enable(struct mv88e6xxx_chip *chip, int port, u8 lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 				bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) irqreturn_t mv88e6352_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 					u8 lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) irqreturn_t mv88e6390_serdes_irq_status(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 					u8 lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) int mv88e6352_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int mv88e6352_serdes_get_strings(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 				 int port, uint8_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int mv88e6352_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			       uint64_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int mv88e6390_serdes_get_sset_count(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int mv88e6390_serdes_get_strings(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 				 int port, uint8_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) int mv88e6390_serdes_get_stats(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 			       uint64_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) int mv88e6352_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) void mv88e6352_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int mv88e6390_serdes_get_regs_len(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void mv88e6390_serdes_get_regs(struct mv88e6xxx_chip *chip, int port, void *_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Return the (first) SERDES lane address a port is using, 0 otherwise. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static inline u8 mv88e6xxx_serdes_get_lane(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 					   int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	if (!chip->info->ops->serdes_get_lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	return chip->info->ops->serdes_get_lane(chip, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static inline int mv88e6xxx_serdes_power_up(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 					    int port, u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	if (!chip->info->ops->serdes_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	return chip->info->ops->serdes_power(chip, port, lane, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline int mv88e6xxx_serdes_power_down(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 					      int port, u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (!chip->info->ops->serdes_power)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	return chip->info->ops->serdes_power(chip, port, lane, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) mv88e6xxx_serdes_irq_mapping(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	if (!chip->info->ops->serdes_irq_mapping)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 		return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	return chip->info->ops->serdes_irq_mapping(chip, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline int mv88e6xxx_serdes_irq_enable(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 					      int port, u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 	if (!chip->info->ops->serdes_irq_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	return chip->info->ops->serdes_irq_enable(chip, port, lane, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) static inline int mv88e6xxx_serdes_irq_disable(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 					       int port, u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	if (!chip->info->ops->serdes_irq_enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	return chip->info->ops->serdes_irq_enable(chip, port, lane, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline irqreturn_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) mv88e6xxx_serdes_irq_status(struct mv88e6xxx_chip *chip, int port, u8 lane)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	if (!chip->info->ops->serdes_irq_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 		return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	return chip->info->ops->serdes_irq_status(chip, port, lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #endif