^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88E6xxx Switch PTP support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2017 National Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Erik Hons <erik.hons@ni.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Brandon Streiff <brandon.streiff@ni.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Dane Wagner <dane.wagner@ni.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _MV88E6XXX_PTP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _MV88E6XXX_PTP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Offset 0x00: TAI Global Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MV88E6XXX_TAI_CFG 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MV88E6XXX_TAI_CFG_CAP_OVERWRITE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MV88E6XXX_TAI_CFG_CAP_CTR_START 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MV88E6XXX_TAI_CFG_EVREQ_FALLING 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MV88E6XXX_TAI_CFG_TRIG_ACTIVE_LO 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MV88E6XXX_TAI_CFG_IRL_ENABLE 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MV88E6XXX_TAI_CFG_TRIG_IRQ_EN 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MV88E6XXX_TAI_CFG_EVREQ_IRQ_EN 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MV88E6XXX_TAI_CFG_TRIG_LOCK 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MV88E6XXX_TAI_CFG_BLOCK_UPDATE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MV88E6XXX_TAI_CFG_MULTI_PTP 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MV88E6XXX_TAI_CFG_TRIG_MODE_ONESHOT 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MV88E6XXX_TAI_CFG_TRIG_ENABLE 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Offset 0x01: Timestamp Clock Period (ps) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MV88E6XXX_TAI_CLOCK_PERIOD 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) /* Offset 0x02/0x03: Trigger Generation Amount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_LO 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MV88E6XXX_TAI_TRIG_GEN_AMOUNT_HI 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Offset 0x04: Clock Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MV88E6XXX_TAI_TRIG_CLOCK_COMP 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* Offset 0x05: Trigger Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MV88E6XXX_TAI_TRIG_CFG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* Offset 0x06: Ingress Rate Limiter Clock Generation Amount */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MV88E6XXX_TAI_IRL_AMOUNT 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Offset 0x07: Ingress Rate Limiter Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MV88E6XXX_TAI_IRL_COMP 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Offset 0x08: Ingress Rate Limiter Compensation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MV88E6XXX_TAI_IRL_COMP_PS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Offset 0x09: Event Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MV88E6XXX_TAI_EVENT_STATUS 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MV88E6XXX_TAI_EVENT_STATUS_CAP_TRIG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MV88E6XXX_TAI_EVENT_STATUS_ERROR 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MV88E6XXX_TAI_EVENT_STATUS_VALID 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MV88E6XXX_TAI_EVENT_STATUS_CTR_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Offset 0x0A/0x0B: Event Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MV88E6XXX_TAI_EVENT_TIME_LO 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MV88E6XXX_TAI_EVENT_TYPE_HI 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* Offset 0x0E/0x0F: PTP Global Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MV88E6XXX_TAI_TIME_LO 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MV88E6XXX_TAI_TIME_HI 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Offset 0x10/0x11: Trig Generation Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MV88E6XXX_TAI_TRIG_TIME_LO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MV88E6XXX_TAI_TRIG_TIME_HI 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Offset 0x12: Lock Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MV88E6XXX_TAI_LOCK_STATUS 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Offset 0x00: Ether Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MV88E6XXX_PTP_GC_ETYPE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* 6165 Global Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Offset 0x00: Ether Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MV88E6XXX_PTP_GC_ETYPE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Offset 0x01: Message ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MV88E6XXX_PTP_GC_MESSAGE_ID 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Offset 0x02: Time Stamp Arrive Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MV88E6XXX_PTP_GC_TS_ARR_PTR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Offset 0x03: Port Arrival Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define MV88E6XXX_PTP_GC_PORT_ARR_INT_EN 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* Offset 0x04: Port Departure Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MV88E6XXX_PTP_GC_PORT_DEP_INT_EN 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Offset 0x05: Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MV88E6XXX_PTP_GC_CONFIG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MV88E6XXX_PTP_GC_CONFIG_DIS_OVERWRITE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MV88E6XXX_PTP_GC_CONFIG_DIS_TS BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Offset 0x8: Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MV88E6XXX_PTP_GC_INT_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Offset 0x9/0xa: Global Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MV88E6XXX_PTP_GC_TIME_LO 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MV88E6XXX_PTP_GC_TIME_HI 0x0A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 6165 Per Port Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Offset 0: Arrival Time 0 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MV88E6165_PORT_PTP_ARR0_STS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* Offset 0x01/0x02: PTP Arrival 0 Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MV88E6165_PORT_PTP_ARR0_TIME_LO 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MV88E6165_PORT_PTP_ARR0_TIME_HI 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Offset 0x03: PTP Arrival 0 Sequence ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MV88E6165_PORT_PTP_ARR0_SEQID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* Offset 0x04: PTP Arrival 1 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MV88E6165_PORT_PTP_ARR1_STS 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Offset 0x05/0x6E: PTP Arrival 1 Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MV88E6165_PORT_PTP_ARR1_TIME_LO 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MV88E6165_PORT_PTP_ARR1_TIME_HI 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Offset 0x07: PTP Arrival 1 Sequence ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MV88E6165_PORT_PTP_ARR1_SEQID 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Offset 0x08: PTP Departure Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MV88E6165_PORT_PTP_DEP_STS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Offset 0x09/0x0a: PTP Deperture Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MV88E6165_PORT_PTP_DEP_TIME_LO 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MV88E6165_PORT_PTP_DEP_TIME_HI 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Offset 0x0b: PTP Departure Sequence ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MV88E6165_PORT_PTP_DEP_SEQID 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Offset 0x0d: Port Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MV88E6164_PORT_STATUS 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ptp_to_chip(ptp) container_of(ptp, struct mv88e6xxx_chip, \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) ptp_clock_info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) extern const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) extern const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) extern const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static inline long mv88e6xxx_hwtstamp_work(struct ptp_clock_info *ptp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static inline int mv88e6xxx_ptp_setup(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline void mv88e6xxx_ptp_free(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static const struct mv88e6xxx_ptp_ops mv88e6165_ptp_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static const struct mv88e6xxx_ptp_ops mv88e6250_ptp_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) static const struct mv88e6xxx_ptp_ops mv88e6352_ptp_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #endif /* _MV88E6XXX_PTP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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