Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Marvell 88E6xxx PHY access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Copyright (c) 2017 Andrew Lunn <andrew@lunn.ch>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef _MV88E6XXX_PHY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define _MV88E6XXX_PHY_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MV88E6XXX_PHY_PAGE		0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define MV88E6XXX_PHY_PAGE_COPPER	0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* PHY Registers accesses implementations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		       int addr, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 			int addr, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) int mv88e6185_phy_ppu_read(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 			   int addr, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) int mv88e6185_phy_ppu_write(struct mv88e6xxx_chip *chip, struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			    int addr, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Generic PHY operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		       int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			    u8 page, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			     u8 page, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int mv88e6xxx_phy_setup(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /*_MV88E6XXX_PHY_H */