^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88E6xxx Switch hardware timestamping support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2017 National Instruments
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Erik Hons <erik.hons@ni.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Brandon Streiff <brandon.streiff@ni.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Dane Wagner <dane.wagner@ni.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _MV88E6XXX_HWTSTAMP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _MV88E6XXX_HWTSTAMP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* Global 6352 PTP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Offset 0x00: PTP EtherType */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MV88E6XXX_PTP_ETHERTYPE 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Offset 0x01: Message Type Timestamp Enables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MV88E6XXX_PTP_MSGTYPE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MV88E6XXX_PTP_MSGTYPE_SYNC 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MV88E6XXX_PTP_MSGTYPE_DELAY_REQ 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MV88E6XXX_PTP_MSGTYPE_PDLAY_REQ 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MV88E6XXX_PTP_MSGTYPE_PDLAY_RES 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MV88E6XXX_PTP_MSGTYPE_ALL_EVENT 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* Offset 0x02: Timestamp Arrival Capture Pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MV88E6XXX_PTP_TS_ARRIVAL_PTR 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Offset 0x05: PTP Global Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MV88E6165_PTP_CFG 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MV88E6165_PTP_CFG_TSPEC_MASK 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MV88E6165_PTP_CFG_DISABLE_TS_OVERWRITE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MV88E6165_PTP_CFG_DISABLE_PTP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Offset 0x07: PTP Global Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MV88E6341_PTP_CFG 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MV88E6341_PTP_CFG_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MV88E6341_PTP_CFG_IDX_MASK 0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MV88E6341_PTP_CFG_DATA_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MV88E6341_PTP_CFG_MODE_IDX 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MV88E6341_PTP_CFG_MODE_TS_AT_PHY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MV88E6341_PTP_CFG_MODE_TS_AT_MAC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) /* Offset 0x08: PTP Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MV88E6XXX_PTP_IRQ_STATUS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Per-Port 6352 PTP Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) /* Offset 0x00: PTP Configuration 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MV88E6XXX_PORT_PTP_CFG0 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_MASK 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_1588 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MV88E6XXX_PORT_PTP_CFG0_TSPEC_8021AS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_TSPEC_MATCH 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_OVERWRITE 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MV88E6XXX_PORT_PTP_CFG0_DISABLE_PTP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Offset 0x01: PTP Configuration 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MV88E6XXX_PORT_PTP_CFG1 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Offset 0x02: PTP Configuration 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MV88E6XXX_PORT_PTP_CFG2 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MV88E6XXX_PORT_PTP_CFG2_EMBED_ARRIVAL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MV88E6XXX_PORT_PTP_CFG2_DEP_IRQ_EN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MV88E6XXX_PORT_PTP_CFG2_ARR_IRQ_EN 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* Offset 0x03: PTP LED Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define MV88E6XXX_PORT_PTP_LED_CFG 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Offset 0x08: PTP Arrival 0 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MV88E6XXX_PORT_PTP_ARR0_STS 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Offset 0x09/0x0A: PTP Arrival 0 Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MV88E6XXX_PORT_PTP_ARR0_TIME_LO 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MV88E6XXX_PORT_PTP_ARR0_TIME_HI 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Offset 0x0B: PTP Arrival 0 Sequence ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MV88E6XXX_PORT_PTP_ARR0_SEQID 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) /* Offset 0x0C: PTP Arrival 1 Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MV88E6XXX_PORT_PTP_ARR1_STS 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* Offset 0x0D/0x0E: PTP Arrival 1 Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MV88E6XXX_PORT_PTP_ARR1_TIME_LO 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MV88E6XXX_PORT_PTP_ARR1_TIME_HI 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Offset 0x0F: PTP Arrival 1 Sequence ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define MV88E6XXX_PORT_PTP_ARR1_SEQID 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Offset 0x10: PTP Departure Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define MV88E6XXX_PORT_PTP_DEP_STS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* Offset 0x11/0x12: PTP Deperture Time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MV88E6XXX_PORT_PTP_DEP_TIME_LO 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MV88E6XXX_PORT_PTP_DEP_TIME_HI 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Offset 0x13: PTP Departure Sequence ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MV88E6XXX_PORT_PTP_DEP_SEQID 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Status fields for arrival and depature timestamp status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MV88E6XXX_PTP_TS_STATUS_MASK 0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MV88E6XXX_PTP_TS_STATUS_NORMAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MV88E6XXX_PTP_TS_STATUS_OVERWITTEN 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MV88E6XXX_PTP_TS_STATUS_DISCARDED 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MV88E6XXX_PTP_TS_VALID 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #ifdef CONFIG_NET_DSA_MV88E6XXX_PTP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct ifreq *ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct ifreq *ifr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct sk_buff *clone, unsigned int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) bool mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct sk_buff *clone, unsigned int type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct ethtool_ts_info *info);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int mv88e6352_hwtstamp_port_enable(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) int mv88e6352_hwtstamp_port_disable(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int mv88e6165_global_enable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int mv88e6165_global_disable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #else /* !CONFIG_NET_DSA_MV88E6XXX_PTP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static inline int mv88e6xxx_port_hwtstamp_set(struct dsa_switch *ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) int port, struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline int mv88e6xxx_port_hwtstamp_get(struct dsa_switch *ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int port, struct ifreq *ifr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static inline bool mv88e6xxx_port_rxtstamp(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct sk_buff *clone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline bool mv88e6xxx_port_txtstamp(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct sk_buff *clone,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static inline int mv88e6xxx_get_ts_info(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct ethtool_ts_info *info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline int mv88e6xxx_hwtstamp_setup(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void mv88e6xxx_hwtstamp_free(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #endif /* CONFIG_NET_DSA_MV88E6XXX_PTP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #endif /* _MV88E6XXX_HWTSTAMP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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