^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88E6xxx Switch Global 2 Registers support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _MV88E6XXX_GLOBAL2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _MV88E6XXX_GLOBAL2_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Offset 0x00: Interrupt Source Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MV88E6XXX_G2_INT_SRC 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MV88E6XXX_G2_INT_SRC_WDOG 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MV88E6XXX_G2_INT_SRC_JAM_LIMIT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MV88E6XXX_G2_INT_SRC_DUPLEX_MISMATCH 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MV88E6XXX_G2_INT_SRC_WAKE_EVENT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MV88E6352_G2_INT_SRC_SERDES 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MV88E6352_G2_INT_SRC_PHY 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MV88E6390_G2_INT_SRC_PHY 0x07fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MV88E6XXX_G2_INT_SOURCE_WATCHDOG 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Offset 0x01: Interrupt Mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MV88E6XXX_G2_INT_MASK 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MV88E6XXX_G2_INT_MASK_WDOG 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MV88E6XXX_G2_INT_MASK_JAM_LIMIT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MV88E6XXX_G2_INT_MASK_DUPLEX_MISMATCH 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MV88E6XXX_G2_INT_MASK_WAKE_EVENT 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MV88E6352_G2_INT_MASK_SERDES 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MV88E6352_G2_INT_MASK_PHY 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MV88E6390_G2_INT_MASK_PHY 0x07fe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* Offset 0x02: MGMT Enable Register 2x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MV88E6XXX_G2_MGMT_EN_2X 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Offset 0x03: MGMT Enable Register 0x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MV88E6XXX_G2_MGMT_EN_0X 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* Offset 0x04: Flow Control Delay Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MV88E6XXX_G2_FLOW_CTL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* Offset 0x05: Switch Management Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MV88E6XXX_G2_SWITCH_MGMT 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MV88E6XXX_G2_SWITCH_MGMT_USE_DOUBLE_TAG_DATA 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MV88E6XXX_G2_SWITCH_MGMT_PREVENT_LOOPS 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MV88E6XXX_G2_SWITCH_MGMT_FLOW_CTL_MSG 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MV88E6XXX_G2_SWITCH_MGMT_FORCE_FLOW_CTL_PRI 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MV88E6XXX_G2_SWITCH_MGMT_RSVD2CPU 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Offset 0x06: Device Mapping Table Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MV88E6XXX_G2_DEVICE_MAPPING 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MV88E6XXX_G2_DEVICE_MAPPING_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MV88E6XXX_G2_DEVICE_MAPPING_DEV_MASK 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MV88E6352_G2_DEVICE_MAPPING_PORT_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MV88E6390_G2_DEVICE_MAPPING_PORT_MASK 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Offset 0x07: Trunk Mask Table Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MV88E6XXX_G2_TRUNK_MASK 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MV88E6XXX_G2_TRUNK_MASK_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define MV88E6XXX_G2_TRUNK_MASK_NUM_MASK 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MV88E6XXX_G2_TRUNK_MASK_HASH 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Offset 0x08: Trunk Mapping Table Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MV88E6XXX_G2_TRUNK_MAPPING 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MV88E6XXX_G2_TRUNK_MAPPING_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MV88E6XXX_G2_TRUNK_MAPPING_ID_MASK 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Offset 0x09: Ingress Rate Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MV88E6XXX_G2_IRL_CMD 0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MV88E6XXX_G2_IRL_CMD_BUSY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MV88E6352_G2_IRL_CMD_OP_MASK 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define MV88E6352_G2_IRL_CMD_OP_NOOP 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MV88E6352_G2_IRL_CMD_OP_INIT_ALL 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MV88E6352_G2_IRL_CMD_OP_INIT_RES 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MV88E6352_G2_IRL_CMD_OP_WRITE_REG 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MV88E6352_G2_IRL_CMD_OP_READ_REG 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MV88E6390_G2_IRL_CMD_OP_MASK 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MV88E6390_G2_IRL_CMD_OP_READ_REG 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MV88E6390_G2_IRL_CMD_OP_INIT_ALL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MV88E6390_G2_IRL_CMD_OP_INIT_RES 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MV88E6390_G2_IRL_CMD_OP_WRITE_REG 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define MV88E6352_G2_IRL_CMD_PORT_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define MV88E6390_G2_IRL_CMD_PORT_MASK 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define MV88E6XXX_G2_IRL_CMD_RES_MASK 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define MV88E6XXX_G2_IRL_CMD_REG_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Offset 0x0A: Ingress Rate Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define MV88E6XXX_G2_IRL_DATA 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define MV88E6XXX_G2_IRL_DATA_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* Offset 0x0B: Cross-chip Port VLAN Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define MV88E6XXX_G2_PVT_ADDR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define MV88E6XXX_G2_PVT_ADDR_BUSY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define MV88E6XXX_G2_PVT_ADDR_OP_MASK 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MV88E6XXX_G2_PVT_ADDR_OP_INIT_ONES 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MV88E6XXX_G2_PVT_ADDR_OP_WRITE_PVLAN 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MV88E6XXX_G2_PVT_ADDR_OP_READ 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MV88E6XXX_G2_PVT_ADDR_PTR_MASK 0x01ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Offset 0x0C: Cross-chip Port VLAN Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MV88E6XXX_G2_PVT_DATA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MV88E6XXX_G2_PVT_DATA_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Offset 0x0D: Switch MAC/WoL/WoF Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MV88E6XXX_G2_SWITCH_MAC 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MV88E6XXX_G2_SWITCH_MAC_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MV88E6XXX_G2_SWITCH_MAC_PTR_MASK 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MV88E6XXX_G2_SWITCH_MAC_DATA_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Offset 0x0E: ATU Stats Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MV88E6XXX_G2_ATU_STATS 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MV88E6XXX_G2_ATU_STATS_BIN_0 (0x0 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MV88E6XXX_G2_ATU_STATS_BIN_1 (0x1 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MV88E6XXX_G2_ATU_STATS_BIN_2 (0x2 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MV88E6XXX_G2_ATU_STATS_BIN_3 (0x3 << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MV88E6XXX_G2_ATU_STATS_MODE_ALL (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MV88E6XXX_G2_ATU_STATS_MODE_ALL_DYNAMIC (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MV88E6XXX_G2_ATU_STATS_MODE_FID_ALL_DYNAMIC (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MV88E6XXX_G2_ATU_STATS_MASK 0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Offset 0x0F: Priority Override Table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MV88E6XXX_G2_PRIO_OVERRIDE 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MV88E6XXX_G2_PRIO_OVERRIDE_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MV88E6XXX_G2_PRIO_OVERRIDE_FPRISET 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MV88E6XXX_G2_PRIO_OVERRIDE_PTR_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MV88E6352_G2_PRIO_OVERRIDE_QPRIAVBEN 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MV88E6352_G2_PRIO_OVERRIDE_DATAAVB_MASK 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MV88E6XXX_G2_PRIO_OVERRIDE_QFPRIEN 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MV88E6XXX_G2_PRIO_OVERRIDE_DATA_MASK 0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* Offset 0x14: EEPROM Command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MV88E6XXX_G2_EEPROM_CMD 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MV88E6XXX_G2_EEPROM_CMD_BUSY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MV88E6XXX_G2_EEPROM_CMD_OP_MASK 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MV88E6XXX_G2_EEPROM_CMD_OP_WRITE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MV88E6XXX_G2_EEPROM_CMD_OP_READ 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MV88E6XXX_G2_EEPROM_CMD_OP_LOAD 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MV88E6XXX_G2_EEPROM_CMD_RUNNING 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MV88E6XXX_G2_EEPROM_CMD_WRITE_EN 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MV88E6352_G2_EEPROM_CMD_ADDR_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MV88E6390_G2_EEPROM_CMD_DATA_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* Offset 0x15: EEPROM Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MV88E6352_G2_EEPROM_DATA 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MV88E6352_G2_EEPROM_DATA_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* Offset 0x15: EEPROM Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MV88E6390_G2_EEPROM_ADDR 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MV88E6390_G2_EEPROM_ADDR_MASK 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* Offset 0x16: AVB Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MV88E6352_G2_AVB_CMD 0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MV88E6352_G2_AVB_CMD_BUSY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MV88E6352_G2_AVB_CMD_OP_READ 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MV88E6352_G2_AVB_CMD_OP_READ_INCR 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MV88E6352_G2_AVB_CMD_OP_WRITE 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MV88E6390_G2_AVB_CMD_OP_READ 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MV88E6390_G2_AVB_CMD_OP_READ_INCR 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define MV88E6390_G2_AVB_CMD_OP_WRITE 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define MV88E6352_G2_AVB_CMD_PORT_MASK 0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MV88E6352_G2_AVB_CMD_PORT_TAIGLOBAL 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MV88E6165_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MV88E6352_G2_AVB_CMD_PORT_PTPGLOBAL 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MV88E6390_G2_AVB_CMD_PORT_MASK 0x1f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define MV88E6390_G2_AVB_CMD_PORT_TAIGLOBAL 0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MV88E6390_G2_AVB_CMD_PORT_PTPGLOBAL 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MV88E6352_G2_AVB_CMD_BLOCK_PTP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define MV88E6352_G2_AVB_CMD_BLOCK_AVB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MV88E6352_G2_AVB_CMD_BLOCK_QAV 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define MV88E6352_G2_AVB_CMD_BLOCK_QVB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MV88E6352_G2_AVB_CMD_BLOCK_MASK 0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MV88E6352_G2_AVB_CMD_ADDR_MASK 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* Offset 0x17: AVB Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MV88E6352_G2_AVB_DATA 0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* Offset 0x18: SMI PHY Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MV88E6XXX_G2_SMI_PHY_CMD 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MV88E6XXX_G2_SMI_PHY_CMD_BUSY 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MV88E6390_G2_SMI_PHY_CMD_FUNC_MASK 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MV88E6390_G2_SMI_PHY_CMD_FUNC_INTERNAL 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define MV88E6390_G2_SMI_PHY_CMD_FUNC_EXTERNAL 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define MV88E6390_G2_SMI_PHY_CMD_FUNC_SETUP 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_MASK 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_45 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define MV88E6XXX_G2_SMI_PHY_CMD_MODE_22 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_MASK 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_WRITE_DATA 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_22_READ_DATA 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_ADDR 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_WRITE_DATA 0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA_INC 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MV88E6XXX_G2_SMI_PHY_CMD_OP_45_READ_DATA 0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MV88E6XXX_G2_SMI_PHY_CMD_DEV_ADDR_MASK 0x03e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MV88E6XXX_G2_SMI_PHY_CMD_REG_ADDR_MASK 0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define MV88E6XXX_G2_SMI_PHY_CMD_SETUP_PTR_MASK 0x03ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Offset 0x19: SMI PHY Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MV88E6XXX_G2_SMI_PHY_DATA 0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Offset 0x1A: Scratch and Misc. Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MV88E6XXX_G2_SCRATCH_MISC_MISC 0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MV88E6XXX_G2_SCRATCH_MISC_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MV88E6XXX_G2_SCRATCH_MISC_PTR_MASK 0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MV88E6XXX_G2_SCRATCH_MISC_DATA_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Offset 0x1B: Watch Dog Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MV88E6250_G2_WDOG_CTL 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MV88E6250_G2_WDOG_CTL_QC_HISTORY 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define MV88E6250_G2_WDOG_CTL_QC_EVENT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define MV88E6250_G2_WDOG_CTL_QC_ENABLE 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MV88E6250_G2_WDOG_CTL_EGRESS_HISTORY 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MV88E6250_G2_WDOG_CTL_EGRESS_EVENT 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MV88E6250_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MV88E6250_G2_WDOG_CTL_FORCE_IRQ 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MV88E6250_G2_WDOG_CTL_HISTORY 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MV88E6250_G2_WDOG_CTL_SWRESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Offset 0x1B: Watch Dog Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MV88E6352_G2_WDOG_CTL 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MV88E6352_G2_WDOG_CTL_EGRESS_EVENT 0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MV88E6352_G2_WDOG_CTL_RMU_TIMEOUT 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MV88E6352_G2_WDOG_CTL_QC_ENABLE 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MV88E6352_G2_WDOG_CTL_EGRESS_HISTORY 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MV88E6352_G2_WDOG_CTL_EGRESS_ENABLE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MV88E6352_G2_WDOG_CTL_FORCE_IRQ 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MV88E6352_G2_WDOG_CTL_HISTORY 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MV88E6352_G2_WDOG_CTL_SWRESET 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* Offset 0x1B: Watch Dog Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MV88E6390_G2_WDOG_CTL 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MV88E6390_G2_WDOG_CTL_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MV88E6390_G2_WDOG_CTL_PTR_MASK 0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MV88E6390_G2_WDOG_CTL_PTR_INT_SOURCE 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MV88E6390_G2_WDOG_CTL_PTR_INT_STS 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MV88E6390_G2_WDOG_CTL_PTR_INT_ENABLE 0x1100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MV88E6390_G2_WDOG_CTL_PTR_EVENT 0x1200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MV88E6390_G2_WDOG_CTL_PTR_HISTORY 0x1300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MV88E6390_G2_WDOG_CTL_DATA_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MV88E6390_G2_WDOG_CTL_CUT_THROUGH 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MV88E6390_G2_WDOG_CTL_QUEUE_CONTROLLER 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define MV88E6390_G2_WDOG_CTL_EGRESS 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define MV88E6390_G2_WDOG_CTL_FORCE_IRQ 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Offset 0x1C: QoS Weights Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MV88E6XXX_G2_QOS_WEIGHTS 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MV88E6XXX_G2_QOS_WEIGHTS_UPDATE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MV88E6352_G2_QOS_WEIGHTS_PTR_MASK 0x3f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MV88E6390_G2_QOS_WEIGHTS_PTR_MASK 0x7f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MV88E6XXX_G2_QOS_WEIGHTS_DATA_MASK 0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* Offset 0x1D: Misc Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MV88E6XXX_G2_MISC 0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MV88E6XXX_G2_MISC_5_BIT_PORT 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MV88E6352_G2_NOEGR_POLICY 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define MV88E6390_G2_LAG_ID_4 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* Scratch/Misc registers accessed through MV88E6XXX_G2_SCRATCH_MISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Offset 0x02: Misc Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MV88E6352_G2_SCRATCH_MISC_CFG 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MV88E6352_G2_SCRATCH_MISC_CFG_NORMALSMI 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) /* Offset 0x60-0x61: GPIO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define MV88E6352_G2_SCRATCH_GPIO_CFG0 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define MV88E6352_G2_SCRATCH_GPIO_CFG1 0x61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* Offset 0x62-0x63: GPIO Direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define MV88E6352_G2_SCRATCH_GPIO_DIR0 0x62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define MV88E6352_G2_SCRATCH_GPIO_DIR1 0x63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define MV88E6352_G2_SCRATCH_GPIO_DIR_OUT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define MV88E6352_G2_SCRATCH_GPIO_DIR_IN 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Offset 0x64-0x65: GPIO Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define MV88E6352_G2_SCRATCH_GPIO_DATA0 0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define MV88E6352_G2_SCRATCH_GPIO_DATA1 0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* Offset 0x68-0x6F: GPIO Pin Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define MV88E6352_G2_SCRATCH_GPIO_PCTL0 0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define MV88E6352_G2_SCRATCH_GPIO_PCTL1 0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define MV88E6352_G2_SCRATCH_GPIO_PCTL2 0x6A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define MV88E6352_G2_SCRATCH_GPIO_PCTL3 0x6B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define MV88E6352_G2_SCRATCH_GPIO_PCTL4 0x6C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define MV88E6352_G2_SCRATCH_GPIO_PCTL5 0x6D
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define MV88E6352_G2_SCRATCH_GPIO_PCTL6 0x6E
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define MV88E6352_G2_SCRATCH_GPIO_PCTL7 0x6F
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define MV88E6352_G2_SCRATCH_CONFIG_DATA0 0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MV88E6352_G2_SCRATCH_CONFIG_DATA1 0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MV88E6352_G2_SCRATCH_CONFIG_DATA1_NO_CPU BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define MV88E6352_G2_SCRATCH_CONFIG_DATA2 0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define MV88E6352_G2_SCRATCH_CONFIG_DATA2_P0_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MV88E6352_G2_SCRATCH_GPIO_PCTL_GPIO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define MV88E6352_G2_SCRATCH_GPIO_PCTL_TRIG 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define MV88E6352_G2_SCRATCH_GPIO_PCTL_EVREQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #ifdef CONFIG_NET_DSA_MV88E6XXX_GLOBAL2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int bit, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) int addr, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int addr, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct ethtool_eeprom *eeprom, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) struct ethtool_eeprom *eeprom, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct ethtool_eeprom *eeprom, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) struct ethtool_eeprom *eeprom, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip, int src_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int src_port, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct mii_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct mii_bus *bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip, int target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) extern const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) extern const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) extern const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) extern const struct mv88e6xxx_avb_ops mv88e6165_avb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) extern const struct mv88e6xxx_avb_ops mv88e6352_avb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) extern const struct mv88e6xxx_avb_ops mv88e6390_avb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) extern const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bool external);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip, u16 kind, u16 bin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip, u16 *stats);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #else /* !CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static inline int mv88e6xxx_g2_require(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (chip->info->global2_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_err(chip->dev, "this chip requires CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 enabled\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) static inline int mv88e6xxx_g2_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) static inline int mv88e6xxx_g2_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static inline int mv88e6xxx_g2_wait_bit(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) int reg, int bit, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) static inline int mv88e6352_g2_irl_init_all(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) static inline int mv88e6390_g2_irl_init_all(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static inline int mv88e6xxx_g2_smi_phy_read(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int addr, int reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) static inline int mv88e6xxx_g2_smi_phy_write(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) int addr, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static inline int mv88e6xxx_g2_set_switch_mac(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static inline int mv88e6xxx_g2_get_eeprom8(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static inline int mv88e6xxx_g2_set_eeprom8(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static inline int mv88e6xxx_g2_get_eeprom16(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static inline int mv88e6xxx_g2_set_eeprom16(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct ethtool_eeprom *eeprom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u8 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static inline int mv88e6xxx_g2_pvt_write(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int src_dev, int src_port, u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) static inline int mv88e6xxx_g2_misc_4_bit_port(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) static inline int mv88e6xxx_g2_irq_setup(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static inline void mv88e6xxx_g2_irq_free(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static inline int mv88e6xxx_g2_irq_mdio_setup(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) static inline void mv88e6xxx_g2_irq_mdio_free(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) struct mii_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) static inline int mv88e6185_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) static inline int mv88e6352_g2_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static inline int mv88e6xxx_g2_pot_clear(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static const struct mv88e6xxx_irq_ops mv88e6097_watchdog_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static const struct mv88e6xxx_irq_ops mv88e6250_watchdog_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static const struct mv88e6xxx_irq_ops mv88e6390_watchdog_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static const struct mv88e6xxx_avb_ops mv88e6165_avb_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) static const struct mv88e6xxx_avb_ops mv88e6352_avb_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) static const struct mv88e6xxx_avb_ops mv88e6390_avb_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static const struct mv88e6xxx_gpio_ops mv88e6352_gpio_ops = {};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static inline int mv88e6xxx_g2_scratch_gpio_set_smi(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) bool external)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static inline int mv88e6xxx_g2_trunk_clear(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static inline int mv88e6xxx_g2_device_mapping_write(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int target, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static inline int mv88e6xxx_g2_atu_stats_set(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) u16 kind, u16 bin)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static inline int mv88e6xxx_g2_atu_stats_get(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) u16 *stats)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #endif /* CONFIG_NET_DSA_MV88E6XXX_GLOBAL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #endif /* _MV88E6XXX_GLOBAL2_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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