Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell 88E6xxx Switch Global (1) Registers support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #ifndef _MV88E6XXX_GLOBAL1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define _MV88E6XXX_GLOBAL1_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* Offset 0x00: Switch Global Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define MV88E6XXX_G1_STS				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define MV88E6352_G1_STS_PPU_STATE			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define MV88E6185_G1_STS_PPU_STATE_MASK			0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define MV88E6185_G1_STS_PPU_STATE_DISABLED_RST		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define MV88E6185_G1_STS_PPU_STATE_INITIALIZING		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define MV88E6185_G1_STS_PPU_STATE_DISABLED		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define MV88E6185_G1_STS_PPU_STATE_POLLING		0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define MV88E6XXX_G1_STS_INIT_READY			0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define MV88E6XXX_G1_STS_IRQ_AVB			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define MV88E6XXX_G1_STS_IRQ_DEVICE			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define MV88E6XXX_G1_STS_IRQ_STATS			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define MV88E6XXX_G1_STS_IRQ_VTU_PROB			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define MV88E6XXX_G1_STS_IRQ_VTU_DONE			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define MV88E6XXX_G1_STS_IRQ_ATU_PROB			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define MV88E6XXX_G1_STS_IRQ_ATU_DONE			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define MV88E6XXX_G1_STS_IRQ_TCAM_DONE			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define MV88E6XXX_G1_STS_IRQ_EEPROM_DONE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define MV88E6XXX_G1_MAC_01		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define MV88E6XXX_G1_MAC_23		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define MV88E6XXX_G1_MAC_45		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) /* Offset 0x01: ATU FID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MV88E6352_G1_ATU_FID		0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) /* Offset 0x02: VTU FID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define MV88E6352_G1_VTU_FID		0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define MV88E6352_G1_VTU_FID_MASK	0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) /* Offset 0x03: VTU SID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define MV88E6352_G1_VTU_SID		0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define MV88E6352_G1_VTU_SID_MASK	0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* Offset 0x04: Switch Global Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define MV88E6XXX_G1_CTL1			0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define MV88E6XXX_G1_CTL1_SW_RESET		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define MV88E6XXX_G1_CTL1_PPU_ENABLE		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define MV88E6352_G1_CTL1_DISCARD_EXCESS	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define MV88E6185_G1_CTL1_SCHED_PRIO		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define MV88E6185_G1_CTL1_MAX_FRAME_1632	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define MV88E6185_G1_CTL1_RELOAD_EEPROM		0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define MV88E6XXX_G1_CTL1_DEVICE_EN		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define MV88E6XXX_G1_CTL1_STATS_DONE_EN		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define MV88E6XXX_G1_CTL1_VTU_PROBLEM_EN	0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define MV88E6XXX_G1_CTL1_VTU_DONE_EN		0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define MV88E6XXX_G1_CTL1_ATU_PROBLEM_EN	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MV88E6XXX_G1_CTL1_ATU_DONE_EN		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define MV88E6XXX_G1_CTL1_TCAM_EN		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define MV88E6XXX_G1_CTL1_EEPROM_DONE_EN	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* Offset 0x05: VTU Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define MV88E6XXX_G1_VTU_OP			0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define MV88E6XXX_G1_VTU_OP_BUSY		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define MV88E6XXX_G1_VTU_OP_MASK		0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define MV88E6XXX_G1_VTU_OP_FLUSH_ALL		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define MV88E6XXX_G1_VTU_OP_NOOP		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define MV88E6XXX_G1_VTU_OP_VTU_LOAD_PURGE	0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define MV88E6XXX_G1_VTU_OP_VTU_GET_NEXT	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define MV88E6XXX_G1_VTU_OP_STU_LOAD_PURGE	0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define MV88E6XXX_G1_VTU_OP_STU_GET_NEXT	0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define MV88E6XXX_G1_VTU_OP_GET_CLR_VIOLATION	0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define MV88E6XXX_G1_VTU_OP_MEMBER_VIOLATION	BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define MV88E6XXX_G1_VTU_OP_MISS_VIOLATION	BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define MV88E6XXX_G1_VTU_OP_SPID_MASK		0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Offset 0x06: VTU VID Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define MV88E6XXX_G1_VTU_VID		0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define MV88E6XXX_G1_VTU_VID_MASK	0x0fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define MV88E6390_G1_VTU_VID_PAGE	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define MV88E6XXX_G1_VTU_VID_VALID	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Offset 0x07: VTU/STU Data Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93)  * Offset 0x08: VTU/STU Data Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94)  * Offset 0x09: VTU/STU Data Register 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define MV88E6XXX_G1_VTU_DATA1				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define MV88E6XXX_G1_VTU_DATA2				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define MV88E6XXX_G1_VTU_DATA3				0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define MV88E6XXX_G1_VTU_STU_DATA_MASK			0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED		0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MV88E6XXX_G1_STU_DATA_PORT_STATE_DISABLED	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MV88E6XXX_G1_STU_DATA_PORT_STATE_BLOCKING	0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define MV88E6XXX_G1_STU_DATA_PORT_STATE_LEARNING	0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MV88E6XXX_G1_STU_DATA_PORT_STATE_FORWARDING	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Offset 0x0A: ATU Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define MV88E6XXX_G1_ATU_CTL		0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define MV88E6XXX_G1_ATU_CTL_LEARN2ALL	0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define MV88E6161_G1_ATU_CTL_HASH_MASK	0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* Offset 0x0B: ATU Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define MV88E6XXX_G1_ATU_OP				0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define MV88E6XXX_G1_ATU_OP_BUSY			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define MV88E6XXX_G1_ATU_OP_MASK			0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define MV88E6XXX_G1_ATU_OP_NOOP			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define MV88E6XXX_G1_ATU_OP_LOAD_DB			0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MV88E6XXX_G1_ATU_OP_GET_NEXT_DB			0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_ALL_DB		0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MV88E6XXX_G1_ATU_OP_FLUSH_MOVE_NON_STATIC_DB	0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MV88E6XXX_G1_ATU_OP_GET_CLR_VIOLATION		0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MV88E6XXX_G1_ATU_OP_AGE_OUT_VIOLATION		BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MV88E6XXX_G1_ATU_OP_MEMBER_VIOLATION		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MV88E6XXX_G1_ATU_OP_MISS_VIOLATION		BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MV88E6XXX_G1_ATU_OP_FULL_VIOLATION		BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Offset 0x0C: ATU Data Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MV88E6XXX_G1_ATU_DATA					0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MV88E6XXX_G1_ATU_DATA_TRUNK				0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MV88E6XXX_G1_ATU_DATA_TRUNK_ID_MASK			0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MV88E6XXX_G1_ATU_DATA_PORT_VECTOR_MASK			0x3ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MV88E6XXX_G1_ATU_DATA_STATE_MASK			0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_UNUSED			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_1_OLDEST		0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_2			0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_3			0x0003
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_4			0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_5			0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_6			0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_AGE_7_NEWEST		0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY		0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY_PO		0x0009
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL		0x000a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_AVB_NRL_PO	0x000b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_DA_MGMT_PO	0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC			0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_PO		0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED			0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY		0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL		0x0005
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT		0x0006
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC			0x0007
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY_PO		0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_AVB_NRL_PO	0x000d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_DA_MGMT_PO	0x000e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_PO		0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Offset 0x0D: ATU MAC Address Register Bytes 0 & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * Offset 0x0E: ATU MAC Address Register Bytes 2 & 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * Offset 0x0F: ATU MAC Address Register Bytes 4 & 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define MV88E6XXX_G1_ATU_MAC01		0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define MV88E6XXX_G1_ATU_MAC23		0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define MV88E6XXX_G1_ATU_MAC45		0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* Offset 0x10: IP-PRI Mapping Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * Offset 0x11: IP-PRI Mapping Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * Offset 0x12: IP-PRI Mapping Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  * Offset 0x13: IP-PRI Mapping Register 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)  * Offset 0x14: IP-PRI Mapping Register 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)  * Offset 0x15: IP-PRI Mapping Register 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)  * Offset 0x16: IP-PRI Mapping Register 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)  * Offset 0x17: IP-PRI Mapping Register 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MV88E6XXX_G1_IP_PRI_0	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define MV88E6XXX_G1_IP_PRI_1	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define MV88E6XXX_G1_IP_PRI_2	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define MV88E6XXX_G1_IP_PRI_3	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define MV88E6XXX_G1_IP_PRI_4	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define MV88E6XXX_G1_IP_PRI_5	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define MV88E6XXX_G1_IP_PRI_6	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define MV88E6XXX_G1_IP_PRI_7	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Offset 0x18: IEEE-PRI Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define MV88E6XXX_G1_IEEE_PRI	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /* Offset 0x19: Core Tag Type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define MV88E6185_G1_CORE_TAG_TYPE	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Offset 0x1A: Monitor Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define MV88E6185_G1_MONITOR_CTL			0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK	0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK	0x0f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK	        0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define MV88E6352_G1_MONITOR_CTL_CPU_DEST_MASK	        0x00f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define MV88E6352_G1_MONITOR_CTL_MIRROR_DEST_MASK	0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Offset 0x1A: Monitor & MGMT Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MV88E6390_G1_MONITOR_MGMT_CTL				0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE			0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_MASK			0x3f00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI	0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST		0x2100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST		0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI	0x00e0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define MV88E6390_G1_MONITOR_MGMT_CTL_DATA_MASK			0x00ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* Offset 0x1C: Global Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define MV88E6XXX_G1_CTL2			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MV88E6185_G1_CTL2_CASCADE_PORT_MASK	0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MV88E6185_G1_CTL2_CASCADE_PORT_NONE	0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define MV88E6185_G1_CTL2_CASCADE_PORT_MULTI	0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define MV88E6352_G1_CTL2_HEADER_TYPE_MASK	0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define MV88E6352_G1_CTL2_HEADER_TYPE_ORIG	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define MV88E6352_G1_CTL2_HEADER_TYPE_MGMT	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define MV88E6390_G1_CTL2_HEADER_TYPE_LAG	0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define MV88E6352_G1_CTL2_RMU_MODE_MASK		0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define MV88E6352_G1_CTL2_RMU_MODE_DISABLED	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MV88E6352_G1_CTL2_RMU_MODE_PORT_4	0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MV88E6352_G1_CTL2_RMU_MODE_PORT_5	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define MV88E6352_G1_CTL2_RMU_MODE_PORT_6	0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MV88E6085_G1_CTL2_DA_CHECK		0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define MV88E6085_G1_CTL2_P10RM			0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define MV88E6085_G1_CTL2_RM_ENABLE		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MV88E6352_G1_CTL2_DA_CHECK		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define MV88E6390_G1_CTL2_RMU_MODE_MASK		0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define MV88E6390_G1_CTL2_RMU_MODE_PORT_0	0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define MV88E6390_G1_CTL2_RMU_MODE_PORT_1	0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define MV88E6390_G1_CTL2_RMU_MODE_PORT_9	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define MV88E6390_G1_CTL2_RMU_MODE_PORT_10	0x0300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define MV88E6390_G1_CTL2_RMU_MODE_ALL_DSA	0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define MV88E6390_G1_CTL2_RMU_MODE_DISABLED	0x0700
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define MV88E6390_G1_CTL2_HIST_MODE_MASK	0x00c0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define MV88E6390_G1_CTL2_HIST_MODE_RX		0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define MV88E6390_G1_CTL2_HIST_MODE_TX		0x0080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define MV88E6352_G1_CTL2_CTR_MODE_MASK		0x0060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define MV88E6390_G1_CTL2_CTR_MODE		0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK	0x001f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Offset 0x1D: Stats Operation Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define MV88E6XXX_G1_STATS_OP			0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MV88E6XXX_G1_STATS_OP_BUSY		0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MV88E6XXX_G1_STATS_OP_NOP		0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MV88E6XXX_G1_STATS_OP_FLUSH_ALL		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MV88E6XXX_G1_STATS_OP_FLUSH_PORT	0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MV88E6XXX_G1_STATS_OP_READ_CAPTURED	0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MV88E6XXX_G1_STATS_OP_CAPTURE_PORT	0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define MV88E6XXX_G1_STATS_OP_HIST_RX		0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define MV88E6XXX_G1_STATS_OP_HIST_TX		0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define MV88E6XXX_G1_STATS_OP_HIST_RX_TX	0x0c00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9	0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10	0x0400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* Offset 0x1E: Stats Counter Register Bytes 3 & 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * Offset 0x1F: Stats Counter Register Bytes 1 & 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define MV88E6XXX_G1_STATS_COUNTER_32	0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define MV88E6XXX_G1_STATS_COUNTER_01	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 			  bit, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 			   u16 mask, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 				 enum mv88e6xxx_egress_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 				 int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 				 enum mv88e6xxx_egress_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 				 int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) int mv88e6xxx_g1_atu_set_learn2all(struct mv88e6xxx_chip *chip, bool learn2all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int mv88e6xxx_g1_atu_set_age_time(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 				  unsigned int msecs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) int mv88e6xxx_g1_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 			     struct mv88e6xxx_atu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) int mv88e6xxx_g1_atu_loadpurge(struct mv88e6xxx_chip *chip, u16 fid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			       struct mv88e6xxx_atu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) int mv88e6xxx_g1_atu_flush(struct mv88e6xxx_chip *chip, u16 fid, bool all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int mv88e6xxx_g1_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 			    bool all);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int mv88e6xxx_g1_atu_prob_irq_setup(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void mv88e6xxx_g1_atu_prob_irq_free(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) int mv88e6165_g1_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int mv88e6165_g1_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 			     struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 			       struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) int mv88e6250_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 			     struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) int mv88e6250_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 			       struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 			     struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 			       struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) int mv88e6390_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 			     struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) int mv88e6390_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 			       struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) int mv88e6xxx_g1_vtu_prob_irq_setup(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) void mv88e6xxx_g1_vtu_prob_irq_free(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) int mv88e6xxx_g1_atu_get_next(struct mv88e6xxx_chip *chip, u16 fid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #endif /* _MV88E6XXX_GLOBAL1_H */