Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Marvell 88E6xxx Switch Global (1) Registers support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include "chip.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include "global1.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) int mv88e6xxx_g1_read(struct mv88e6xxx_chip *chip, int reg, u16 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 	int addr = chip->info->global1_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 	return mv88e6xxx_read(chip, addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) int mv88e6xxx_g1_write(struct mv88e6xxx_chip *chip, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 	int addr = chip->info->global1_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	return mv88e6xxx_write(chip, addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) int mv88e6xxx_g1_wait_bit(struct mv88e6xxx_chip *chip, int reg, int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 			  bit, int val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	return mv88e6xxx_wait_bit(chip, chip->info->global1_addr, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) 				  bit, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) int mv88e6xxx_g1_wait_mask(struct mv88e6xxx_chip *chip, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 			   u16 mask, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	return mv88e6xxx_wait_mask(chip, chip->info->global1_addr, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 				   mask, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* Offset 0x00: Switch Global Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) static int mv88e6185_g1_wait_ppu_disabled(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 				      MV88E6185_G1_STS_PPU_STATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 				      MV88E6185_G1_STS_PPU_STATE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) static int mv88e6185_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 	return mv88e6xxx_g1_wait_mask(chip, MV88E6XXX_G1_STS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 				      MV88E6185_G1_STS_PPU_STATE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 				      MV88E6185_G1_STS_PPU_STATE_POLLING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) static int mv88e6352_g1_wait_ppu_polling(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	int bit = __bf_shf(MV88E6352_G1_STS_PPU_STATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) static int mv88e6xxx_g1_wait_init_ready(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	int bit = __bf_shf(MV88E6XXX_G1_STS_INIT_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	/* Wait up to 1 second for the switch to be ready. The InitReady bit 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	 * is set to a one when all units inside the device (ATU, VTU, etc.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	 * have finished their initialization and are ready to accept frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STS, bit, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) void mv88e6xxx_g1_wait_eeprom_done(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	const unsigned long timeout = jiffies + 1 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	/* Wait up to 1 second for the switch to finish reading the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	 * EEPROM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 		err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 		if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 			dev_err(chip->dev, "Error reading status");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 		/* If the switch is still resetting, it may not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 		 * respond on the bus, and so MDIO read returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 		 * 0xffff. Differentiate between that, and waiting for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 		 * the EEPROM to be done by bit 0 being set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 		 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		if (val != 0xffff &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		    val & BIT(MV88E6XXX_G1_STS_IRQ_EEPROM_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 			return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 		usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	dev_err(chip->dev, "Timeout waiting for EEPROM done");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Offset 0x01: Switch MAC Address Register Bytes 0 & 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)  * Offset 0x02: Switch MAC Address Register Bytes 2 & 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)  * Offset 0x03: Switch MAC Address Register Bytes 4 & 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	reg = (addr[0] << 8) | addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_01, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	reg = (addr[2] << 8) | addr[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_23, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	reg = (addr[4] << 8) | addr[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_MAC_45, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Offset 0x04: Switch Global Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) int mv88e6185_g1_reset(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	/* Set the SWReset bit 15 along with the PPUEn bit 14, to also restart
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	 * the PPU, including re-doing PHY detection and initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	val |= MV88E6XXX_G1_CTL1_SW_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	err = mv88e6xxx_g1_wait_init_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	return mv88e6185_g1_wait_ppu_polling(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int mv88e6250_g1_reset(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	/* Set the SWReset bit 15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 	val |= MV88E6XXX_G1_CTL1_SW_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	return mv88e6xxx_g1_wait_init_ready(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) int mv88e6352_g1_reset(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	err = mv88e6250_g1_reset(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	return mv88e6352_g1_wait_ppu_polling(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) int mv88e6185_g1_ppu_enable(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	val |= MV88E6XXX_G1_CTL1_PPU_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	return mv88e6185_g1_wait_ppu_polling(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) int mv88e6185_g1_ppu_disable(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 	val &= ~MV88E6XXX_G1_CTL1_PPU_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	return mv88e6185_g1_wait_ppu_disabled(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int mv88e6185_g1_set_max_frame_size(struct mv88e6xxx_chip *chip, int mtu)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	mtu += ETH_HLEN + ETH_FCS_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	val &= ~MV88E6185_G1_CTL1_MAX_FRAME_1632;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	if (mtu > 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 		val |= MV88E6185_G1_CTL1_MAX_FRAME_1632;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* Offset 0x10: IP-PRI Mapping Register 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)  * Offset 0x11: IP-PRI Mapping Register 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)  * Offset 0x12: IP-PRI Mapping Register 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)  * Offset 0x13: IP-PRI Mapping Register 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)  * Offset 0x14: IP-PRI Mapping Register 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)  * Offset 0x15: IP-PRI Mapping Register 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)  * Offset 0x16: IP-PRI Mapping Register 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)  * Offset 0x17: IP-PRI Mapping Register 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) int mv88e6085_g1_ip_pri_map(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	/* Reset the IP TOS/DiffServ/Traffic priorities to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* Offset 0x18: IEEE-PRI Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) int mv88e6085_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	/* Reset the IEEE Tag priorities to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) int mv88e6250_g1_ieee_pri_map(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	/* Reset the IEEE Tag priorities to defaults */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa50);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* Offset 0x1a: Monitor Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* Offset 0x1a: Monitor & MGMT Control on some devices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) int mv88e6095_g1_set_egress_port(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 				 enum mv88e6xxx_egress_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 				 int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	int *dest_port_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	case MV88E6XXX_EGRESS_DIR_INGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 		dest_port_chip = &chip->ingress_dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 		reg &= ~MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 		reg |= port <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 		       __bf_shf(MV88E6185_G1_MONITOR_CTL_INGRESS_DEST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	case MV88E6XXX_EGRESS_DIR_EGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 		dest_port_chip = &chip->egress_dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 		reg &= ~MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 		reg |= port <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 		       __bf_shf(MV88E6185_G1_MONITOR_CTL_EGRESS_DEST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 	err = mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 		*dest_port_chip = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Older generations also call this the ARP destination. It has been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)  * generalized in more modern devices such that more than ARP can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)  * egress it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) int mv88e6095_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 	err = mv88e6xxx_g1_read(chip, MV88E6185_G1_MONITOR_CTL, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	reg &= ~MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 	reg |= port << __bf_shf(MV88E6185_G1_MONITOR_CTL_ARP_DEST_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 	return mv88e6xxx_g1_write(chip, MV88E6185_G1_MONITOR_CTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) static int mv88e6390_g1_monitor_write(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 				      u16 pointer, u8 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 	reg = MV88E6390_G1_MONITOR_MGMT_CTL_UPDATE | pointer | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 	return mv88e6xxx_g1_write(chip, MV88E6390_G1_MONITOR_MGMT_CTL, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) int mv88e6390_g1_set_egress_port(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 				 enum mv88e6xxx_egress_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 				 int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	int *dest_port_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	u16 ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	switch (direction) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	case MV88E6XXX_EGRESS_DIR_INGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) 		dest_port_chip = &chip->ingress_dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_INGRESS_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) 	case MV88E6XXX_EGRESS_DIR_EGRESS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		dest_port_chip = &chip->egress_dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 		ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_EGRESS_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 		break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 	default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	err = mv88e6390_g1_monitor_write(chip, ptr, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) 	if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 		*dest_port_chip = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) int mv88e6390_g1_set_cpu_port(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 	u16 ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 	/* Use the default high priority for management frames sent to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 	 * the CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) 	port |= MV88E6390_G1_MONITOR_MGMT_CTL_PTR_CPU_DEST_MGMTPRI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) 	return mv88e6390_g1_monitor_write(chip, ptr, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int mv88e6390_g1_mgmt_rsvd2cpu(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 	u16 ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) 	/* 01:80:c2:00:00:00-01:80:c2:00:00:07 are Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	/* 01:80:c2:00:00:08-01:80:c2:00:00:0f are Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200000XHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	/* 01:80:c2:00:00:20-01:80:c2:00:00:27 are Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XLO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 	/* 01:80:c2:00:00:28-01:80:c2:00:00:2f are Management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 	ptr = MV88E6390_G1_MONITOR_MGMT_CTL_PTR_0180C200002XHI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 	err = mv88e6390_g1_monitor_write(chip, ptr, 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Offset 0x1c: Global Control 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int mv88e6xxx_g1_ctl2_mask(struct mv88e6xxx_chip *chip, u16 mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 				  u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL2, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	reg &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 	reg |= val & mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 	return mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) int mv88e6185_g1_set_cascade_port(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	const u16 mask = MV88E6185_G1_CTL2_CASCADE_PORT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 	return mv88e6xxx_g1_ctl2_mask(chip, mask, port << __bf_shf(mask));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int mv88e6085_g1_rmu_disable(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6085_G1_CTL2_P10RM |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 				      MV88E6085_G1_CTL2_RM_ENABLE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) int mv88e6352_g1_rmu_disable(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6352_G1_CTL2_RMU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 				      MV88E6352_G1_CTL2_RMU_MODE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) int mv88e6390_g1_rmu_disable(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_RMU_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 				      MV88E6390_G1_CTL2_RMU_MODE_DISABLED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int mv88e6390_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) 	return mv88e6xxx_g1_ctl2_mask(chip, MV88E6390_G1_CTL2_HIST_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) 				      MV88E6390_G1_CTL2_HIST_MODE_RX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 				      MV88E6390_G1_CTL2_HIST_MODE_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int mv88e6xxx_g1_set_device_number(struct mv88e6xxx_chip *chip, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) 	return mv88e6xxx_g1_ctl2_mask(chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 				      MV88E6XXX_G1_CTL2_DEVICE_NUMBER_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) 				      index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) /* Offset 0x1d: Statistics Operation 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static int mv88e6xxx_g1_stats_wait(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	int bit = __bf_shf(MV88E6XXX_G1_STATS_OP_BUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	return mv88e6xxx_g1_wait_bit(chip, MV88E6XXX_G1_STATS_OP, bit, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) int mv88e6095_g1_stats_set_histogram(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	val |= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) int mv88e6xxx_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 	/* Snapshot the hardware statistics counters for this port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 				 MV88E6XXX_G1_STATS_OP_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 				 MV88E6XXX_G1_STATS_OP_HIST_RX_TX | port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 	/* Wait for the snapshotting to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	return mv88e6xxx_g1_stats_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) int mv88e6320_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	port = (port + 1) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	return mv88e6xxx_g1_stats_snapshot(chip, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) int mv88e6390_g1_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	port = (port + 1) << 5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	/* Snapshot the hardware statistics counters for this port. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 				 MV88E6XXX_G1_STATS_OP_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 				 MV88E6XXX_G1_STATS_OP_CAPTURE_PORT | port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	/* Wait for the snapshotting to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 	return mv88e6xxx_g1_stats_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void mv88e6xxx_g1_stats_read(struct mv88e6xxx_chip *chip, int stat, u32 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 	u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	*val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 				 MV88E6XXX_G1_STATS_OP_BUSY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 				 MV88E6XXX_G1_STATS_OP_READ_CAPTURED | stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) 	err = mv88e6xxx_g1_stats_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_32, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	value = reg << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_COUNTER_01, &reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 	*val = value | reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) int mv88e6xxx_g1_stats_clear(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) 	int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) 	u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STATS_OP, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) 	/* Keep the histogram mode bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) 	val &= MV88E6XXX_G1_STATS_OP_HIST_RX_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) 	val |= MV88E6XXX_G1_STATS_OP_BUSY | MV88E6XXX_G1_STATS_OP_FLUSH_ALL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) 	if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) 		return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) 	/* Wait for the flush to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) 	return mv88e6xxx_g1_stats_wait(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }