^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Marvell 88E6xxx Ethernet switch single-chip definition
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _MV88E6XXX_CHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _MV88E6XXX_CHIP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/if_vlan.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/ptp_clock_kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/timecounter.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EDSA_HLEN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MV88E6XXX_N_FID 4096
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* PVT limits for 4-bit port and 5-bit switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MV88E6XXX_MAX_PVT_SWITCHES 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MV88E6XXX_MAX_PVT_PORTS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MV88E6XXX_MAX_GPIO 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) enum mv88e6xxx_egress_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MV88E6XXX_EGRESS_MODE_UNMODIFIED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MV88E6XXX_EGRESS_MODE_UNTAGGED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MV88E6XXX_EGRESS_MODE_TAGGED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MV88E6XXX_EGRESS_MODE_ETHERTYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) enum mv88e6xxx_egress_direction {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MV88E6XXX_EGRESS_DIR_INGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MV88E6XXX_EGRESS_DIR_EGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) enum mv88e6xxx_frame_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MV88E6XXX_FRAME_MODE_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MV88E6XXX_FRAME_MODE_DSA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MV88E6XXX_FRAME_MODE_PROVIDER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MV88E6XXX_FRAME_MODE_ETHERTYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* List of supported models */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) enum mv88e6xxx_model {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MV88E6085,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MV88E6095,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MV88E6097,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MV88E6123,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MV88E6131,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MV88E6141,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MV88E6161,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MV88E6165,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MV88E6171,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MV88E6172,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MV88E6175,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MV88E6176,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MV88E6185,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MV88E6190,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MV88E6190X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MV88E6191,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MV88E6220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MV88E6240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MV88E6250,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) MV88E6290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) MV88E6320,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) MV88E6321,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) MV88E6341,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) MV88E6350,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) MV88E6351,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) MV88E6352,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) MV88E6390,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) MV88E6390X,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) enum mv88e6xxx_family {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) MV88E6XXX_FAMILY_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) MV88E6XXX_FAMILY_6065, /* 6031 6035 6061 6065 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) MV88E6XXX_FAMILY_6095, /* 6092 6095 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) MV88E6XXX_FAMILY_6097, /* 6046 6085 6096 6097 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) MV88E6XXX_FAMILY_6165, /* 6123 6161 6165 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) MV88E6XXX_FAMILY_6185, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) MV88E6XXX_FAMILY_6250, /* 6220 6250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) MV88E6XXX_FAMILY_6320, /* 6320 6321 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) MV88E6XXX_FAMILY_6341, /* 6141 6341 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) MV88E6XXX_FAMILY_6351, /* 6171 6175 6350 6351 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MV88E6XXX_FAMILY_6352, /* 6172 6176 6240 6352 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MV88E6XXX_FAMILY_6390, /* 6190 6190X 6191 6290 6390 6390X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct mv88e6xxx_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) struct mv88e6xxx_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum mv88e6xxx_family family;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u16 prod_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int num_databases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int num_macs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int num_internal_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int num_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int max_vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int port_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int phy_base_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int global1_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int global2_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int age_time_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int g1_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int g2_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Mark certain ports as invalid. This is required for example for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * MV88E6220 (which is in general a MV88E6250 with 7 ports) but the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * ports 2-4 are not routet to pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int invalid_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Multi-chip Addressing Mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * Some chips respond to only 2 registers of its own SMI device address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * when it is non-zero, and use indirect access to internal registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bool multi_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Dual-chip Addressing Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Some chips respond to only half of the 32 SMI addresses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * allowing two to coexist on the same SMI interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bool dual_chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum dsa_tag_protocol tag_protocol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Mask for FromPort and ToPort value of PortVec used in ATU Move
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * operation. 0 means that the ATU Move operation is not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u8 atu_move_port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) const struct mv88e6xxx_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Supports PTP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool ptp_support;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct mv88e6xxx_atu_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) bool trunk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u16 portvec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 mac[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct mv88e6xxx_vtu_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u16 fid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u8 sid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) bool valid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u8 member[DSA_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 state[DSA_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct mv88e6xxx_bus_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct mv88e6xxx_irq_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct mv88e6xxx_gpio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct mv88e6xxx_avb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct mv88e6xxx_ptp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) struct mv88e6xxx_irq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) u16 masked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct irq_chip chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct irq_domain *domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int nirqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* state flags for mv88e6xxx_port_hwtstamp::state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) MV88E6XXX_HWTSTAMP_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) struct mv88e6xxx_port_hwtstamp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Port index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) int port_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Timestamping state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* Resources for receive timestamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct sk_buff_head rx_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct sk_buff_head rx_queue2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* Resources for transmit timestamping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned long tx_tstamp_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct sk_buff *tx_skb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u16 tx_seq_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* Current timestamp configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct hwtstamp_config tstamp_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) enum mv88e6xxx_policy_mapping {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) MV88E6XXX_POLICY_MAPPING_DA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MV88E6XXX_POLICY_MAPPING_SA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) MV88E6XXX_POLICY_MAPPING_VTU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) MV88E6XXX_POLICY_MAPPING_ETYPE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) MV88E6XXX_POLICY_MAPPING_PPPOE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) MV88E6XXX_POLICY_MAPPING_VBAS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) MV88E6XXX_POLICY_MAPPING_OPT82,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MV88E6XXX_POLICY_MAPPING_UDP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) enum mv88e6xxx_policy_action {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) MV88E6XXX_POLICY_ACTION_NORMAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) MV88E6XXX_POLICY_ACTION_MIRROR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MV88E6XXX_POLICY_ACTION_TRAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MV88E6XXX_POLICY_ACTION_DISCARD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct mv88e6xxx_policy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) enum mv88e6xxx_policy_mapping mapping;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum mv88e6xxx_policy_action action;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct ethtool_rx_flow_spec fs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) u8 addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct mv88e6xxx_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct mv88e6xxx_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u64 serdes_stats[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u64 atu_member_violation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) u64 atu_miss_violation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u64 atu_full_violation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 vtu_member_violation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u64 vtu_miss_violation;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) phy_interface_t interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u8 cmode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) bool mirror_ingress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) bool mirror_egress;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) unsigned int serdes_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) char serdes_irq_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct devlink_region *region;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) enum mv88e6xxx_region_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) MV88E6XXX_REGION_GLOBAL1 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) MV88E6XXX_REGION_GLOBAL2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) MV88E6XXX_REGION_ATU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) _MV88E6XXX_REGION_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct mv88e6xxx_region_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) enum mv88e6xxx_region_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mv88e6xxx_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) const struct mv88e6xxx_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* The dsa_switch this private structure is related to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* The device this structure is associated to */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* This mutex protects the access to the switch registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct mutex reg_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* The MII bus and the address on the bus that is used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * communication with the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) const struct mv88e6xxx_bus_ops *smi_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int sw_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* Handles automatic disabling and re-enabling of the PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * polling unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) const struct mv88e6xxx_bus_ops *phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct mutex ppu_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int ppu_disabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct work_struct ppu_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct timer_list ppu_timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* This mutex serialises access to the statistics unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Hold this mutex over snapshot + dump sequences.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct mutex stats_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* A switch may have a GPIO line tied to its reset pin. Parse
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * this from the device tree, and use it before performing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * switch soft reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) /* set to size of eeprom if supported by the switch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 eeprom_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) /* List of mdio busses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) struct list_head mdios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) /* Policy Control List IDs and rules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct idr policies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* There can be two interrupt controllers, which are chained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * off a GPIO as interrupt source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct mv88e6xxx_irq g1_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct mv88e6xxx_irq g2_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) char irq_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) int device_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) char device_irq_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) int watchdog_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) char watchdog_irq_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) int atu_prob_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) char atu_prob_irq_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int vtu_prob_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) char vtu_prob_irq_name[64];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct kthread_worker *kworker;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct kthread_delayed_work irq_poll_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* GPIO resources */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) u8 gpio_data[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* This cyclecounter abstracts the switch PTP time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * reg_lock must be held for any operation that read()s.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct cyclecounter tstamp_cc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct timecounter tstamp_tc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) struct delayed_work overflow_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct ptp_clock *ptp_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) struct ptp_clock_info ptp_clock_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct delayed_work tai_event_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) struct ptp_pin_desc pin_config[MV88E6XXX_MAX_GPIO];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) u16 trig_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) u16 evcap_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) u16 enable_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Current ingress and egress monitor ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) int egress_dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) int ingress_dest_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Per-port timestamping resources. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mv88e6xxx_port_hwtstamp port_hwtstamp[DSA_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) /* Array of port structures. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct mv88e6xxx_port ports[DSA_MAX_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* devlink regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct devlink_region *regions[_MV88E6XXX_REGION_MAX];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) struct mv88e6xxx_bus_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) int (*read)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) int (*write)(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mv88e6xxx_mdio_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct mv88e6xxx_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bool external;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct mv88e6xxx_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Switch Setup Errata, called early in the switch setup to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * allow any errata actions to be performed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int (*setup_errata)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) int (*ieee_pri_map)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) int (*ip_pri_map)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Ingress Rate Limit unit (IRL) operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int (*irl_init_all)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) int (*get_eeprom)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct ethtool_eeprom *eeprom, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int (*set_eeprom)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ethtool_eeprom *eeprom, u8 *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int (*set_switch_mac)(struct mv88e6xxx_chip *chip, u8 *addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) int (*phy_read)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int addr, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) int (*phy_write)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct mii_bus *bus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int addr, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /* Priority Override Table operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int (*pot_clear)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* PHY Polling Unit (PPU) operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int (*ppu_enable)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) int (*ppu_disable)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* Switch Software Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) int (*reset)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /* RGMII Receive/Transmit Timing Control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) int (*port_set_rgmii_delay)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) phy_interface_t mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define LINK_FORCED_DOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define LINK_FORCED_UP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define LINK_UNFORCED -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* Port's MAC link state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * or LINK_UNFORCED for normal link detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int (*port_set_link)(struct mv88e6xxx_chip *chip, int port, int link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define PAUSE_ON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define PAUSE_OFF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) /* Enable/disable sending Pause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int (*port_set_pause)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) int pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SPEED_MAX INT_MAX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SPEED_UNFORCED -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define DUPLEX_UNFORCED -2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /* Port's MAC speed (in Mbps) and MAC duplex mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * or DUPLEX_UNFORCED for normal duplex detection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int (*port_set_speed_duplex)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) int speed, int duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* What interface mode should be used for maximum speed? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) phy_interface_t (*port_max_speed_mode)(int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) int (*port_tag_remap)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int (*port_set_policy)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) enum mv88e6xxx_policy_mapping mapping,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) enum mv88e6xxx_policy_action action);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) int (*port_set_frame_mode)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) enum mv88e6xxx_frame_mode mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) int (*port_set_egress_floods)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) bool unicast, bool multicast);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) int (*port_set_ether_type)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) u16 etype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) size_t size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) u8 out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int (*port_disable_pri_override)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int (*port_setup_message_port)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * Some chips allow this to be configured on specific ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) int (*port_set_cmode)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) phy_interface_t mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) int (*port_get_cmode)(struct mv88e6xxx_chip *chip, int port, u8 *cmode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Some devices have a per port register indicating what is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * the upstream port this port should forward to.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) int (*port_set_upstream_port)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int upstream_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) /* Snapshot the statistics for a port. The statistics can then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * be read back a leisure but still with a consistent view.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) int (*stats_snapshot)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Set the histogram mode for statistics, when the control registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * are separated out of the STATS_OP register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) int (*stats_set_histogram)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Return the number of strings describing statistics */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) int (*stats_get_sset_count)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int (*stats_get_strings)(struct mv88e6xxx_chip *chip, uint8_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) int (*stats_get_stats)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) uint64_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) int (*set_cpu_port)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) int (*set_egress_port)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) enum mv88e6xxx_egress_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define MV88E6XXX_CASCADE_PORT_NONE 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) int (*set_cascade_port)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) const struct mv88e6xxx_irq_ops *watchdog_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int (*mgmt_rsvd2cpu)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Power on/off a SERDES interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) int (*serdes_power)(struct mv88e6xxx_chip *chip, int port, u8 lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) bool up);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* SERDES lane mapping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) u8 (*serdes_get_lane)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) int (*serdes_pcs_get_state)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) u8 lane, struct phylink_link_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) int (*serdes_pcs_config)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 lane, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) const unsigned long *advertise);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) int (*serdes_pcs_an_restart)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u8 lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int (*serdes_pcs_link_up)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) u8 lane, int speed, int duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /* SERDES interrupt handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) unsigned int (*serdes_irq_mapping)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int (*serdes_irq_enable)(struct mv88e6xxx_chip *chip, int port, u8 lane,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) bool enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) irqreturn_t (*serdes_irq_status)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u8 lane);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Statistics from the SERDES interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) int (*serdes_get_sset_count)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) int (*serdes_get_strings)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) uint8_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) int (*serdes_get_stats)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) uint64_t *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* SERDES registers for ethtool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) int (*serdes_get_regs_len)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) void (*serdes_get_regs)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) void *_p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Address Translation Unit operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) int (*atu_get_hash)(struct mv88e6xxx_chip *chip, u8 *hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) int (*atu_set_hash)(struct mv88e6xxx_chip *chip, u8 hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /* VLAN Translation Unit operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) int (*vtu_getnext)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) int (*vtu_loadpurge)(struct mv88e6xxx_chip *chip,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct mv88e6xxx_vtu_entry *entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /* GPIO operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) const struct mv88e6xxx_gpio_ops *gpio_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /* Interface to the AVB/PTP registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) const struct mv88e6xxx_avb_ops *avb_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* Remote Management Unit operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) int (*rmu_disable)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) /* Precision Time Protocol operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) const struct mv88e6xxx_ptp_ops *ptp_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /* Phylink */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) void (*phylink_validate)(struct mv88e6xxx_chip *chip, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) unsigned long *mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) struct phylink_link_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Max Frame Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) int (*set_max_frame_size)(struct mv88e6xxx_chip *chip, int mtu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) struct mv88e6xxx_irq_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Action to be performed when the interrupt happens */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int (*irq_action)(struct mv88e6xxx_chip *chip, int irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Setup the hardware to generate the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) int (*irq_setup)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Reset the hardware to stop generating the interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) void (*irq_free)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct mv88e6xxx_gpio_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Get/set data on GPIO pin */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) int (*get_data)(struct mv88e6xxx_chip *chip, unsigned int pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) int (*set_data)(struct mv88e6xxx_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /* get/set GPIO direction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) int (*get_dir)(struct mv88e6xxx_chip *chip, unsigned int pin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) int (*set_dir)(struct mv88e6xxx_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) bool input);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) /* get/set GPIO pin control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) int (*get_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int *func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) int (*set_pctl)(struct mv88e6xxx_chip *chip, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) int func);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct mv88e6xxx_avb_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) /* Access port-scoped Precision Time Protocol registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) int (*port_ptp_read)(struct mv88e6xxx_chip *chip, int port, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) u16 *data, int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) int (*port_ptp_write)(struct mv88e6xxx_chip *chip, int port, int addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) /* Access global Precision Time Protocol registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) int (*ptp_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int (*ptp_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* Access global Time Application Interface registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) int (*tai_read)(struct mv88e6xxx_chip *chip, int addr, u16 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) int (*tai_write)(struct mv88e6xxx_chip *chip, int addr, u16 data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mv88e6xxx_ptp_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u64 (*clock_read)(const struct cyclecounter *cc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) int (*ptp_enable)(struct ptp_clock_info *ptp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct ptp_clock_request *rq, int on);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int (*ptp_verify)(struct ptp_clock_info *ptp, unsigned int pin,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) enum ptp_pin_function func, unsigned int chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) void (*event_work)(struct work_struct *ugly);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) int (*port_enable)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int (*port_disable)(struct mv88e6xxx_chip *chip, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) int (*global_enable)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int (*global_disable)(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) int n_ext_ts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) int arr0_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) int arr1_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) int dep_sts_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) u32 rx_filters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) u32 cc_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) u32 cc_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) u32 cc_mult_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) u32 cc_mult_dem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) #define STATS_TYPE_PORT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define STATS_TYPE_BANK0 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) #define STATS_TYPE_BANK1 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct mv88e6xxx_hw_stat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) char string[ETH_GSTRING_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) int reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) return chip->info->pvt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return chip->info->num_databases;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static inline unsigned int mv88e6xxx_num_macs(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) return chip->info->num_macs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return chip->info->num_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static inline u16 mv88e6xxx_port_mask(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) return GENMASK((s32)mv88e6xxx_num_ports(chip) - 1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return chip->info->num_gpio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static inline bool mv88e6xxx_is_invalid_port(struct mv88e6xxx_chip *chip, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return (chip->info->invalid_port_mask & BIT(port)) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) u16 mask, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) int bit, int val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) static inline void mv88e6xxx_reg_lock(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mutex_lock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) static inline void mv88e6xxx_reg_unlock(struct mv88e6xxx_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) mutex_unlock(&chip->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) #endif /* _MV88E6XXX_CHIP_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags