^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/net/dsa/mv88e6060.h - Marvell 88e6060 switch chip support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2015 Neil Armstrong
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Based on mv88e6xxx.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2008 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __MV88E6060_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __MV88E6060_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define MV88E6060_PORTS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define REG_PORT(p) (0x8 + (p))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PORT_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PORT_STATUS_PAUSE_EN BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PORT_STATUS_MY_PAUSE BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PORT_STATUS_FC (PORT_STATUS_MY_PAUSE | PORT_STATUS_PAUSE_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PORT_STATUS_RESOLVED BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PORT_STATUS_LINK BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PORT_STATUS_PORTMODE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PORT_STATUS_PHYMODE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PORT_STATUS_DUPLEX BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PORT_STATUS_SPEED BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PORT_SWITCH_ID 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PORT_SWITCH_ID_6060 0x0600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PORT_SWITCH_ID_6060_MASK 0xfff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PORT_SWITCH_ID_6060_R1 0x0601
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PORT_SWITCH_ID_6060_R2 0x0602
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PORT_CONTROL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PORT_CONTROL_FORCE_FLOW_CTRL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PORT_CONTROL_TRAILER BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PORT_CONTROL_HEADER BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PORT_CONTROL_INGRESS_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PORT_CONTROL_VLAN_TUNNEL BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PORT_CONTROL_STATE_MASK 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PORT_CONTROL_STATE_DISABLED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PORT_CONTROL_STATE_BLOCKING 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PORT_CONTROL_STATE_LEARNING 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PORT_CONTROL_STATE_FORWARDING 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PORT_VLAN_MAP 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PORT_VLAN_MAP_DBNUM_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PORT_VLAN_MAP_TABLE_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PORT_ASSOC_VECTOR 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PORT_ASSOC_VECTOR_MONITOR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PORT_ASSOC_VECTOR_PAV_MASK 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PORT_RX_CNTR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PORT_TX_CNTR 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define REG_GLOBAL 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define GLOBAL_STATUS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GLOBAL_STATUS_SW_MODE_MASK (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define GLOBAL_STATUS_SW_MODE_0 (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GLOBAL_STATUS_SW_MODE_1 (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GLOBAL_STATUS_SW_MODE_2 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GLOBAL_STATUS_SW_MODE_3 (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GLOBAL_STATUS_INIT_READY BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GLOBAL_STATUS_ATU_FULL BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GLOBAL_STATUS_ATU_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GLOBAL_STATUS_PHY_INT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GLOBAL_STATUS_EEINT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GLOBAL_MAC_01 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GLOBAL_MAC_01_DIFF_ADDR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define GLOBAL_MAC_23 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define GLOBAL_MAC_45 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define GLOBAL_CONTROL 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define GLOBAL_CONTROL_DISCARD_EXCESS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define GLOBAL_CONTROL_MAX_FRAME_1536 BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define GLOBAL_CONTROL_RELOAD_EEPROM BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define GLOBAL_CONTROL_CTRMODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define GLOBAL_CONTROL_ATU_FULL_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define GLOBAL_CONTROL_ATU_DONE_EN BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define GLOBAL_CONTROL_PHYINT_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define GLOBAL_CONTROL_EEPROM_DONE_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define GLOBAL_ATU_CONTROL 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GLOBAL_ATU_CONTROL_SWRESET BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GLOBAL_ATU_CONTROL_LEARNDIS BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GLOBAL_ATU_CONTROL_ATUSIZE_256 (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GLOBAL_ATU_CONTROL_ATUSIZE_512 (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GLOBAL_ATU_CONTROL_ATUSIZE_1024 (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GLOBAL_ATU_CONTROL_ATE_AGE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GLOBAL_ATU_CONTROL_ATE_AGE_MASK (0xff << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GLOBAL_ATU_CONTROL_ATE_AGE_5MIN (0x13 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GLOBAL_ATU_OP 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GLOBAL_ATU_OP_BUSY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GLOBAL_ATU_OP_NOP (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GLOBAL_ATU_OP_FLUSH_ALL ((1 << 12) | GLOBAL_ATU_OP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GLOBAL_ATU_OP_FLUSH_UNLOCKED ((2 << 12) | GLOBAL_ATU_OP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define GLOBAL_ATU_OP_LOAD_DB ((3 << 12) | GLOBAL_ATU_OP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define GLOBAL_ATU_OP_GET_NEXT_DB ((4 << 12) | GLOBAL_ATU_OP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define GLOBAL_ATU_OP_FLUSH_DB ((5 << 12) | GLOBAL_ATU_OP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define GLOBAL_ATU_OP_FLUSH_UNLOCKED_DB ((6 << 12) | GLOBAL_ATU_OP_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define GLOBAL_ATU_DATA 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define GLOBAL_ATU_DATA_PORT_VECTOR_MASK 0x3f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define GLOBAL_ATU_DATA_STATE_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define GLOBAL_ATU_DATA_STATE_UNUSED 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define GLOBAL_ATU_DATA_STATE_UC_STATIC 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GLOBAL_ATU_DATA_STATE_UC_LOCKED 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GLOBAL_ATU_DATA_STATE_MC_STATIC 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GLOBAL_ATU_DATA_STATE_MC_LOCKED 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GLOBAL_ATU_MAC_01 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GLOBAL_ATU_MAC_23 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GLOBAL_ATU_MAC_45 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct mv88e6060_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* MDIO bus and address on bus to use. When in single chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * mode, address is 0, and the switch uses multiple addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * on the bus. When in multi-chip mode, the switch uses a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * single address which contains two registers used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) * indirect access to more registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) int sw_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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