^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * net/dsa/mv88e6060.c - Driver for Marvell 88e6060 switch chips
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2008-2009 Marvell Semiconductor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/jiffies.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "mv88e6060.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) static int reg_read(struct mv88e6060_priv *priv, int addr, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) return mdiobus_read_nested(priv->bus, priv->sw_addr + addr, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) static int reg_write(struct mv88e6060_priv *priv, int addr, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) return mdiobus_write_nested(priv->bus, priv->sw_addr + addr, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static const char *mv88e6060_get_name(struct mii_bus *bus, int sw_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ret = mdiobus_read(bus, sw_addr + REG_PORT(0), PORT_SWITCH_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) if (ret >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if (ret == PORT_SWITCH_ID_6060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) return "Marvell 88E6060 (A0)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) if (ret == PORT_SWITCH_ID_6060_R1 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ret == PORT_SWITCH_ID_6060_R2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) return "Marvell 88E6060 (B0)";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if ((ret & PORT_SWITCH_ID_6060_MASK) == PORT_SWITCH_ID_6060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return "Marvell 88E6060";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static enum dsa_tag_protocol mv88e6060_get_tag_protocol(struct dsa_switch *ds,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) enum dsa_tag_protocol m)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) return DSA_TAG_PROTO_TRAILER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static int mv88e6060_switch_reset(struct mv88e6060_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Set all ports to the disabled state. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) for (i = 0; i < MV88E6060_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ret = reg_read(priv, REG_PORT(i), PORT_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ret = reg_write(priv, REG_PORT(i), PORT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) ret & ~PORT_CONTROL_STATE_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Wait for transmit queues to drain. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) usleep_range(2000, 4000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Reset the switch. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ret = reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) GLOBAL_ATU_CONTROL_SWRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) GLOBAL_ATU_CONTROL_LEARNDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* Wait up to one second for reset to complete. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) timeout = jiffies + 1 * HZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) while (time_before(jiffies, timeout)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = reg_read(priv, REG_GLOBAL, GLOBAL_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret & GLOBAL_STATUS_INIT_READY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (time_after(jiffies, timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int mv88e6060_setup_global(struct mv88e6060_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* Disable discarding of frames with excessive collisions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * set the maximum frame size to 1536 bytes, and mask all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * interrupt sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ret = reg_write(priv, REG_GLOBAL, GLOBAL_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) GLOBAL_CONTROL_MAX_FRAME_1536);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Disable automatic address learning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return reg_write(priv, REG_GLOBAL, GLOBAL_ATU_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) GLOBAL_ATU_CONTROL_LEARNDIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static int mv88e6060_setup_port(struct mv88e6060_priv *priv, int p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) int addr = REG_PORT(p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Do not force flow control, disable Ingress and Egress
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Header tagging, disable VLAN tunneling, and set the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * state to Forwarding. Additionally, if this is the CPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * port, enable Ingress and Egress Trailer tagging mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) ret = reg_write(priv, addr, PORT_CONTROL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dsa_is_cpu_port(priv->ds, p) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PORT_CONTROL_TRAILER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PORT_CONTROL_INGRESS_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PORT_CONTROL_STATE_FORWARDING :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PORT_CONTROL_STATE_FORWARDING);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Port based VLAN map: give each port its own address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * database, allow the CPU port to talk to each of the 'real'
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * ports, and allow each of the 'real' ports to only talk to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * the CPU port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) ret = reg_write(priv, addr, PORT_VLAN_MAP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) ((p & 0xf) << PORT_VLAN_MAP_DBNUM_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (dsa_is_cpu_port(priv->ds, p) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dsa_user_ports(priv->ds) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) BIT(dsa_to_port(priv->ds, p)->cpu_dp->index)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Port Association Vector: when learning source addresses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * of packets, add the address to the address database using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * a port bitmap that has only the bit for this port set and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * the other bits clear.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) return reg_write(priv, addr, PORT_ASSOC_VECTOR, BIT(p));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static int mv88e6060_setup_addr(struct mv88e6060_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u8 addr[ETH_ALEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u16 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) eth_random_addr(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val = addr[0] << 8 | addr[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* The multicast bit is always transmitted as a zero, so the switch uses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * bit 8 for "DiffAddr", where 0 means all ports transmit the same SA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) val &= 0xfeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_01, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) ret = reg_write(priv, REG_GLOBAL, GLOBAL_MAC_23,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) (addr[2] << 8) | addr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return reg_write(priv, REG_GLOBAL, GLOBAL_MAC_45,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) (addr[4] << 8) | addr[5]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static int mv88e6060_setup(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) struct mv88e6060_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) priv->ds = ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ret = mv88e6060_switch_reset(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* @@@ initialise atu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) ret = mv88e6060_setup_global(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) ret = mv88e6060_setup_addr(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) for (i = 0; i < MV88E6060_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = mv88e6060_setup_port(priv, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static int mv88e6060_port_to_phy_addr(int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (port >= 0 && port < MV88E6060_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) return port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static int mv88e6060_phy_read(struct dsa_switch *ds, int port, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct mv88e6060_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) addr = mv88e6060_port_to_phy_addr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) if (addr == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return reg_read(priv, addr, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) mv88e6060_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct mv88e6060_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) addr = mv88e6060_port_to_phy_addr(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) if (addr == -1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) return 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return reg_write(priv, addr, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static const struct dsa_switch_ops mv88e6060_switch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) .get_tag_protocol = mv88e6060_get_tag_protocol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) .setup = mv88e6060_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) .phy_read = mv88e6060_phy_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .phy_write = mv88e6060_phy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int mv88e6060_probe(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct device *dev = &mdiodev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) struct mv88e6060_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) priv->bus = mdiodev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) priv->sw_addr = mdiodev->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) name = mv88e6060_get_name(priv->bus, priv->sw_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) if (!name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) dev_info(dev, "switch %s detected\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) if (!ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) ds->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ds->num_ports = MV88E6060_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) ds->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) ds->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) ds->ops = &mv88e6060_switch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) dev_set_drvdata(dev, ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) return dsa_register_switch(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static void mv88e6060_remove(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dsa_unregister_switch(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static const struct of_device_id mv88e6060_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .compatible = "marvell,mv88e6060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) static struct mdio_driver mv88e6060_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .probe = mv88e6060_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .remove = mv88e6060_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .mdiodrv.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .name = "mv88e6060",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .of_match_table = mv88e6060_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) mdio_module_driver(mv88e6060_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) MODULE_DESCRIPTION("Driver for Marvell 88E6060 ethernet switch chip");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) MODULE_ALIAS("platform:mv88e6060");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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