^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __MT7530_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __MT7530_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define MT7530_NUM_PORTS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define MT7530_CPU_PORT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MT7530_NUM_FDB_RECORDS 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MT7530_ALL_MEMBERS 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) enum mt753x_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) ID_MT7530 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) ID_MT7621 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) ID_MT7531 = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define NUM_TRGMII_CTRL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TRGMII_BASE(x) (0x10000 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Registers to ethsys access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ETHSYS_CLKCFG0 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SYSC_REG_RSTCTRL 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define RESET_MCM BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Registers to mac forward control for unknown frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MT7530_MFC 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define BC_FFP(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define UNM_FFP(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define UNM_FFP_MASK UNM_FFP(~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define UNU_FFP(x) (((x) & 0xff) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define UNU_FFP_MASK UNU_FFP(~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CPU_EN BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CPU_PORT(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CPU_MASK (0xf << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MIRROR_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MIRROR_PORT(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MIRROR_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Registers for CPU forward control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MT7531_CFC 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MT7531_MIRROR_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MT7531_MIRROR_MASK (MIRROR_MASK << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MT7531_CPU_PMAP_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MT7531_CFC : MT7530_MFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MT7531_MIRROR_EN : MIRROR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MT7531_MIRROR_MASK : MIRROR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* Registers for BPDU and PAE frame control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MT753X_BPC 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) enum mt753x_bpdu_port_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MT753X_BPDU_FOLLOW_MFC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MT753X_BPDU_CPU_EXCLUDE = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MT753X_BPDU_CPU_INCLUDE = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) MT753X_BPDU_CPU_ONLY = 6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) MT753X_BPDU_DROP = 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* Registers for address table access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MT7530_ATA1 0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define STATIC_EMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define STATIC_ENT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MT7530_ATA2 0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /* Register for address table write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define MT7530_ATWD 0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Register for address table control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MT7530_ATC 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ATC_HASH (((x) & 0xfff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ATC_BUSY BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ATC_SRCH_END BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ATC_SRCH_HIT BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ATC_INVALID BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ATC_MAT(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ATC_MAT_MACTAB ATC_MAT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum mt7530_fdb_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) MT7530_FDB_READ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) MT7530_FDB_WRITE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) MT7530_FDB_FLUSH = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) MT7530_FDB_START = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) MT7530_FDB_NEXT = 5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* Registers for table search read address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define MT7530_TSRA1 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MAC_BYTE_0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MAC_BYTE_1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define MAC_BYTE_2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define MAC_BYTE_3 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define MAC_BYTE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define MT7530_TSRA2 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define MAC_BYTE_4 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define MAC_BYTE_5 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CVID 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CVID_MASK 0xfff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MT7530_ATRD 0x8C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define AGE_TIMER 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define AGE_TIMER_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PORT_MAP 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PORT_MAP_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ENT_STATUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ENT_STATUS_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* Register for vlan table control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define MT7530_VTCR 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VTCR_BUSY BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VTCR_INVALID BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VTCR_FUNC(x) (((x) & 0xf) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VTCR_VID ((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum mt7530_vlan_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Read/Write the specified VID entry from VAWD register based
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * on VID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) MT7530_VTCR_RD_VID = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) MT7530_VTCR_WR_VID = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Register for setup vlan and acl write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MT7530_VAWD1 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PORT_STAG BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Independent VLAN Learning */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IVL_MAC BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Per VLAN Egress Tag Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VTAG_EN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* VLAN Member Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PORT_MEM(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* VLAN Entry Valid */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VLAN_VALID BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define PORT_MEM_SHFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PORT_MEM_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define MT7530_VAWD2 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Egress Tag Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) enum mt7530_vlan_egress_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) MT7530_VLAN_EGRESS_UNTAG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) MT7530_VLAN_EGRESS_TAG = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) MT7530_VLAN_EGRESS_STACK = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Register for port STP state control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define FID_PST(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define FID_PST_MASK FID_PST(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum mt7530_stp_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) MT7530_STP_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) MT7530_STP_BLOCKING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) MT7530_STP_LISTENING = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) MT7530_STP_LEARNING = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) MT7530_STP_FORWARDING = 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* Register for port control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PORT_TX_MIR BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PORT_RX_MIR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define PORT_VLAN(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum mt7530_port_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* Fallback Mode: Forward received frames with ingress ports that do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * not belong to the VLAN member. Frames whose VID is not listed on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * the VLAN table are forwarded by the PCR_MATRIX members.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* Security Mode: Discard any frame due to ingress membership
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * violation or VID missed on the VLAN table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PCR_MATRIX(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PORT_PRI(x) (((x) & 0x7) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EG_TAG(x) (((x) & 0x3) << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PCR_MATRIX_MASK PCR_MATRIX(0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PCR_MATRIX_CLR PCR_MATRIX(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PCR_PORT_VLAN_MASK PORT_VLAN(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Register for port security control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SA_DIS BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Register for port vlan control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define PORT_SPEC_TAG BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PVC_EG_TAG(x) (((x) & 0x7) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define PVC_EG_TAG_MASK PVC_EG_TAG(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define VLAN_ATTR(x) (((x) & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define VLAN_ATTR_MASK VLAN_ATTR(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) enum mt7530_vlan_port_eg_tag {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MT7530_VLAN_EG_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) MT7530_VLAN_EG_CONSISTENT = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) enum mt7530_vlan_port_attr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) MT7530_VLAN_USER = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) MT7530_VLAN_TRANSPARENT = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define STAG_VPID (((x) & 0xffff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* Register for port port-and-protocol based vlan 1 control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define G0_PORT_VID(x) (((x) & 0xfff) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define G0_PORT_VID_MASK G0_PORT_VID(0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define G0_PORT_VID_DEF G0_PORT_VID(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Register for port MAC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define PMCR_EXT_PHY BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define PMCR_MAC_MODE BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PMCR_FORCE_MODE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define PMCR_TX_EN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PMCR_RX_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define PMCR_BACKOFF_EN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define PMCR_BACKPR_EN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PMCR_TX_FC_EN BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define PMCR_RX_FC_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define PMCR_FORCE_SPEED_1000 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define PMCR_FORCE_SPEED_100 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PMCR_FORCE_FDX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define PMCR_FORCE_LNK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) PMCR_FORCE_SPEED_1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define MT7531_FORCE_LNK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define MT7531_FORCE_SPD BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define MT7531_FORCE_DPX BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define MT7531_FORCE_RX_FC BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define MT7531_FORCE_TX_FC BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MT7531_FORCE_SPD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) MT7531_FORCE_DPX | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) MT7531_FORCE_RX_FC | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) MT7531_FORCE_TX_FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) MT7531_FORCE_MODE : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) PMCR_FORCE_MODE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) PMCR_FORCE_FDX | PMCR_FORCE_LNK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) PMCR_TX_EN | PMCR_RX_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) PMCR_FORCE_SPEED_1000 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) PMCR_FORCE_FDX | PMCR_FORCE_LNK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define PMSR_EEE1G BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define PMSR_EEE100M BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define PMSR_RX_FC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define PMSR_TX_FC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define PMSR_SPEED_1000 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PMSR_SPEED_100 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PMSR_SPEED_10 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PMSR_DPX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define PMSR_LINK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Register for port debug count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define MT7531_DIS_CLR BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Register for MIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define MT7530_MIB_CCR 0x4fe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CCR_MIB_ENABLE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CCR_RX_OCT_CNT_GOOD BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CCR_RX_OCT_CNT_BAD BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CCR_TX_OCT_CNT_GOOD BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CCR_TX_OCT_CNT_BAD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) CCR_RX_OCT_CNT_BAD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) CCR_TX_OCT_CNT_GOOD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) CCR_TX_OCT_CNT_BAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) CCR_RX_OCT_CNT_GOOD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) CCR_RX_OCT_CNT_BAD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) CCR_TX_OCT_CNT_GOOD | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) CCR_TX_OCT_CNT_BAD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* MT7531 SGMII register group */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define MT7531_SGMII_REG_BASE 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ((p) - 5) * 0x1000 + (r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Register forSGMII PCS_CONTROL_1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define MT7531_SGMII_LINK_STATUS BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define MT7531_SGMII_AN_ENABLE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define MT7531_SGMII_AN_RESTART BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* Register for SGMII PCS_SPPED_ABILITY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define MT7531_SGMII_TX_CONFIG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* Register for SGMII_MODE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define MT7531_SGMII_FORCE_DUPLEX BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define MT7531_SGMII_FORCE_SPEED_100 BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define MT7531_SGMII_FORCE_SPEED_10 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) enum mt7531_sgmii_force_duplex {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) MT7531_SGMII_FORCE_FULL_DUPLEX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) /* Fields of QPHY_PWR_STATE_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define MT7531_SGMII_PHYA_PWD BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) /* Values of SGMII SPEED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define MT7531_RG_TPHY_SPEED_1_25G 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define MT7531_RG_TPHY_SPEED_3_125G BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* Register for system reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define MT7530_SYS_CTRL 0x7000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define SYS_CTRL_PHY_RST BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define SYS_CTRL_SW_RST BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define SYS_CTRL_REG_RST BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) /* Register for PHY Indirect Access Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define MT7531_PHY_IAC 0x701C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define MT7531_PHY_ACS_ST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define MT7531_MDIO_CMD_MASK (0x3 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define MT7531_MDIO_ST_MASK (0x3 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define MT7531_MDIO_RW_DATA_MASK (0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum mt7531_phy_iac_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) MT7531_MDIO_ADDR = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) MT7531_MDIO_WRITE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) MT7531_MDIO_READ = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) MT7531_MDIO_READ_CL45 = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* MDIO_ST: MDIO start field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) enum mt7531_mdio_st {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) MT7531_MDIO_ST_CL45 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) MT7531_MDIO_ST_CL22 = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) MT7531_MDIO_CMD(MT7531_MDIO_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) MT7531_MDIO_CMD(MT7531_MDIO_READ))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* Register for RGMII clock phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define MT7531_CLKGEN_CTRL 0x7500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CLK_SKEW_OUT_MASK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CLK_SKEW_IN(x) (((x) & 0x3) << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CLK_SKEW_IN_MASK GENMASK(7, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define RXCLK_NO_DELAY BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TXCLK_NO_REVERSE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define GP_MODE(x) (((x) & 0x3) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define GP_MODE_MASK GENMASK(2, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define GP_CLK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) enum mt7531_gp_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) MT7531_GP_MODE_RGMII = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) MT7531_GP_MODE_MII = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MT7531_GP_MODE_REV_MII = 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) enum mt7531_clk_skew {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) MT7531_CLK_SKEW_NO_CHG = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) MT7531_CLK_SKEW_DLY_100PPS = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) MT7531_CLK_SKEW_DLY_200PPS = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) MT7531_CLK_SKEW_REVERSE = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Register for hw trap status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define MT7530_HWTRAP 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define HWTRAP_XTAL_40MHZ (BIT(10))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define HWTRAP_XTAL_20MHZ (BIT(9))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define MT7531_HWTRAP 0x7800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define HWTRAP_XTAL_FSEL_MASK BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define HWTRAP_XTAL_FSEL_25MHZ BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define HWTRAP_XTAL_FSEL_40MHZ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) /* Unique fields of (M)HWSTRAP for MT7531 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define XTAL_FSEL_S 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define XTAL_FSEL_M BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define PHY_EN BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CHG_STRAP BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Register for hw trap modification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define MT7530_MHWTRAP 0x7804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define MHWTRAP_PHY0_SEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define MHWTRAP_MANUAL BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define MHWTRAP_P5_MAC_SEL BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define MHWTRAP_P6_DIS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define MHWTRAP_P5_RGMII_MODE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define MHWTRAP_P5_DIS BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define MHWTRAP_PHY_ACCESS BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Register for TOP signal control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define MT7530_TOP_SIG_CTRL 0x7808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define MT7531_TOP_SIG_SR 0x780c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define PAD_DUAL_SGMII_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define PAD_MCM_SMI_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define MT7530_IO_DRV_CR 0x7810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define P5_IO_CLK_DRV(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define MT7531_CHIP_REV 0x781C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define MT7531_PLLGP_EN 0x7820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define EN_COREPLL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SW_CLKSW BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SW_PLLGP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define MT7530_P6ECR 0x7830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define P6_INTF_MODE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define P6_INTF_MODE(x) ((x) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define MT7531_PLLGP_CR0 0x78a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define RG_COREPLL_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define RG_COREPLL_POSDIV_S 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define RG_COREPLL_POSDIV_M 0x3800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define RG_COREPLL_SDM_PCW_S 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define RG_COREPLL_SDM_PCW_M 0x3ffffe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define RG_COREPLL_SDM_PCW_CHG BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* Registers for RGMII and SGMII PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define MT7531_ANA_PLLGP_CR2 0x78b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define MT7531_ANA_PLLGP_CR5 0x78bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /* Registers for TRGMII on the both side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define MT7530_TRGMII_RCK_CTRL 0x7a00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define RX_RST BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define RXC_DQSISEL BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define DQSI1_TAP_MASK (0x7f << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define DQSI0_TAP_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define DQSI1_TAP(x) (((x) & 0x7f) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define DQSI0_TAP(x) ((x) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define MT7530_TRGMII_RCK_RTT 0x7a04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define DQS1_GATE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define DQS0_GATE BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define BSLIP_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define EDGE_CHK BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define RD_TAP_MASK 0x7f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define RD_TAP(x) ((x) & 0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define MT7530_TRGMII_TXCTRL 0x7a40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define TRAIN_TXEN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define TXC_INV BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define TX_RST BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define TD_DM_DRVP(x) ((x) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define TD_DM_DRVN(x) (((x) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define MT7530_TRGMII_TCK_CTRL 0x7a78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define TCK_TAP(x) (((x) & 0xf) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define MT7530_P5RGMIIRXCR 0x7b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define CSR_RGMII_EDGE_ALIGN BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define MT7530_P5RGMIITXCR 0x7b04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /* Registers for GPIO mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define MT7531_GPIO_MODE0 0x7c0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define MT7531_GPIO0_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define MT7531_GPIO0_INTERRUPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define MT7531_GPIO_MODE1 0x7c10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define MT7531_EXT_P_MDC_11 (2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define MT7531_EXT_P_MDIO_12 (2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define MT7530_CREV 0x7ffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define CHIP_NAME_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define MT7530_ID 0x7530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define MT7531_CREV 0x781C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define CHIP_REV_M 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define MT7531_ID 0x7531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* Registers for core PLL access through mmd indirect */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define CORE_PLL_GROUP2 0x401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define RG_SYSPLL_EN_NORMAL BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define RG_SYSPLL_VODEN BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define RG_SYSPLL_LF BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define RG_SYSPLL_LVROD_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define RG_SYSPLL_FBKSEL BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define RT_SYSPLL_EN_AFE_OLT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define CORE_PLL_GROUP4 0x403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define RG_SYSPLL_DDSFBK_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define RG_SYSPLL_BIAS_EN BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define RG_SYSPLL_BIAS_LPF_EN BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define MT7531_PHY_PLL_OFF BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define MT7531_PHY_PLL_BYPASS_MODE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define MT753X_CTRL_PHY_ADDR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define CORE_PLL_GROUP5 0x404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define CORE_PLL_GROUP6 0x405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define CORE_PLL_GROUP7 0x406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define RG_LCDDS_PWDB BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define RG_LCDDS_ISO_EN BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define RG_LCCDS_C(x) (((x) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define RG_LCDDS_PCW_NCPO_CHG BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define CORE_PLL_GROUP10 0x409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define CORE_PLL_GROUP11 0x40a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define CORE_GSWPLL_GRP1 0x40d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define RG_GSWPLL_EN_PRE BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define RG_GSWPLL_FBKSEL BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define RG_GSWPLL_BP BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define RG_GSWPLL_BR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define CORE_GSWPLL_GRP2 0x40e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define CORE_TRGMII_GSW_CLK_CG 0x410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define REG_GSWCK_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define REG_TRGMIICK_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define MIB_DESC(_s, _o, _n) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) .size = (_s), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) .offset = (_o), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) .name = (_n), \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct mt7530_mib_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct mt7530_fdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) u8 port_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u8 aging;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u8 mac[6];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) bool noarp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /* struct mt7530_port - This is the main data structure for holding the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) * of the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * @enable: The status used for show port is enabled or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) * @pm: The matrix used to show all connections with the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * @pvid: The VLAN specified is to be considered a PVID at ingress. Any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * untagged frames will be assigned to the related VLAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) * @vlan_filtering: The flags indicating whether the port that can recognize
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) * VLAN-tagged frames.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct mt7530_port {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) bool enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) u32 pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u16 pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) /* Port 5 interface select definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) enum p5_interface_select {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) P5_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) P5_INTF_SEL_PHY_P0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) P5_INTF_SEL_PHY_P4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) P5_INTF_SEL_GMAC5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) P5_INTF_SEL_GMAC5_SGMII,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) static const char *p5_intf_modes(unsigned int p5_interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) switch (p5_interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) case P5_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return "DISABLED";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) case P5_INTF_SEL_PHY_P0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) return "PHY P0";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) case P5_INTF_SEL_PHY_P4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) return "PHY P4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) case P5_INTF_SEL_GMAC5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return "GMAC5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) case P5_INTF_SEL_GMAC5_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) return "GMAC5_SGMII";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) return "unknown";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /* struct mt753x_info - This is the main data structure for holding the specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * part for each supported device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) * @sw_setup: Holding the handler to a device initialization
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) * @phy_read: Holding the way reading PHY port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) * @phy_write: Holding the way writing PHY port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) * @pad_setup: Holding the way setting up the bus pad for a certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * MAC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) * @phy_mode_supported: Check if the PHY type is being supported on a certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) * port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) * @mac_port_validate: Holding the way to set addition validate type for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) * certan MAC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) * @mac_port_get_state: Holding the way getting the MAC/PCS state for a certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) * MAC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) * @mac_port_config: Holding the way setting up the PHY attribute to a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) * certain MAC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) * @mac_pcs_an_restart Holding the way restarting PCS autonegotiation for a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) * certain MAC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) * @mac_pcs_link_up: Holding the way setting up the PHY attribute to the pcs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) * of the certain MAC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct mt753x_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) enum mt753x_id id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) int (*sw_setup)(struct dsa_switch *ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) int (*phy_read)(struct dsa_switch *ds, int port, int regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) int (*phy_write)(struct dsa_switch *ds, int port, int regnum, u16 val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) int (*cpu_port_config)(struct dsa_switch *ds, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) bool (*phy_mode_supported)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) const struct phylink_link_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) void (*mac_port_validate)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) unsigned long *supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) int (*mac_port_get_state)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct phylink_link_state *state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) int (*mac_port_config)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) phy_interface_t interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) void (*mac_pcs_an_restart)(struct dsa_switch *ds, int port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) void (*mac_pcs_link_up)(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) unsigned int mode, phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int speed, int duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) /* struct mt7530_priv - This is the main data structure for holding the state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) * of the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) * @dev: The device pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) * @ds: The pointer to the dsa core structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) * @bus: The bus used for the device and built-in PHY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) * @rstc: The pointer to reset control used by MCM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) * @core_pwr: The power supplied into the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) * @io_pwr: The power supplied into the I/O
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) * @reset: The descriptor for GPIO line tied to its reset pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) * @mcm: Flag for distinguishing if standalone IC or module
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) * coupling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) * @ports: Holding the state among ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) * @reg_mutex: The lock for protecting among process accessing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) * registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) * @p6_interface Holding the current port 6 interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * @p5_intf_sel: Holding the current port 5 interface select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mt7530_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) struct dsa_switch *ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) struct mii_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) struct reset_control *rstc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct regulator *core_pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct regulator *io_pwr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) struct gpio_desc *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) const struct mt753x_info *info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) bool mcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) phy_interface_t p6_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) phy_interface_t p5_interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) unsigned int p5_intf_sel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) u8 mirror_rx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) u8 mirror_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct mt7530_port ports[MT7530_NUM_PORTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /* protect among processes for registers access*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct mutex reg_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) struct mt7530_hw_vlan_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) int port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) u8 old_members;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) bool untagged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) int port, bool untagged)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) e->port = port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) e->untagged = untagged;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct mt7530_hw_vlan_entry *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct mt7530_hw_stats {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) const char *string;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) u16 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u8 sizeof_stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) struct mt7530_dummy_poll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) struct mt7530_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) struct mt7530_priv *priv, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) p->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) p->reg = reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) #endif /* __MT7530_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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