^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Mediatek MT7530 DSA Switch driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/etherdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/if_bridge.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/netdevice.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of_mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/of_net.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/phylink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/gpio/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <net/dsa.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include "mt7530.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* String, offset, and register size in bytes if different from 4 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static const struct mt7530_mib_desc mt7530_mib[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) MIB_DESC(1, 0x00, "TxDrop"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) MIB_DESC(1, 0x04, "TxCrcErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MIB_DESC(1, 0x08, "TxUnicast"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) MIB_DESC(1, 0x0c, "TxMulticast"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) MIB_DESC(1, 0x10, "TxBroadcast"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) MIB_DESC(1, 0x14, "TxCollision"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) MIB_DESC(1, 0x18, "TxSingleCollision"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) MIB_DESC(1, 0x1c, "TxMultipleCollision"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) MIB_DESC(1, 0x20, "TxDeferred"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) MIB_DESC(1, 0x24, "TxLateCollision"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) MIB_DESC(1, 0x28, "TxExcessiveCollistion"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) MIB_DESC(1, 0x2c, "TxPause"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) MIB_DESC(1, 0x30, "TxPktSz64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MIB_DESC(1, 0x34, "TxPktSz65To127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) MIB_DESC(1, 0x38, "TxPktSz128To255"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) MIB_DESC(1, 0x3c, "TxPktSz256To511"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MIB_DESC(1, 0x40, "TxPktSz512To1023"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) MIB_DESC(1, 0x44, "Tx1024ToMax"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) MIB_DESC(2, 0x48, "TxBytes"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) MIB_DESC(1, 0x60, "RxDrop"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) MIB_DESC(1, 0x64, "RxFiltering"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) MIB_DESC(1, 0x68, "RxUnicast"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) MIB_DESC(1, 0x6c, "RxMulticast"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) MIB_DESC(1, 0x70, "RxBroadcast"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) MIB_DESC(1, 0x74, "RxAlignErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) MIB_DESC(1, 0x78, "RxCrcErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) MIB_DESC(1, 0x7c, "RxUnderSizeErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) MIB_DESC(1, 0x80, "RxFragErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) MIB_DESC(1, 0x84, "RxOverSzErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) MIB_DESC(1, 0x88, "RxJabberErr"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) MIB_DESC(1, 0x8c, "RxPause"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) MIB_DESC(1, 0x90, "RxPktSz64"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) MIB_DESC(1, 0x94, "RxPktSz65To127"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) MIB_DESC(1, 0x98, "RxPktSz128To255"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) MIB_DESC(1, 0x9c, "RxPktSz256To511"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) MIB_DESC(1, 0xa0, "RxPktSz512To1023"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) MIB_DESC(2, 0xa8, "RxBytes"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) MIB_DESC(1, 0xb0, "RxCtrlDrop"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) MIB_DESC(1, 0xb4, "RxIngressDrop"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) MIB_DESC(1, 0xb8, "RxArlDrop"),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int value, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Write the desired MMD Devad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Write the desired MMD register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Select the Function : DATA with no post increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Read the content of the MMD's selected register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) value = bus->read(bus, 0, MII_MMD_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) dev_err(&bus->dev, "failed to read mmd register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) core_write_mmd_indirect(struct mt7530_priv *priv, int prtad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int devad, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Write the desired MMD Devad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ret = bus->write(bus, 0, MII_MMD_CTRL, devad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Write the desired MMD register address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) ret = bus->write(bus, 0, MII_MMD_DATA, prtad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Select the Function : DATA with no post increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Write the data into MMD's selected register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = bus->write(bus, 0, MII_MMD_DATA, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) dev_err(&bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) "failed to write mmd register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) core_write(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) core_set(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) core_rmw(priv, reg, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) core_clear(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) core_rmw(priv, reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u16 page, r, lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) page = (reg >> 6) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) r = (reg >> 2) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) lo = val & 0xffff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) hi = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* MT7530 uses 31 as the pseudo port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = bus->write(bus, 0x1f, 0x1f, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) ret = bus->write(bus, 0x1f, r, lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ret = bus->write(bus, 0x1f, 0x10, hi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_err(&bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "failed to write mt7530 register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) mt7530_mii_read(struct mt7530_priv *priv, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u16 page, r, lo, hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) page = (reg >> 6) & 0x3ff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) r = (reg >> 2) & 0xf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* MT7530 uses 31 as the pseudo port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ret = bus->write(bus, 0x1f, 0x1f, page);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dev_err(&bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "failed to read mt7530 register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) lo = bus->read(bus, 0x1f, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) hi = bus->read(bus, 0x1f, 0x10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) return (hi << 16) | (lo & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) mt7530_mii_write(priv, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) _mt7530_unlocked_read(struct mt7530_dummy_poll *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return mt7530_mii_read(p->priv, p->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) _mt7530_read(struct mt7530_dummy_poll *p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct mii_bus *bus = p->priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) val = mt7530_mii_read(p->priv, p->reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static u32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) mt7530_read(struct mt7530_priv *priv, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) INIT_MT7530_DUMMY_POLL(&p, priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return _mt7530_read(&p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) mt7530_rmw(struct mt7530_priv *priv, u32 reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) u32 mask, u32 set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) val = mt7530_mii_read(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) val |= set;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) mt7530_mii_write(priv, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) mt7530_rmw(priv, reg, 0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) mt7530_rmw(priv, reg, val, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* Set the command operating upon the MAC address entries */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) val = ATC_BUSY | ATC_MAT(0) | cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mt7530_write(priv, MT7530_ATC, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) ret = readx_poll_timeout(_mt7530_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) !(val & ATC_BUSY), 20, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(priv->dev, "reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* Additional sanity for read command if the specified
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * entry is invalid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) val = mt7530_read(priv, MT7530_ATC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) if (rsp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) *rsp = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u32 reg[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) /* Read from ARL table into an array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) for (i = 0; i < 3; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) __func__, __LINE__, i, reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) fdb->vid = (reg[1] >> CVID) & CVID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) mt7530_fdb_write(struct mt7530_priv *priv, u16 vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) u8 port_mask, const u8 *mac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) u8 aging, u8 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) u32 reg[3] = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) reg[1] |= vid & CVID_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* STATIC_ENT indicate that entry is static wouldn't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) * be aged out and STATIC_EMP specified as erasing an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) * entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) reg[1] |= mac[5] << MAC_BYTE_5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) reg[1] |= mac[4] << MAC_BYTE_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) reg[0] |= mac[3] << MAC_BYTE_3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) reg[0] |= mac[2] << MAC_BYTE_2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) reg[0] |= mac[1] << MAC_BYTE_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) reg[0] |= mac[0] << MAC_BYTE_0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* Write array into the ARL table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) for (i = 0; i < 3; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Setup TX circuit including relevant PAD and driving */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) u32 ncpo1, ssc_delta, trgint, i, xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) if (xtal == HWTRAP_XTAL_20MHZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) "%s: MT7530 with a 20MHz XTAL is not supported!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) switch (interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) trgint = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* PLL frequency: 125MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) ncpo1 = 0x0c80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case PHY_INTERFACE_MODE_TRGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) trgint = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (priv->id == ID_MT7621) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) /* PLL frequency: 150MHz: 1.2GBit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (xtal == HWTRAP_XTAL_40MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ncpo1 = 0x0780;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (xtal == HWTRAP_XTAL_25MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) ncpo1 = 0x0a00;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) } else { /* PLL frequency: 250MHz: 2.0Gbit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (xtal == HWTRAP_XTAL_40MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) ncpo1 = 0x0c80;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (xtal == HWTRAP_XTAL_25MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) ncpo1 = 0x1400;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(priv->dev, "xMII interface %d not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) if (xtal == HWTRAP_XTAL_25MHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ssc_delta = 0x57;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ssc_delta = 0x87;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) P6_INTF_MODE(trgint));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /* Lower Tx Driving for TRGMII path */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) for (i = 0 ; i < NUM_TRGMII_CTRL ; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) mt7530_write(priv, MT7530_TRGMII_TD_ODT(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) TD_DM_DRVP(8) | TD_DM_DRVN(8));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) /* Setup core clock for MT7530 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) if (!trgint) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* Disable MT7530 core clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* Disable PLL, since phy_device has not yet been created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * provided for phy_[read,write]_mmd_indirect is called, we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * provide our own core_write_mmd_indirect to complete this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) core_write_mmd_indirect(priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) CORE_GSWPLL_GRP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) MDIO_MMD_VEND2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /* Set core clock into 500Mhz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) core_write(priv, CORE_GSWPLL_GRP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) RG_GSWPLL_POSDIV_500M(1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) RG_GSWPLL_FBKDIV_500M(25));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) /* Enable PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) core_write(priv, CORE_GSWPLL_GRP1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) RG_GSWPLL_EN_PRE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) RG_GSWPLL_POSDIV_200M(2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) RG_GSWPLL_FBKDIV_200M(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* Enable MT7530 core clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /* Setup the MT7530 TRGMII Tx Clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) core_write(priv, CORE_PLL_GROUP4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) RG_SYSPLL_BIAS_LPF_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) core_write(priv, CORE_PLL_GROUP2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) RG_SYSPLL_POSDIV(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) core_write(priv, CORE_PLL_GROUP7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) RG_LCDDS_PWDB | RG_LCDDS_ISO_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) core_set(priv, CORE_TRGMII_GSW_CLK_CG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) REG_GSWCK_EN | REG_TRGMIICK_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!trgint)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mt7530_rmw(priv, MT7530_TRGMII_RD(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) RD_TAP_MASK, RD_TAP(16));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) val = mt7530_read(priv, MT7531_TOP_SIG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) return (val & PAD_DUAL_SGMII_EN) != 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 top_sig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 hwstrap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 xtal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (mt7531_dual_sgmii_supported(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) val = mt7530_read(priv, MT7531_CREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) hwstrap = mt7530_read(priv, MT7531_HWTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) if ((val & CHIP_REV_M) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) HWTRAP_XTAL_FSEL_25MHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* Step 1 : Disable MT7531 COREPLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) val = mt7530_read(priv, MT7531_PLLGP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) val &= ~EN_COREPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) mt7530_write(priv, MT7531_PLLGP_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Step 2: switch to XTAL output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) val = mt7530_read(priv, MT7531_PLLGP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) val |= SW_CLKSW;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) mt7530_write(priv, MT7531_PLLGP_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) val &= ~RG_COREPLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /* Step 3: disable PLLGP and enable program PLLGP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) val = mt7530_read(priv, MT7531_PLLGP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) val |= SW_PLLGP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) mt7530_write(priv, MT7531_PLLGP_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) /* Step 4: program COREPLL output frequency to 500MHz */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) val &= ~RG_COREPLL_POSDIV_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val |= 2 << RG_COREPLL_POSDIV_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) usleep_range(25, 35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) switch (xtal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) case HWTRAP_XTAL_FSEL_25MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val &= ~RG_COREPLL_SDM_PCW_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) val |= 0x140000 << RG_COREPLL_SDM_PCW_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) case HWTRAP_XTAL_FSEL_40MHZ:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val &= ~RG_COREPLL_SDM_PCW_M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) val |= 0x190000 << RG_COREPLL_SDM_PCW_S;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* Set feedback divide ratio update signal to high */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val |= RG_COREPLL_SDM_PCW_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Wait for at least 16 XTAL clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) usleep_range(10, 20);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /* Step 5: set feedback divide ratio update signal to low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) val &= ~RG_COREPLL_SDM_PCW_CHG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /* Enable 325M clock for SGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /* Enable 250SSC clock for RGMII */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) /* Step 6: Enable MT7531 PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) val = mt7530_read(priv, MT7531_PLLGP_CR0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) val |= RG_COREPLL_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) mt7530_write(priv, MT7531_PLLGP_CR0, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) val = mt7530_read(priv, MT7531_PLLGP_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) val |= EN_COREPLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) mt7530_write(priv, MT7531_PLLGP_EN, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) usleep_range(25, 35);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) mt7530_mib_reset(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) return mdiobus_read_nested(priv->bus, port, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return mdiobus_write_nested(priv->bus, port, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) u32 reg, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) MT7531_MDIO_DEV_ADDR(devad) | regnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) MT7531_MDIO_DEV_ADDR(devad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) ret = val & MT7531_MDIO_RW_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) int regnum, u32 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 val, reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) MT7531_MDIO_DEV_ADDR(devad) | regnum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MT7531_MDIO_DEV_ADDR(devad) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) MT7531_MDIO_REG_ADDR(regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) !(val & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) ret = val & MT7531_MDIO_RW_DATA_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct mii_bus *bus = priv->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) !(reg & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) MT7531_MDIO_REG_ADDR(regnum) | data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) !(reg & MT7531_PHY_ACS_ST), 20, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) mutex_unlock(&bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int devad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (regnum & MII_ADDR_C45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) ret = mt7531_ind_c45_phy_read(priv, port, devad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) regnum & MII_REGADDR_C45_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) ret = mt7531_ind_c22_phy_read(priv, port, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) u16 data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) int devad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (regnum & MII_ADDR_C45) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) ret = mt7531_ind_c45_phy_write(priv, port, devad,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) regnum & MII_REGADDR_C45_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) ret = mt7531_ind_c22_phy_write(priv, port, regnum, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) uint8_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (stringset != ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) ETH_GSTRING_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mt7530_get_ethtool_stats(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) uint64_t *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) const struct mt7530_mib_desc *mib;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) u32 reg, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u64 hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) mib = &mt7530_mib[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) data[i] = mt7530_read(priv, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (mib->size == 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) hi = mt7530_read(priv, reg + 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) data[i] |= hi << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) if (sset != ETH_SS_STATS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) return ARRAY_SIZE(mt7530_mib);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) u8 tx_delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) val = mt7530_read(priv, MT7530_MHWTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) switch (priv->p5_intf_sel) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) case P5_INTF_SEL_PHY_P0:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) val |= MHWTRAP_PHY0_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) case P5_INTF_SEL_PHY_P4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /* Setup the MAC by default for the cpu port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) mt7530_write(priv, MT7530_PMCR_P(5), 0x56300);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) case P5_INTF_SEL_GMAC5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) val &= ~MHWTRAP_P5_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case P5_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) dev_err(ds->dev, "Unsupported p5_intf_sel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) priv->p5_intf_sel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) goto unlock_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /* Setup RGMII settings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) if (phy_interface_mode_is_rgmii(interface)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) val |= MHWTRAP_P5_RGMII_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /* P5 RGMII RX Clock Control: delay setting for 1000M */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) /* Don't set delay in DSA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) if (!dsa_is_dsa_port(priv->ds, 5) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) (interface == PHY_INTERFACE_MODE_RGMII_TXID ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) interface == PHY_INTERFACE_MODE_RGMII_ID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) tx_delay = 4; /* n * 0.5 ns */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) /* P5 RGMII TX Clock Control: delay x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) mt7530_write(priv, MT7530_P5RGMIITXCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) CSR_RGMII_TXC_CFG(0x10 + tx_delay));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* reduce P5 RGMII Tx driving, 8mA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) mt7530_write(priv, MT7530_IO_DRV_CR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) mt7530_write(priv, MT7530_MHWTRAP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) priv->p5_interface = interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unlock_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) mt753x_cpu_port_enable(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) /* Setup max capability of CPU port at first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (priv->info->cpu_port_config) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) ret = priv->info->cpu_port_config(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) /* Enable Mediatek header mode on the cpu port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mt7530_write(priv, MT7530_PVC_P(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) PORT_SPEC_TAG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* Unknown multicast frame forwarding to the cpu port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) /* Set CPU port number */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (priv->id == ID_MT7621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* CPU port gets connected to all user ports of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) * the switch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mt7530_write(priv, MT7530_PCR_P(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) PCR_MATRIX(dsa_user_ports(priv->ds)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) mt7530_port_enable(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) struct phy_device *phy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) /* Allow the user port gets connected to the cpu port and also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) * restore the port matrix if the port is the member of a certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) * bridge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) priv->ports[port].enable = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) priv->ports[port].pm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) mt7530_port_disable(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) /* Clear up all port matrix which could be restored in the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) * enablement for the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) priv->ports[port].enable = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) PCR_MATRIX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) u32 stp_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) case BR_STATE_DISABLED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) stp_state = MT7530_STP_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case BR_STATE_BLOCKING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) stp_state = MT7530_STP_BLOCKING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) case BR_STATE_LISTENING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) stp_state = MT7530_STP_LISTENING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) case BR_STATE_LEARNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) stp_state = MT7530_STP_LEARNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) case BR_STATE_FORWARDING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) stp_state = MT7530_STP_FORWARDING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mt7530_port_bridge_join(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct net_device *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) u32 port_bitmap = BIT(MT7530_CPU_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) for (i = 0; i < MT7530_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) /* Add this port to the port matrix of the other ports in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * same bridge. If the port is disabled, port matrix is kept
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) * and not being setup until the port becomes enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) if (dsa_is_user_port(ds, i) && i != port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if (dsa_to_port(ds, i)->bridge_dev != bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) if (priv->ports[i].enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) mt7530_set(priv, MT7530_PCR_P(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) PCR_MATRIX(BIT(port)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) priv->ports[i].pm |= PCR_MATRIX(BIT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) port_bitmap |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) /* Add the all other ports to this port matrix. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) if (priv->ports[port].enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) mt7530_rmw(priv, MT7530_PCR_P(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) priv->ports[port].pm |= PCR_MATRIX(port_bitmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) bool all_user_ports_removed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) /* When a port is removed from the bridge, the port would be set up
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) * back to the default as is at initial boot which is a VLAN-unaware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) * port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) MT7530_PORT_MATRIX_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) VLAN_ATTR(MT7530_VLAN_TRANSPARENT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) for (i = 0; i < MT7530_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (dsa_is_user_port(ds, i) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) all_user_ports_removed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) /* CPU port also does the same thing until all user ports belonging to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) * the CPU port get out of VLAN filtering mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (all_user_ports_removed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) PCR_MATRIX(dsa_user_ports(priv->ds)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Trapped into security mode allows packet forwarding through VLAN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) * table lookup. CPU port is set to fallback mode to let untagged
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) * frames pass through.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) if (dsa_is_cpu_port(ds, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) MT7530_PORT_FALLBACK_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) MT7530_PORT_SECURITY_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* Set the port as a user port which is to be able to recognize VID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) * from incoming packets before fetching entry within the VLAN table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) VLAN_ATTR(MT7530_VLAN_USER) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) PVC_EG_TAG(MT7530_VLAN_EG_DISABLED));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) mt7530_port_bridge_leave(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) struct net_device *bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) for (i = 0; i < MT7530_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) /* Remove this port from the port matrix of the other ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) * in the same bridge. If the port is disabled, port matrix
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) * is kept and not being setup until the port becomes enabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) if (dsa_is_user_port(ds, i) && i != port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) if (dsa_to_port(ds, i)->bridge_dev != bridge)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (priv->ports[i].enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) mt7530_clear(priv, MT7530_PCR_P(i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) PCR_MATRIX(BIT(port)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) priv->ports[i].pm &= ~PCR_MATRIX(BIT(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* Set the cpu port to be the only one in the port matrix of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) * this port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) if (priv->ports[port].enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) PCR_MATRIX(BIT(MT7530_CPU_PORT)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) mt7530_port_fdb_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) const unsigned char *addr, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) u8 port_mask = BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) mt7530_port_fdb_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) const unsigned char *addr, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) u8 port_mask = BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) mt7530_port_fdb_dump(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dsa_fdb_dump_cb_t *cb, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) struct mt7530_fdb _fdb = { 0 };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) int cnt = MT7530_NUM_FDB_RECORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) u32 rsp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) if (rsp & ATC_SRCH_HIT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) mt7530_fdb_read(priv, &_fdb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (_fdb.port_mask & BIT(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) } while (--cnt &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) !(rsp & ATC_SRCH_END) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) val = VTCR_BUSY | VTCR_FUNC(cmd) | vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) mt7530_write(priv, MT7530_VTCR, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) ret = readx_poll_timeout(_mt7530_read, &p, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) !(val & VTCR_BUSY), 20, 20000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) dev_err(priv->dev, "poll timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) val = mt7530_read(priv, MT7530_VTCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (val & VTCR_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) dev_err(priv->dev, "read VTCR invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) mt7530_port_vlan_filtering(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) bool vlan_filtering,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct switchdev_trans *trans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) if (switchdev_trans_ph_prepare(trans))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) if (vlan_filtering) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) /* The port is being kept as VLAN-unaware port when bridge is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) * set up with vlan_filtering not being set, Otherwise, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) * port and the corresponding CPU port is required the setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * for becoming a VLAN-aware port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) mt7530_port_set_vlan_aware(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) mt7530_port_set_vlan_unaware(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) mt7530_port_vlan_prepare(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) const struct switchdev_obj_port_vlan *vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) /* nothing needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) mt7530_hw_vlan_add(struct mt7530_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) struct mt7530_hw_vlan_entry *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u8 new_members;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) new_members = entry->old_members | BIT(entry->port) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) BIT(MT7530_CPU_PORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) /* Validate the entry with independent learning, create egress tag per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) * VLAN and joining the port as one of the port members.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) mt7530_write(priv, MT7530_VAWD1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) /* Decide whether adding tag or not for those outgoing packets from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) * port inside the VLAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) MT7530_VLAN_EGRESS_TAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) mt7530_rmw(priv, MT7530_VAWD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) ETAG_CTRL_P_MASK(entry->port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) ETAG_CTRL_P(entry->port, val));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* CPU port is always taken as a tagged port for serving more than one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) * VLANs across and also being applied with egress type stack mode for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) * that VLAN tags would be appended after hardware special tag used as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) * DSA tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) mt7530_rmw(priv, MT7530_VAWD2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) ETAG_CTRL_P_MASK(MT7530_CPU_PORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) ETAG_CTRL_P(MT7530_CPU_PORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) MT7530_VLAN_EGRESS_STACK));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) mt7530_hw_vlan_del(struct mt7530_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) struct mt7530_hw_vlan_entry *entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) u8 new_members;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) new_members = entry->old_members & ~BIT(entry->port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) val = mt7530_read(priv, MT7530_VAWD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) if (!(val & VLAN_VALID)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) "Cannot be deleted due to invalid entry\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) /* If certain member apart from CPU port is still alive in the VLAN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) * the entry would be kept valid. Otherwise, the entry is got to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) * disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (new_members && new_members != BIT(MT7530_CPU_PORT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) VLAN_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) mt7530_write(priv, MT7530_VAWD1, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) mt7530_write(priv, MT7530_VAWD1, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) mt7530_write(priv, MT7530_VAWD2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) struct mt7530_hw_vlan_entry *entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) mt7530_vlan_op vlan_op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) /* Fetch entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) val = mt7530_read(priv, MT7530_VAWD1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /* Manipulate entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) vlan_op(priv, entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) /* Flush result to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) mt7530_port_vlan_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) const struct switchdev_obj_port_vlan *vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct mt7530_hw_vlan_entry new_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) u16 vid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) mt7530_hw_vlan_entry_init(&new_entry, port, untagged);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) mt7530_hw_vlan_update(priv, vid, &new_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) mt7530_hw_vlan_add);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) if (pvid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) G0_PORT_VID(vlan->vid_end));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) priv->ports[port].pvid = vlan->vid_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) mt7530_port_vlan_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) const struct switchdev_obj_port_vlan *vlan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct mt7530_hw_vlan_entry target_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) u16 vid, pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) mutex_lock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) pvid = priv->ports[port].pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) mt7530_hw_vlan_entry_init(&target_entry, port, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) mt7530_hw_vlan_update(priv, vid, &target_entry,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) mt7530_hw_vlan_del);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) /* PVID is being restored to the default whenever the PVID port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) * is being removed from the VLAN.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (pvid == vid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) pvid = G0_PORT_VID_DEF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) priv->ports[port].pvid = pvid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) mutex_unlock(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) static int mt753x_mirror_port_get(unsigned int id, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) MIRROR_PORT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) static int mt753x_mirror_port_set(unsigned int id, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) MIRROR_PORT(val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) static int mt753x_port_mirror_add(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) struct dsa_mall_mirror_tc_entry *mirror,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) bool ingress)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) int monitor_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) /* Check for existent entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* MT7530 only supports one monitor port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) monitor_port = mt753x_mirror_port_get(priv->id, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (val & MT753X_MIRROR_EN(priv->id) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) monitor_port != mirror->to_local_port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) return -EEXIST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) val |= MT753X_MIRROR_EN(priv->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) val &= ~MT753X_MIRROR_MASK(priv->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) val = mt7530_read(priv, MT7530_PCR_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (ingress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) val |= PORT_RX_MIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) priv->mirror_rx |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) val |= PORT_TX_MIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) priv->mirror_tx |= BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) mt7530_write(priv, MT7530_PCR_P(port), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) static void mt753x_port_mirror_del(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) struct dsa_mall_mirror_tc_entry *mirror)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) val = mt7530_read(priv, MT7530_PCR_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) if (mirror->ingress) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) val &= ~PORT_RX_MIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) priv->mirror_rx &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) val &= ~PORT_TX_MIR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) priv->mirror_tx &= ~BIT(port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) mt7530_write(priv, MT7530_PCR_P(port), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (!priv->mirror_rx && !priv->mirror_tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) val &= ~MT753X_MIRROR_EN(priv->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static enum dsa_tag_protocol
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) mtk_get_tag_protocol(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) enum dsa_tag_protocol mp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) if (port != MT7530_CPU_PORT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) dev_warn(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) "port not matched with tagging CPU port\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) return DSA_TAG_PROTO_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) return DSA_TAG_PROTO_MTK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) mt7530_setup(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) struct device_node *phy_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) struct device_node *mac_np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) phy_interface_t interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) u32 id, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* The parent node of master netdev which holds the common system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) * controller also is the container for two GMACs nodes representing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) * as two netdev instances.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) ds->configure_vlan_while_not_filtering = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (priv->id == ID_MT7530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) regulator_set_voltage(priv->core_pwr, 1000000, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = regulator_enable(priv->core_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) "Failed to enable core power: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) regulator_set_voltage(priv->io_pwr, 3300000, 3300000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) ret = regulator_enable(priv->io_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) dev_err(priv->dev, "Failed to enable io pwr: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) /* Reset whole chip through gpio pin or memory-mapped registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) * different type of hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) if (priv->mcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) reset_control_assert(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) reset_control_deassert(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) gpiod_set_value_cansleep(priv->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) gpiod_set_value_cansleep(priv->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* Waiting for MT7530 got to stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) 20, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) dev_err(priv->dev, "reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) id = mt7530_read(priv, MT7530_CREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) id >>= CHIP_NAME_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) if (id != MT7530_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) dev_err(priv->dev, "chip %x can't be supported\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) /* Reset the switch through internal reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) mt7530_write(priv, MT7530_SYS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) SYS_CTRL_REG_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) val = mt7530_read(priv, MT7530_MHWTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) val |= MHWTRAP_MANUAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) mt7530_write(priv, MT7530_MHWTRAP, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) priv->p6_interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /* Enable and reset MIB counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) mt7530_mib_reset(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) for (i = 0; i < MT7530_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) /* Disable forwarding by default on all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) PCR_MATRIX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (dsa_is_cpu_port(ds, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) ret = mt753x_cpu_port_enable(ds, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) mt7530_port_disable(ds, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) /* Enable consistent egress tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) /* Setup port 5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) priv->p5_intf_sel = P5_DISABLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) if (!dsa_is_unused_port(ds, 5)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) if (ret && ret != -ENODEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) /* Scan the ethernet nodes. look for GMAC1, lookup used phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) for_each_child_of_node(dn, mac_np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) if (!of_device_is_compatible(mac_np,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) "mediatek,eth-mac"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) ret = of_property_read_u32(mac_np, "reg", &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (ret < 0 || id != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) phy_node = of_parse_phandle(mac_np, "phy-handle", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (!phy_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) if (phy_node->parent == priv->dev->of_node->parent) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) ret = of_get_phy_mode(mac_np, &interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) if (ret && ret != -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) of_node_put(mac_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) id = of_mdio_parse_addr(ds->dev, phy_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) if (id == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) priv->p5_intf_sel = P5_INTF_SEL_PHY_P0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (id == 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) priv->p5_intf_sel = P5_INTF_SEL_PHY_P4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) of_node_put(mac_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) of_node_put(phy_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) mt7530_setup_port5(ds, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) /* Flush the FDB table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) mt7531_setup(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) struct mt7530_dummy_poll p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) u32 val, id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) /* Reset whole chip through gpio pin or memory-mapped registers for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) * different type of hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) if (priv->mcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) reset_control_assert(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) reset_control_deassert(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) gpiod_set_value_cansleep(priv->reset, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) usleep_range(1000, 1100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) gpiod_set_value_cansleep(priv->reset, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) /* Waiting for MT7530 got to stable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) 20, 1000000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) dev_err(priv->dev, "reset timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) id = mt7530_read(priv, MT7531_CREV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) id >>= CHIP_NAME_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (id != MT7531_ID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) dev_err(priv->dev, "chip %x can't be supported\n", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) /* Reset the switch through internal reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) mt7530_write(priv, MT7530_SYS_CTRL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) SYS_CTRL_REG_RST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) if (mt7531_dual_sgmii_supported(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) /* Let ds->slave_mii_bus be able to access external phy. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) MT7531_EXT_P_MDC_11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) MT7531_EXT_P_MDIO_12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) priv->p5_intf_sel = P5_INTF_SEL_GMAC5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dev_dbg(ds->dev, "P5 support %s interface\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) p5_intf_modes(priv->p5_intf_sel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) MT7531_GPIO0_INTERRUPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) /* Let phylink decide the interface later. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) priv->p5_interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) priv->p6_interface = PHY_INTERFACE_MODE_NA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) /* Enable PHY core PLL, since phy_device has not yet been created
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) * provided for phy_[read,write]_mmd_indirect is called, we provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) * our own mt7531_ind_mmd_phy_[read,write] to complete this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) * function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) MDIO_MMD_VEND2, CORE_PLL_GROUP4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) val |= MT7531_PHY_PLL_BYPASS_MODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) val &= ~MT7531_PHY_PLL_OFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) CORE_PLL_GROUP4, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) /* BPDU to CPU port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) BIT(MT7530_CPU_PORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) MT753X_BPDU_CPU_ONLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) /* Enable and reset MIB counters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) mt7530_mib_reset(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) for (i = 0; i < MT7530_NUM_PORTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) /* Disable forwarding by default on all ports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) PCR_MATRIX_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (dsa_is_cpu_port(ds, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) ret = mt753x_cpu_port_enable(ds, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) mt7530_port_disable(ds, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) /* Enable consistent egress tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) ds->configure_vlan_while_not_filtering = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) /* Flush the FDB table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) mt7530_phy_mode_supported(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) case 0 ... 4: /* Internal phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) if (state->interface != PHY_INTERFACE_MODE_GMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (!phy_interface_mode_is_rgmii(state->interface) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) state->interface != PHY_INTERFACE_MODE_MII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) state->interface != PHY_INTERFACE_MODE_GMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) case 6: /* 1st cpu port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) if (state->interface != PHY_INTERFACE_MODE_RGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) state->interface != PHY_INTERFACE_MODE_TRGMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) mt7531_phy_mode_supported(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) case 0 ... 4: /* Internal phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) if (state->interface != PHY_INTERFACE_MODE_GMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) if (mt7531_is_rgmii_port(priv, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) return phy_interface_mode_is_rgmii(state->interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) case 6: /* 1st cpu port supports sgmii/8023z only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) if (state->interface != PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) !phy_interface_mode_is_8023z(state->interface))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dev_err(priv->dev, "%s: unsupported port: %i\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) static bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) mt753x_phy_mode_supported(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) return priv->info->phy_mode_supported(ds, port, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return priv->info->pad_setup(ds, state->interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /* Only need to setup port5. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (port != 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) mt7530_setup_port5(priv->ds, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) struct phy_device *phydev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (!mt7531_is_rgmii_port(priv, port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) dev_err(priv->dev, "RGMII mode is not available for port %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) val = mt7530_read(priv, MT7531_CLKGEN_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) val |= GP_CLK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) val &= ~GP_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) val |= GP_MODE(MT7531_GP_MODE_RGMII);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) val &= ~CLK_SKEW_IN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) val &= ~CLK_SKEW_OUT_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) /* Do not adjust rgmii delay when vendor phy driver presents. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) if (!phydev || phy_driver_is_genphy(phydev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) switch (interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) val |= TXCLK_NO_REVERSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) val |= RXCLK_NO_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) case PHY_INTERFACE_MODE_RGMII_RXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) val |= TXCLK_NO_REVERSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) case PHY_INTERFACE_MODE_RGMII_TXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) val |= RXCLK_NO_DELAY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) case PHY_INTERFACE_MODE_RGMII_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) mt7530_write(priv, MT7531_CLKGEN_CTRL, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) unsigned long *supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) /* Port5 supports ethier RGMII or SGMII.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * Port6 supports SGMII only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) if (mt7531_is_rgmii_port(priv, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) phylink_set(supported, 1000baseX_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) phylink_set(supported, 2500baseX_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) phylink_set(supported, 2500baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) unsigned int mode, phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) int speed, int duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) /* For adjusting speed and duplex of SGMII force mode. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) if (interface != PHY_INTERFACE_MODE_SGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) phylink_autoneg_inband(mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) /* SGMII force mode setting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) val = mt7530_read(priv, MT7531_SGMII_MODE(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) val &= ~MT7531_SGMII_IF_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) case SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) val |= MT7531_SGMII_FORCE_SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) val |= MT7531_SGMII_FORCE_SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) val |= MT7531_SGMII_FORCE_SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) /* MT7531 SGMII 1G force mode can only work in full duplex mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) if ((speed == SPEED_10 || speed == SPEED_100) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) duplex != DUPLEX_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) val |= MT7531_SGMII_FORCE_HALF_DUPLEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) mt7530_write(priv, MT7531_SGMII_MODE(port), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) static bool mt753x_is_mac_port(u32 port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) return (port == 5 || port == 6);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (!mt753x_is_mac_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) MT7531_SGMII_PHYA_PWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) val &= ~MT7531_RG_TPHY_SPEED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) * encoding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) mt7530_rmw(priv, MT7531_SGMII_MODE(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) MT7531_SGMII_FORCE_SPEED_1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) if (!mt753x_is_mac_port(port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) MT7531_SGMII_PHYA_PWD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) mt7530_set(priv, MT7531_SGMII_MODE(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) MT7531_SGMII_REMOTE_FAULT_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) MT7531_SGMII_SPEED_DUPLEX_AN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) MT7531_SGMII_TX_CONFIG_MASK, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) /* Only restart AN when AN is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) if (val & MT7531_SGMII_AN_ENABLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) val |= MT7531_SGMII_AN_RESTART;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) struct phy_device *phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) struct dsa_port *dp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) if (!mt753x_is_mac_port(port)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) dev_err(priv->dev, "port %d is not a MAC port\n", port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) switch (interface) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) case PHY_INTERFACE_MODE_RGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) case PHY_INTERFACE_MODE_RGMII_ID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) case PHY_INTERFACE_MODE_RGMII_RXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) case PHY_INTERFACE_MODE_RGMII_TXID:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) dp = dsa_to_port(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) phydev = dp->slave->phydev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) return mt7531_rgmii_setup(priv, port, interface, phydev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) case PHY_INTERFACE_MODE_SGMII:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return mt7531_sgmii_setup_mode_an(priv, port, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) case PHY_INTERFACE_MODE_NA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) case PHY_INTERFACE_MODE_1000BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) case PHY_INTERFACE_MODE_2500BASEX:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) if (phylink_autoneg_inband(mode))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) return mt7531_sgmii_setup_mode_force(priv, port, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) return priv->info->mac_port_config(ds, port, mode, state->interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) const struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) u32 mcr_cur, mcr_new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (!mt753x_phy_mode_supported(ds, port, state))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) case 0 ... 4: /* Internal phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) if (state->interface != PHY_INTERFACE_MODE_GMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) if (priv->p5_interface == state->interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) if (mt753x_mac_config(ds, port, mode, state) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) if (priv->p5_intf_sel != P5_DISABLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) priv->p5_interface = state->interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) case 6: /* 1st cpu port */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (priv->p6_interface == state->interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) mt753x_pad_setup(ds, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) if (mt753x_mac_config(ds, port, mode, state) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) goto unsupported;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) priv->p6_interface = state->interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) unsupported:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) dev_err(ds->dev, "%s: unsupported %s port: %i\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) __func__, phy_modes(state->interface), port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (phylink_autoneg_inband(mode) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) state->interface != PHY_INTERFACE_MODE_SGMII) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) dev_err(ds->dev, "%s: in-band negotiation unsupported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) mcr_new = mcr_cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) mcr_new &= ~PMCR_LINK_SETTINGS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) /* Are we connected to external phy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) if (port == 5 && dsa_is_user_port(ds, 5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) mcr_new |= PMCR_EXT_PHY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) if (mcr_new != mcr_cur)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) mt7530_write(priv, MT7530_PMCR_P(port), mcr_new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) if (!priv->info->mac_pcs_an_restart)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) priv->info->mac_pcs_an_restart(ds, port);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) phy_interface_t interface)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) unsigned int mode, phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) int speed, int duplex)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) if (!priv->info->mac_pcs_link_up)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) unsigned int mode,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) phy_interface_t interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) struct phy_device *phydev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) int speed, int duplex,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) bool tx_pause, bool rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) u32 mcr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) /* MT753x MAC works in 1G full duplex mode for all up-clocked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) * variants.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) if (interface == PHY_INTERFACE_MODE_TRGMII ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) (phy_interface_mode_is_8023z(interface))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) switch (speed) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) case SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) mcr |= PMCR_FORCE_SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) case SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) mcr |= PMCR_FORCE_SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) if (duplex == DUPLEX_FULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) mcr |= PMCR_FORCE_FDX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (tx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) mcr |= PMCR_TX_FC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (rx_pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) mcr |= PMCR_RX_FC_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) mt7530_set(priv, MT7530_PMCR_P(port), mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) mt7531_cpu_port_config(struct dsa_switch *ds, int port)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) phy_interface_t interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) int speed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) switch (port) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) case 5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) if (mt7531_is_rgmii_port(priv, port))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) interface = PHY_INTERFACE_MODE_RGMII;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) interface = PHY_INTERFACE_MODE_2500BASEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) priv->p5_interface = interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) interface = PHY_INTERFACE_MODE_2500BASEX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) mt7531_pad_setup(ds, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) priv->p6_interface = interface;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (interface == PHY_INTERFACE_MODE_2500BASEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) speed = SPEED_2500;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) mt7530_write(priv, MT7530_PMCR_P(port),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) PMCR_CPU_PORT_SETTING(priv->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) speed, DUPLEX_FULL, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) mt7530_mac_port_validate(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) unsigned long *supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) if (port == 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) phylink_set(supported, 1000baseX_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) static void mt7531_mac_port_validate(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) unsigned long *supported)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) mt7531_sgmii_validate(priv, port, supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) mt753x_phylink_validate(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) unsigned long *supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) if (state->interface != PHY_INTERFACE_MODE_NA &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) !mt753x_phy_mode_supported(ds, port, state)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) linkmode_zero(supported);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) phylink_set_port_modes(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if (state->interface != PHY_INTERFACE_MODE_TRGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) !phy_interface_mode_is_8023z(state->interface)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) phylink_set(mask, 10baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) phylink_set(mask, 10baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) phylink_set(mask, 100baseT_Half);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) phylink_set(mask, 100baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) phylink_set(mask, Autoneg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) /* This switch only supports 1G full-duplex. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) if (state->interface != PHY_INTERFACE_MODE_MII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) phylink_set(mask, 1000baseT_Full);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) priv->info->mac_port_validate(ds, port, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) phylink_set(mask, Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) phylink_set(mask, Asym_Pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) linkmode_and(supported, supported, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) linkmode_and(state->advertising, state->advertising, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) /* We can only operate at 2500BaseX or 1000BaseX. If requested
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) * to advertise both, only report advertising at 2500BaseX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) phylink_helper_basex_speed(state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) u32 pmsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) if (port < 0 || port >= MT7530_NUM_PORTS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) pmsr = mt7530_read(priv, MT7530_PMSR_P(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) state->link = (pmsr & PMSR_LINK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) state->an_complete = state->link;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) state->duplex = !!(pmsr & PMSR_DPX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) switch (pmsr & PMSR_SPEED_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) case PMSR_SPEED_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) state->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) case PMSR_SPEED_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) state->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) case PMSR_SPEED_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) state->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) state->speed = SPEED_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) if (pmsr & PMSR_RX_FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) state->pause |= MLO_PAUSE_RX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) if (pmsr & PMSR_TX_FC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) state->pause |= MLO_PAUSE_TX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) u32 status, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) u16 config_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) state->link = !!(status & MT7531_SGMII_LINK_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) if (state->interface == PHY_INTERFACE_MODE_SGMII &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) (status & MT7531_SGMII_AN_ENABLE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) config_reg = val >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) switch (config_reg & LPA_SGMII_SPD_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) case LPA_SGMII_1000:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) state->speed = SPEED_1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) case LPA_SGMII_100:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) state->speed = SPEED_100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) case LPA_SGMII_10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) state->speed = SPEED_10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) dev_err(priv->dev, "invalid sgmii PHY speed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) state->link = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) if (config_reg & LPA_SGMII_FULL_DUPLEX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) state->duplex = DUPLEX_FULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) state->duplex = DUPLEX_HALF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) if (state->interface == PHY_INTERFACE_MODE_SGMII)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) return mt7531_sgmii_pcs_get_state_an(priv, port, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) return -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) struct phylink_link_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) return priv->info->mac_port_get_state(ds, port, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) mt753x_setup(struct dsa_switch *ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) return priv->info->sw_setup(ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) mt753x_phy_read(struct dsa_switch *ds, int port, int regnum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) return priv->info->phy_read(ds, port, regnum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) struct mt7530_priv *priv = ds->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) return priv->info->phy_write(ds, port, regnum, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static const struct dsa_switch_ops mt7530_switch_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) .get_tag_protocol = mtk_get_tag_protocol,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .setup = mt753x_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .get_strings = mt7530_get_strings,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) .phy_read = mt753x_phy_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) .phy_write = mt753x_phy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .get_ethtool_stats = mt7530_get_ethtool_stats,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .get_sset_count = mt7530_get_sset_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .port_enable = mt7530_port_enable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) .port_disable = mt7530_port_disable,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .port_stp_state_set = mt7530_stp_state_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) .port_bridge_join = mt7530_port_bridge_join,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) .port_bridge_leave = mt7530_port_bridge_leave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) .port_fdb_add = mt7530_port_fdb_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) .port_fdb_del = mt7530_port_fdb_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) .port_fdb_dump = mt7530_port_fdb_dump,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) .port_vlan_filtering = mt7530_port_vlan_filtering,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) .port_vlan_prepare = mt7530_port_vlan_prepare,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) .port_vlan_add = mt7530_port_vlan_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) .port_vlan_del = mt7530_port_vlan_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .port_mirror_add = mt753x_port_mirror_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .port_mirror_del = mt753x_port_mirror_del,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .phylink_validate = mt753x_phylink_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .phylink_mac_link_state = mt753x_phylink_mac_link_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) .phylink_mac_config = mt753x_phylink_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .phylink_mac_an_restart = mt753x_phylink_mac_an_restart,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) .phylink_mac_link_down = mt753x_phylink_mac_link_down,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .phylink_mac_link_up = mt753x_phylink_mac_link_up,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) static const struct mt753x_info mt753x_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) [ID_MT7621] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .id = ID_MT7621,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .sw_setup = mt7530_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) .phy_read = mt7530_phy_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .phy_write = mt7530_phy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) .pad_setup = mt7530_pad_clk_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) .phy_mode_supported = mt7530_phy_mode_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) .mac_port_validate = mt7530_mac_port_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) .mac_port_get_state = mt7530_phylink_mac_link_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) .mac_port_config = mt7530_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) [ID_MT7530] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) .id = ID_MT7530,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) .sw_setup = mt7530_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .phy_read = mt7530_phy_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .phy_write = mt7530_phy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .pad_setup = mt7530_pad_clk_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .phy_mode_supported = mt7530_phy_mode_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) .mac_port_validate = mt7530_mac_port_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .mac_port_get_state = mt7530_phylink_mac_link_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .mac_port_config = mt7530_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) [ID_MT7531] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .id = ID_MT7531,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .sw_setup = mt7531_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) .phy_read = mt7531_ind_phy_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .phy_write = mt7531_ind_phy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) .pad_setup = mt7531_pad_setup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) .cpu_port_config = mt7531_cpu_port_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) .phy_mode_supported = mt7531_phy_mode_supported,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) .mac_port_validate = mt7531_mac_port_validate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) .mac_port_get_state = mt7531_phylink_mac_link_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) .mac_port_config = mt7531_mac_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) .mac_pcs_an_restart = mt7531_sgmii_restart_an,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) .mac_pcs_link_up = mt7531_sgmii_link_up_force,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) static const struct of_device_id mt7530_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) MODULE_DEVICE_TABLE(of, mt7530_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) mt7530_probe(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) struct mt7530_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) struct device_node *dn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) dn = mdiodev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) if (!priv->ds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) priv->ds->dev = &mdiodev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) priv->ds->num_ports = MT7530_NUM_PORTS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) /* Use medatek,mcm property to distinguish hardware type that would
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) * casues a little bit differences on power-on sequence.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) priv->mcm = of_property_read_bool(dn, "mediatek,mcm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (priv->mcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) if (IS_ERR(priv->rstc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return PTR_ERR(priv->rstc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) /* Get the hardware identifier from the devicetree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) * We will need it for some of the clock and regulator setup.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) priv->info = of_device_get_match_data(&mdiodev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) if (!priv->info)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) /* Sanity check if these required device operations are filled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) * properly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) if (!priv->info->sw_setup || !priv->info->pad_setup ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) !priv->info->phy_read || !priv->info->phy_write ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) !priv->info->phy_mode_supported ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) !priv->info->mac_port_validate ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) !priv->info->mac_port_get_state || !priv->info->mac_port_config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) priv->id = priv->info->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (priv->id == ID_MT7530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) if (IS_ERR(priv->core_pwr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) return PTR_ERR(priv->core_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) if (IS_ERR(priv->io_pwr))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) return PTR_ERR(priv->io_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) /* Not MCM that indicates switch works as the remote standalone
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) * integrated circuit so the GPIO pin would be used to complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) * the reset, otherwise memory-mapped register accessing used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) * through syscon provides in the case of MCM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) if (!priv->mcm) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) GPIOD_OUT_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (IS_ERR(priv->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) dev_err(&mdiodev->dev, "Couldn't get our reset line\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) return PTR_ERR(priv->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) priv->bus = mdiodev->bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) priv->dev = &mdiodev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) priv->ds->priv = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) priv->ds->ops = &mt7530_switch_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) mutex_init(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) dev_set_drvdata(&mdiodev->dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) return dsa_register_switch(priv->ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) mt7530_remove(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) ret = regulator_disable(priv->core_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) dev_err(priv->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) "Failed to disable core power: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) ret = regulator_disable(priv->io_pwr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) dev_err(priv->dev, "Failed to disable io pwr: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) dsa_unregister_switch(priv->ds);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) mutex_destroy(&priv->reg_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) static struct mdio_driver mt7530_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .probe = mt7530_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) .remove = mt7530_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) .mdiodrv.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .name = "mt7530",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .of_match_table = mt7530_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) mdio_module_driver(mt7530_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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