^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Pengutronix, Juergen Borleis <kernel@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Partially based on a patch from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (c) 2014 Stefan Roese <sr@denx.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mdio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/phy.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include "lan9303.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Generate phy-addr and -reg from the input address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PHY_ADDR(x) ((((x) >> 6) + 0x10) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PHY_REG(x) (((x) >> 1) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) struct lan9303_mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct mdio_device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) struct lan9303 chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) static void lan9303_mdio_real_write(struct mdio_device *mdio, int reg, u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mdio->bus->write(mdio->bus, PHY_ADDR(reg), PHY_REG(reg), val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static int lan9303_mdio_write(void *ctx, uint32_t reg, uint32_t val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) reg <<= 2; /* reg num to offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mutex_lock(&sw_dev->device->bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) lan9303_mdio_real_write(sw_dev->device, reg, val & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) lan9303_mdio_real_write(sw_dev->device, reg + 2, (val >> 16) & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mutex_unlock(&sw_dev->device->bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static u16 lan9303_mdio_real_read(struct mdio_device *mdio, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) return mdio->bus->read(mdio->bus, PHY_ADDR(reg), PHY_REG(reg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) static int lan9303_mdio_read(void *ctx, uint32_t reg, uint32_t *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) struct lan9303_mdio *sw_dev = (struct lan9303_mdio *)ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) reg <<= 2; /* reg num to offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) mutex_lock(&sw_dev->device->bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) *val = lan9303_mdio_real_read(sw_dev->device, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *val |= (lan9303_mdio_real_read(sw_dev->device, reg + 2) << 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) mutex_unlock(&sw_dev->device->bus->mdio_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int lan9303_mdio_phy_write(struct lan9303 *chip, int phy, int reg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u16 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct lan9303_mdio *sw_dev = dev_get_drvdata(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) return mdiobus_write_nested(sw_dev->device->bus, phy, reg, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static int lan9303_mdio_phy_read(struct lan9303 *chip, int phy, int reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct lan9303_mdio *sw_dev = dev_get_drvdata(chip->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return mdiobus_read_nested(sw_dev->device->bus, phy, reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) static const struct lan9303_phy_ops lan9303_mdio_phy_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) .phy_read = lan9303_mdio_phy_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) .phy_write = lan9303_mdio_phy_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static const struct regmap_config lan9303_mdio_regmap_config = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) .reg_bits = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) .val_bits = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) .reg_stride = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) .can_multi_write = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) .max_register = 0x0ff, /* address bits 0..1 are not used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) .reg_format_endian = REGMAP_ENDIAN_LITTLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) .volatile_table = &lan9303_register_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) .wr_table = &lan9303_register_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) .rd_table = &lan9303_register_set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) .reg_read = lan9303_mdio_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) .reg_write = lan9303_mdio_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) .cache_type = REGCACHE_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static int lan9303_mdio_probe(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct lan9303_mdio *sw_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) sw_dev = devm_kzalloc(&mdiodev->dev, sizeof(struct lan9303_mdio),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (!sw_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sw_dev->chip.regmap = devm_regmap_init(&mdiodev->dev, NULL, sw_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) &lan9303_mdio_regmap_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) if (IS_ERR(sw_dev->chip.regmap)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) ret = PTR_ERR(sw_dev->chip.regmap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) dev_err(&mdiodev->dev, "regmap init failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* link forward and backward */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) sw_dev->device = mdiodev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dev_set_drvdata(&mdiodev->dev, sw_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) sw_dev->chip.dev = &mdiodev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) sw_dev->chip.ops = &lan9303_mdio_phy_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) ret = lan9303_probe(&sw_dev->chip, mdiodev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) if (ret != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) dev_info(&mdiodev->dev, "LAN9303 MDIO driver loaded successfully\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) static void lan9303_mdio_remove(struct mdio_device *mdiodev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct lan9303_mdio *sw_dev = dev_get_drvdata(&mdiodev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!sw_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) lan9303_remove(&sw_dev->chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /*-------------------------------------------------------------------------*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) static const struct of_device_id lan9303_mdio_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) { .compatible = "smsc,lan9303-mdio" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) { /* sentinel */ },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) MODULE_DEVICE_TABLE(of, lan9303_mdio_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static struct mdio_driver lan9303_mdio_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .mdiodrv.driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .name = "LAN9303_MDIO",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .of_match_table = of_match_ptr(lan9303_mdio_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) .probe = lan9303_mdio_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) .remove = lan9303_mdio_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) mdio_module_driver(lan9303_mdio_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) MODULE_AUTHOR("Stefan Roese <sr@denx.de>, Juergen Borleis <kernel@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) MODULE_DESCRIPTION("Driver for SMSC/Microchip LAN9303 three port ethernet switch in MDIO managed mode");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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