^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __DSA_LOOP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __DSA_LOOP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) struct dsa_chip_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) struct dsa_loop_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* Must be first, such that dsa_register_switch() can access this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * without gory pointer manipulations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) struct dsa_chip_data cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) unsigned int enabled_ports;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) const char *netdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DSA_LOOP_NUM_PORTS 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DSA_LOOP_CPU_PORT (DSA_LOOP_NUM_PORTS - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #endif /* __DSA_LOOP_H */